diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMAF_CFG1_BaseDesign.job
index 569bc8a..5c6f9e0 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMAF_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMAF_CFG1_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG1_BaseDesign.job
index 25f254c..493af8e 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG1_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG2_BaseDesign.job
index 7c892a1..77bbd38 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG2_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32IMA_CFG2_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG1_BaseDesign.job
index 2ab19f4..cef4d31 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG1_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG2_BaseDesign.job
index 27b453d..d39de4f 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG2_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG2_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG3_BaseDesign.job
index 429abb8..fe0ef12 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG3_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG3_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job
index db402e4..b845d53 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_CFG4_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job
index bfca852..0905438 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC1_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job
index b48448e..216154f 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC3_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC4_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC4_BaseDesign.job
index d649486..0181a5e 100644
Binary files a/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC4_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_EVAL_MIV_RV32_DGC4_BaseDesign.job differ
diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
index f44fff6..c5f7e62 100644
--- a/FlashPro_Express_Projects/README.md
+++ b/FlashPro_Express_Projects/README.md
@@ -1,11 +1,11 @@
 # PolarFire Evaluation Kit FPGA Programming Files
 
-This folder contains FlashPro Express v2023.1 projects for the PolarFire Evaluation Kit Mi-V sample designs.
+This folder contains FlashPro Express v2023.2 projects for the PolarFire Evaluation Kit Mi-V sample designs.
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT  
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES  
diff --git a/Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl
index fcce29d..6bb686b 100644
--- a/Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl
+++ b/Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl
@@ -19,7 +19,7 @@ set validConfigs [list "CFG1" "CFG2" "CFG3" "CFG4" "DGC1" "DGC3" "DGC4"]
 set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"]
 set validDieTypes [list "PS" "ES" ""]
 set sdName {BaseDesign}
-set exProgramHex "miv-rv32i-systick-blinky.hex"
+set exProgramHex "miv-rv32-coretimer-timer_interrupt.hex"
 
 # Call procedures to validate user arguments
 set config [verify_config $config]
diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
index c29032a..191af9c 100644
--- a/Libero_Projects/README.md
+++ b/Libero_Projects/README.md
@@ -1,5 +1,5 @@
 # PolarFire Evaluation Kit Mi-V Sample FPGA Designs
-This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the PolarFire Evaluation Kit. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.
+This folder contains Tcl scripts that build Libero SoC v2023.2 design projects for the PolarFire Evaluation Kit. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.
 
 > MI-V Extended Subsystem Design Guide Configurations:
 > * For **Design Guide Configuration - DGC1: SPI Write & Boot** refer to this [DGC1 README](../docs//design_dgc1/README.md)
@@ -7,9 +7,9 @@ This folder contains Tcl scripts that build Libero SoC v2023.1 design projects f
 > * For **Design Guide Configuration - DGC4: Basic Peripherals** refer to this [DGC4 README](../docs//design_dgc4/README.md)
 
 ## Notice
-1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. 
+1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples. 
 
-2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
+2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.
 
 .macro STORE_CONTEXT  
 addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES  
diff --git a/Libero_Projects/import/components/CoreAHBL_C0.tcl b/Libero_Projects/import/components/CoreAHBL_C0.tcl
index 8c37f33..91b67d0 100644
--- a/Libero_Projects/import/components/CoreAHBL_C0.tcl
+++ b/Libero_Projects/import/components/CoreAHBL_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core CoreAHBL_0 to TCL
 # Exporting Create design command for core CoreAHBL_0
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {CoreAHBL_C0} -params {\
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {CoreAHBL_C0} -params {\
 "HADDR_SHG_CFG:1"  \
 "M0_AHBSLOT0ENABLE:false"  \
 "M0_AHBSLOT1ENABLE:false"  \
diff --git a/Libero_Projects/import/components/MIV_ESS_C0.tcl b/Libero_Projects/import/components/MIV_ESS_C0.tcl
index bc55f6d..8b7ef7e 100644
--- a/Libero_Projects/import/components/MIV_ESS_C0.tcl
+++ b/Libero_Projects/import/components/MIV_ESS_C0.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-FCG484I
 # Create and Configure the core component MIV_ESS_0
-create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -download_core -component_name {MIV_ESS_C0} -download_core -params {\
+create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -download_core -component_name {MIV_ESS_C0} -download_core -params {\
 "APBSLOT11ENABLE:false" \
 "APBSLOT12ENABLE:false" \
 "APBSLOT13ENABLE:false" \
diff --git a/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl
index f500318..7ea839a 100644
--- a/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl
+++ b/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG1_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG1_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \
diff --git a/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl
index 979cd11..c0e81fa 100644
--- a/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl
+++ b/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG2_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG2_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \
diff --git a/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl
index 543c8ba..80c8ab6 100644
--- a/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl
+++ b/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl
@@ -1,6 +1,6 @@
 # Exporting core MIV_RV32_CFG3_0 to TCL
 # Exporting Create design command for core MIV_RV32_CFG3_0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:0"  \
diff --git a/Libero_Projects/import/components/cfg4/AHBL_bus.tcl b/Libero_Projects/import/components/cfg4/AHBL_bus.tcl
index 7d91bc5..d87544a 100644
--- a/Libero_Projects/import/components/cfg4/AHBL_bus.tcl
+++ b/Libero_Projects/import/components/cfg4/AHBL_bus.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-1FCG1152I
 # Create and Configure the core component AHBL_bus
-create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {AHBL_bus} -params {\
+create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {AHBL_bus} -params {\
 "HADDR_SHG_CFG:1"  \
 "M0_AHBSLOT0ENABLE:true"  \
 "M0_AHBSLOT1ENABLE:true"  \
diff --git a/Libero_Projects/import/components/cfg4/MIV_RV32_C0.tcl b/Libero_Projects/import/components/cfg4/MIV_RV32_C0.tcl
index 1a36c60..0a46fac 100644
--- a/Libero_Projects/import/components/cfg4/MIV_RV32_C0.tcl
+++ b/Libero_Projects/import/components/cfg4/MIV_RV32_C0.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300TS-1FCG1152I
 # Create and Configure the core component MIV_RV32_C0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x6fff"  \
 "AHB_INITIATOR_TYPE:1"  \
diff --git a/Libero_Projects/import/components/dgc/MIV_RV32_DGC1_C0.tcl b/Libero_Projects/import/components/dgc/MIV_RV32_DGC1_C0.tcl
index 6eaa771..227fecb 100644
--- a/Libero_Projects/import/components/dgc/MIV_RV32_DGC1_C0.tcl
+++ b/Libero_Projects/import/components/dgc/MIV_RV32_DGC1_C0.tcl
@@ -1,5 +1,5 @@
 # Create and Configure the core component MIV_RV32_DGC1_C0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC1_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC1_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \
diff --git a/Libero_Projects/import/components/dgc/MIV_RV32_DGC3_C0.tcl b/Libero_Projects/import/components/dgc/MIV_RV32_DGC3_C0.tcl
index e4f1519..adb0f6a 100644
--- a/Libero_Projects/import/components/dgc/MIV_RV32_DGC3_C0.tcl
+++ b/Libero_Projects/import/components/dgc/MIV_RV32_DGC3_C0.tcl
@@ -1,5 +1,5 @@
 # Create and Configure the core component MIV_RV32_DGC3_C0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC3_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC3_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \
diff --git a/Libero_Projects/import/components/dgc/MIV_RV32_DGC4_C0.tcl b/Libero_Projects/import/components/dgc/MIV_RV32_DGC4_C0.tcl
index 1a4e71e..1842934 100644
--- a/Libero_Projects/import/components/dgc/MIV_RV32_DGC4_C0.tcl
+++ b/Libero_Projects/import/components/dgc/MIV_RV32_DGC4_C0.tcl
@@ -2,7 +2,7 @@
 # Family: PolarFire
 # Part Number: MPF300T-FCG1152I
 # Create and Configure the core component MIV_RV32_DGC4_C0
-create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC4_C0} -params {\
+create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC4_C0} -params {\
 "AHB_END_ADDR_0:0xffff"  \
 "AHB_END_ADDR_1:0x8fff"  \
 "AHB_INITIATOR_TYPE:1"  \
diff --git a/Libero_Projects/import/proc_blocks.tcl b/Libero_Projects/import/proc_blocks.tcl
index 2b02d79..ad0b788 100644
--- a/Libero_Projects/import/proc_blocks.tcl
+++ b/Libero_Projects/import/proc_blocks.tcl
@@ -190,11 +190,10 @@ proc download_required_direct_cores  {hwPlatform softCpu config} {
 	download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
 	download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
-	download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
+	download_core -vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -location {www.microchip-ip.com/repositories/DirectCore}
     if {$softCpu eq "MIV_RV32"} {
-        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore} 
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}
-        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}  
+        download_core -vlnv {Microsemi:MiV:MIV_RV32:3.2.100} -location {www.microchip-ip.com/repositories/DirectCore} 
+        download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore}  
     }
 	if {$softCpu eq "MIV_RV32IMA_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} }
 	if {$softCpu eq "MIV_RV32IMA_L1_AXI"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} }
@@ -241,4 +240,4 @@ proc run_verify_timing { } {
 	run_tool -name {VERIFYTIMING}	
 }
 # Procedure blocks end
-#
\ No newline at end of file
+#
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.hex
new file mode 100644
index 0000000..2ce9d61
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.hex
@@ -0,0 +1,462 @@
+:100000006F00101A6F00C008000000000000000020
+:100010006F00001100000000000000000000000060
+:100020006F008018000000000000000000000000C9
+:100030006F00002000000000000000000000000031
+:10004000000000006F0040276F00802F00000000BC
+:100050000000000000000000000000006F005003DE
+:100060006F0080696F0040366F00803E6F00C046B1
+:100070006F00004F6F0040576F00805F6F0040704F
+:100080006F008078130000001300000013000000D0
+:10009000130101F823201100232221002324310021
+:1000A0002326410023285100232A6100232C7100BC
+:1000B000232E8100232091022322A1022324B102B6
+:1000C0002326C1022328D102232AE102232CF10294
+:1000D000232E01032320110523222105232431058A
+:1000E0002326410523285105232A6105232C710568
+:1000F000232E8105232091072322A1072324B10762
+:100100002326C1072328D107232AE107232CF1073F
+:1001100073252034F3251034EF0010406F00C07FAA
+:10012000130101F823201100232221002324310090
+:100130002326410023285100232A6100232C71002B
+:10014000232E8100232091022322A1022324B10225
+:100150002326C1022328D102232AE102232CF10203
+:10016000232E0103232011052322210523243105F9
+:100170002326410523285105232A6105232C7105D7
+:10018000232E8105232091072322A1072324B107D1
+:100190002326C1072328D107232AE107232CF107AF
+:1001A000EF00502C6F004077130101F8232011005D
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+:040000058000000077
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.lst
new file mode 100644
index 0000000..e8507be
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32-coretimer-timer_interrupt.lst
@@ -0,0 +1,3747 @@
+
+miv-rv32-coretimer-timer_interrupt.elf:     file format elf32-littleriscv
+miv-rv32-coretimer-timer_interrupt.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00001cc0 memsz 0x00002500 flags rwx
+
+Sections:
+Idx Name              Size      VMA       LMA       File off  Algn  Flags
+  0 .entry            000009a0  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text             00001260  800009a0  800009a0  000019a0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata            00000000  80001c00  80001c00  00002cc0  2**4  CONTENTS
+  3 .data             000000c0  80001c00  80001c00  00002c00  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .sbss             00000020  80001cc0  80001cc0  00002cc0  2**4  ALLOC
+  5 .bss              00000020  80001ce0  80001ce0  00002cc0  2**4  ALLOC
+  6 .heap             00000000  80001d00  80001d00  00002cc0  2**4  CONTENTS
+  7 .stack            00000800  80001d00  80001d00  00002cc0  2**4  ALLOC
+  8 .riscv.attributes 0000001c  00000000  00000000  00002cc0  2**0  CONTENTS, READONLY
+  9 .comment          00000051  00000000  00000000  00002cdc  2**0  CONTENTS, READONLY
+ 10 .debug_line       00004687  00000000  00000000  00002d2d  2**0  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_info       00002e5a  00000000  00000000  000073b4  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_abbrev     00000cc2  00000000  00000000  0000a20e  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_aranges    00000398  00000000  00000000  0000aed0  2**3  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_str        0000c434  00000000  00000000  0000b268  2**0  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges     000002e0  00000000  00000000  000176a0  2**3  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro      00003488  00000000  00000000  00017980  2**0  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_frame      00000ce8  00000000  00000000  0001ae08  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+800009a0 l    d  .text	00000000 .text
+80001c00 l    d  .sdata	00000000 .sdata
+80001c00 l    d  .data	00000000 .data
+80001cc0 l    d  .sbss	00000000 .sbss
+80001ce0 l    d  .bss	00000000 .bss
+80001d00 l    d  .heap	00000000 .heap
+80001d00 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_macro	00000000 .debug_macro
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+800009a0 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+80000120 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+800001a8 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+80000230 l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800002b8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000340 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+80000890 l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+800006f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+800003c8 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+80000450 l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800004d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000560 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+800005e8 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+80000670 l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+80000780 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000808 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000918 l       .entry	00000000 generic_restore
+800009f0 l       .text	00000000 ima_cores_setup
+80000a38 l       .text	00000000 vector_address_not_matching
+800009fc l       .text	00000000 generic_reset_handling
+80000ab8 l       .text	00000000 block_copy
+80000a3c l       .text	00000000 initializations
+80000a98 l       .text	00000000 zeroize_block
+80000ae0 l       .text	00000000 block_copy_error
+80000aa8 l       .text	00000000 zeroize_loop
+80000ac8 l       .text	00000000 block_copy_loop
+80000ae4 l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000ae8 l     F .text	00000030 MRV_clear_soft_irq
+80001cc0 l     O .sbss	00000008 g_systick_increment
+80001cc8 l     O .sbss	00000008 g_systick_cmp_value
+80001cd0 l     O .sbss	00000004 d_tick.2196
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+00000000 l    df *ABS*	00000000 hal_irq.c
+80001068 l     F .text	00000024 MRV_enable_interrupts
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_timer.c
+80001cd4 l     O .sbss	00000004 NULL_timer_instance
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80001ab0 l     F .text	0000002c MRV_enable_local_irq
+80001cd8 l     O .sbss	00000004 gpio_pins_state
+80001ce0 g     O .bss	00000008 g_gpio
+00000800 g       *ABS*	00000000 STACK_SIZE
+80002400 g       .sdata	00000000 __global_pointer$
+80001c00 g       *ABS*	00000000 __data_load
+80000ed0  w    F .text	0000001c SysTick_Handler
+8000117c g       .text	00000000 HW_get_8bit_reg_field
+80001cc0 g       .sbss	00000000 __sbss_start
+80000c90 g     F .text	00000088 handle_local_ei_interrupts
+800010b4 g       .text	00000000 HW_set_32bit_reg
+80001c00 g       .sdata	00000000 __sdata_start
+80000fb0  w    F .text	0000001c MSYS_EI4_IRQHandler
+80001154 g       .text	00000000 HW_set_8bit_reg_field
+80000f40  w    F .text	0000001c SUBSYS_IRQHandler
+80000d18 g     F .text	0000015c handle_trap
+00008000 g       *ABS*	00000000 RAM_SIZE
+80001ce8 g     O .bss	00000004 g_core_timer_0
+80001000  w    F .text	0000001c MSYS_EI6_IRQHandler
+800015b0 g     F .text	0000005c TMR_enable_int
+80001038  w    F .text	0000001c SUBSYSR_IRQHandler
+80000f08  w    F .text	0000001c MGECI_IRQHandler
+80001d00 g       .heap	00000000 _heap_end
+80001bc0 g     O .text	00000040 local_irq_handler_table
+8000101c  w    F .text	0000001c MSYS_EI7_IRQHandler
+80001d00 g       .bss	00000000 __bss_end
+80000e74 g     F .text	00000028 _init
+80001144 g       .text	00000000 HW_set_8bit_reg
+8000114c g       .text	00000000 HW_get_8bit_reg
+80000f5c  w    F .text	0000001c MSYS_EI1_IRQHandler
+80001ce0 g       .sbss	00000000 __sbss_end
+800010c4 g       .text	00000000 HW_set_32bit_reg_field
+80002500 g       .stack	00000000 __stack_top
+8000142c g     F .text	00000128 TMR_init
+80001cec g     O .bss	00000008 g_core_uart_0
+80001364 g     F .text	000000c8 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001c00 g     O .data	000000c0 g_message
+800017d4 g     F .text	00000164 GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+80000b18 g     F .text	0000014c handle_m_timer_interrupt
+80001c00 g       *ABS*	00000000 __sdata_load
+80001cc0 g       .data	00000000 __data_end
+800010ec g       .text	00000000 HW_get_32bit_reg_field
+80001660 g     F .text	00000174 GPIO_init
+80000000 g       *ABS*	00000000 RAM_START_ADDRESS
+80001938 g     F .text	00000178 GPIO_get_outputs
+80001ce0 g       .bss	00000000 __bss_start
+8000108c g     F .text	00000028 HAL_enable_interrupts
+80001b34 g     F .text	0000008c main
+80000fcc  w    F .text	0000001c MSYS_EI5_IRQHandler
+80000f24  w    F .text	0000001c MGEUI_IRQHandler
+80001104 g       .text	00000000 HW_get_16bit_reg
+80001c00 g       .sdata	00000000 __sdata_end
+80001d00 g       .heap	00000000 __heap_end
+80000e9c g     F .text	0000001c _fini
+8000110c g       .text	00000000 HW_set_16bit_reg_field
+80000f78  w    F .text	0000001c MSYS_EI2_IRQHandler
+80001d00 g       .stack	00000000 __stack_bottom
+80000eb8  w    F .text	00000018 Software_IRQHandler
+80001554 g     F .text	0000005c TMR_start
+80001d00 g       .heap	00000000 __heap_start
+80001d00 g       .bss	00000000 _end
+80000fe8  w    F .text	00000018 Reserved_IRQHandler
+8000118c g     F .text	000001d8 UART_init
+800010bc g       .text	00000000 HW_get_32bit_reg
+80001054 g     F .text	00000014 _exit
+800010fc g       .text	00000000 HW_set_16bit_reg
+80000f94  w    F .text	0000001c MSYS_EI3_IRQHandler
+80000eec  w    F .text	0000001c External_IRQHandler
+80001c00 g       .data	00000000 __data_start
+80000c64 g     F .text	0000002c handle_m_soft_interrupt
+80001134 g       .text	00000000 HW_get_16bit_reg_field
+80001adc g     F .text	00000058 MSYS_EI0_IRQHandler
+8000160c g     F .text	00000054 TMR_clear_int
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:113
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	1a10006f          	j	800009a0 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:124
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:130
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	1100006f          	j	80000120 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:139
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	1880006f          	j	800001a8 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:148
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	2000006f          	j	80000230 <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:159
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	2740006f          	j	800002b8 <vector_MGEUI_trap_handler>
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:165
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	2f80006f          	j	80000340 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:177
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	0350006f          	j	80000890 <vector_SUBSYSR_IRQHandler>
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:184
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	6980006f          	j	800006f8 <vector_SUBSYS_IRQHandler>
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:191
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	3640006f          	j	800003c8 <vector_MSYS_EI0_trap_handler>
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:197
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	3e80006f          	j	80000450 <vector_MSYS_EI1_trap_handler>
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:203
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	46c0006f          	j	800004d8 <vector_MSYS_EI2_trap_handler>
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:209
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	4f00006f          	j	80000560 <vector_MSYS_EI3_trap_handler>
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:215
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	5740006f          	j	800005e8 <vector_MSYS_EI4_trap_handler>
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:221
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	5f80006f          	j	80000670 <vector_MSYS_EI5_trap_handler>
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:228
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	7040006f          	j	80000780 <vector_MSYS_EI6_trap_handler>
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:238
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	7880006f          	j	80000808 <vector_MSYS_EI7_trap_handler>
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:247
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	f8010113          	addi	sp,sp,-128
+80000094:	00112023          	sw	ra,0(sp)
+80000098:	00212223          	sw	sp,4(sp)
+8000009c:	00312423          	sw	gp,8(sp)
+800000a0:	00412623          	sw	tp,12(sp)
+800000a4:	00512823          	sw	t0,16(sp)
+800000a8:	00612a23          	sw	t1,20(sp)
+800000ac:	00712c23          	sw	t2,24(sp)
+800000b0:	00812e23          	sw	s0,28(sp)
+800000b4:	02912023          	sw	s1,32(sp)
+800000b8:	02a12223          	sw	a0,36(sp)
+800000bc:	02b12423          	sw	a1,40(sp)
+800000c0:	02c12623          	sw	a2,44(sp)
+800000c4:	02d12823          	sw	a3,48(sp)
+800000c8:	02e12a23          	sw	a4,52(sp)
+800000cc:	02f12c23          	sw	a5,56(sp)
+800000d0:	03012e23          	sw	a6,60(sp)
+800000d4:	05112023          	sw	a7,64(sp)
+800000d8:	05212223          	sw	s2,68(sp)
+800000dc:	05312423          	sw	s3,72(sp)
+800000e0:	05412623          	sw	s4,76(sp)
+800000e4:	05512823          	sw	s5,80(sp)
+800000e8:	05612a23          	sw	s6,84(sp)
+800000ec:	05712c23          	sw	s7,88(sp)
+800000f0:	05812e23          	sw	s8,92(sp)
+800000f4:	07912023          	sw	s9,96(sp)
+800000f8:	07a12223          	sw	s10,100(sp)
+800000fc:	07b12423          	sw	s11,104(sp)
+80000100:	07c12623          	sw	t3,108(sp)
+80000104:	07d12823          	sw	t4,112(sp)
+80000108:	07e12a23          	sw	t5,116(sp)
+8000010c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+  csrr a0, mcause
+80000110:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a1, mepc
+80000114:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  jal handle_trap
+80000118:	401000ef          	jal	ra,80000d18 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  j generic_restore
+8000011c:	7fc0006f          	j	80000918 <generic_restore>
+
+80000120 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:254
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+80000120:	f8010113          	addi	sp,sp,-128
+80000124:	00112023          	sw	ra,0(sp)
+80000128:	00212223          	sw	sp,4(sp)
+8000012c:	00312423          	sw	gp,8(sp)
+80000130:	00412623          	sw	tp,12(sp)
+80000134:	00512823          	sw	t0,16(sp)
+80000138:	00612a23          	sw	t1,20(sp)
+8000013c:	00712c23          	sw	t2,24(sp)
+80000140:	00812e23          	sw	s0,28(sp)
+80000144:	02912023          	sw	s1,32(sp)
+80000148:	02a12223          	sw	a0,36(sp)
+8000014c:	02b12423          	sw	a1,40(sp)
+80000150:	02c12623          	sw	a2,44(sp)
+80000154:	02d12823          	sw	a3,48(sp)
+80000158:	02e12a23          	sw	a4,52(sp)
+8000015c:	02f12c23          	sw	a5,56(sp)
+80000160:	03012e23          	sw	a6,60(sp)
+80000164:	05112023          	sw	a7,64(sp)
+80000168:	05212223          	sw	s2,68(sp)
+8000016c:	05312423          	sw	s3,72(sp)
+80000170:	05412623          	sw	s4,76(sp)
+80000174:	05512823          	sw	s5,80(sp)
+80000178:	05612a23          	sw	s6,84(sp)
+8000017c:	05712c23          	sw	s7,88(sp)
+80000180:	05812e23          	sw	s8,92(sp)
+80000184:	07912023          	sw	s9,96(sp)
+80000188:	07a12223          	sw	s10,100(sp)
+8000018c:	07b12423          	sw	s11,104(sp)
+80000190:	07c12623          	sw	t3,108(sp)
+80000194:	07d12823          	sw	t4,112(sp)
+80000198:	07e12a23          	sw	t5,116(sp)
+8000019c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+  jal handle_m_soft_interrupt
+800001a0:	2c5000ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  j generic_restore
+800001a4:	7740006f          	j	80000918 <generic_restore>
+
+800001a8 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:259
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+800001a8:	f8010113          	addi	sp,sp,-128
+800001ac:	00112023          	sw	ra,0(sp)
+800001b0:	00212223          	sw	sp,4(sp)
+800001b4:	00312423          	sw	gp,8(sp)
+800001b8:	00412623          	sw	tp,12(sp)
+800001bc:	00512823          	sw	t0,16(sp)
+800001c0:	00612a23          	sw	t1,20(sp)
+800001c4:	00712c23          	sw	t2,24(sp)
+800001c8:	00812e23          	sw	s0,28(sp)
+800001cc:	02912023          	sw	s1,32(sp)
+800001d0:	02a12223          	sw	a0,36(sp)
+800001d4:	02b12423          	sw	a1,40(sp)
+800001d8:	02c12623          	sw	a2,44(sp)
+800001dc:	02d12823          	sw	a3,48(sp)
+800001e0:	02e12a23          	sw	a4,52(sp)
+800001e4:	02f12c23          	sw	a5,56(sp)
+800001e8:	03012e23          	sw	a6,60(sp)
+800001ec:	05112023          	sw	a7,64(sp)
+800001f0:	05212223          	sw	s2,68(sp)
+800001f4:	05312423          	sw	s3,72(sp)
+800001f8:	05412623          	sw	s4,76(sp)
+800001fc:	05512823          	sw	s5,80(sp)
+80000200:	05612a23          	sw	s6,84(sp)
+80000204:	05712c23          	sw	s7,88(sp)
+80000208:	05812e23          	sw	s8,92(sp)
+8000020c:	07912023          	sw	s9,96(sp)
+80000210:	07a12223          	sw	s10,100(sp)
+80000214:	07b12423          	sw	s11,104(sp)
+80000218:	07c12623          	sw	t3,108(sp)
+8000021c:	07d12823          	sw	t4,112(sp)
+80000220:	07e12a23          	sw	t5,116(sp)
+80000224:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+  jal handle_m_timer_interrupt
+80000228:	0f1000ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  j generic_restore
+8000022c:	6ec0006f          	j	80000918 <generic_restore>
+
+80000230 <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:264
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+80000230:	f8010113          	addi	sp,sp,-128
+80000234:	00112023          	sw	ra,0(sp)
+80000238:	00212223          	sw	sp,4(sp)
+8000023c:	00312423          	sw	gp,8(sp)
+80000240:	00412623          	sw	tp,12(sp)
+80000244:	00512823          	sw	t0,16(sp)
+80000248:	00612a23          	sw	t1,20(sp)
+8000024c:	00712c23          	sw	t2,24(sp)
+80000250:	00812e23          	sw	s0,28(sp)
+80000254:	02912023          	sw	s1,32(sp)
+80000258:	02a12223          	sw	a0,36(sp)
+8000025c:	02b12423          	sw	a1,40(sp)
+80000260:	02c12623          	sw	a2,44(sp)
+80000264:	02d12823          	sw	a3,48(sp)
+80000268:	02e12a23          	sw	a4,52(sp)
+8000026c:	02f12c23          	sw	a5,56(sp)
+80000270:	03012e23          	sw	a6,60(sp)
+80000274:	05112023          	sw	a7,64(sp)
+80000278:	05212223          	sw	s2,68(sp)
+8000027c:	05312423          	sw	s3,72(sp)
+80000280:	05412623          	sw	s4,76(sp)
+80000284:	05512823          	sw	s5,80(sp)
+80000288:	05612a23          	sw	s6,84(sp)
+8000028c:	05712c23          	sw	s7,88(sp)
+80000290:	05812e23          	sw	s8,92(sp)
+80000294:	07912023          	sw	s9,96(sp)
+80000298:	07a12223          	sw	s10,100(sp)
+8000029c:	07b12423          	sw	s11,104(sp)
+800002a0:	07c12623          	sw	t3,108(sp)
+800002a4:	07d12823          	sw	t4,112(sp)
+800002a8:	07e12a23          	sw	t5,116(sp)
+800002ac:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:268
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800002b0:	43d000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:270
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800002b4:	6640006f          	j	80000918 <generic_restore>
+
+800002b8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:274
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800002b8:	f8010113          	addi	sp,sp,-128
+800002bc:	00112023          	sw	ra,0(sp)
+800002c0:	00212223          	sw	sp,4(sp)
+800002c4:	00312423          	sw	gp,8(sp)
+800002c8:	00412623          	sw	tp,12(sp)
+800002cc:	00512823          	sw	t0,16(sp)
+800002d0:	00612a23          	sw	t1,20(sp)
+800002d4:	00712c23          	sw	t2,24(sp)
+800002d8:	00812e23          	sw	s0,28(sp)
+800002dc:	02912023          	sw	s1,32(sp)
+800002e0:	02a12223          	sw	a0,36(sp)
+800002e4:	02b12423          	sw	a1,40(sp)
+800002e8:	02c12623          	sw	a2,44(sp)
+800002ec:	02d12823          	sw	a3,48(sp)
+800002f0:	02e12a23          	sw	a4,52(sp)
+800002f4:	02f12c23          	sw	a5,56(sp)
+800002f8:	03012e23          	sw	a6,60(sp)
+800002fc:	05112023          	sw	a7,64(sp)
+80000300:	05212223          	sw	s2,68(sp)
+80000304:	05312423          	sw	s3,72(sp)
+80000308:	05412623          	sw	s4,76(sp)
+8000030c:	05512823          	sw	s5,80(sp)
+80000310:	05612a23          	sw	s6,84(sp)
+80000314:	05712c23          	sw	s7,88(sp)
+80000318:	05812e23          	sw	s8,92(sp)
+8000031c:	07912023          	sw	s9,96(sp)
+80000320:	07a12223          	sw	s10,100(sp)
+80000324:	07b12423          	sw	s11,104(sp)
+80000328:	07c12623          	sw	t3,108(sp)
+8000032c:	07d12823          	sw	t4,112(sp)
+80000330:	07e12a23          	sw	t5,116(sp)
+80000334:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+  jal MGEUI_IRQHandler
+80000338:	3ed000ef          	jal	ra,80000f24 <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  j generic_restore
+8000033c:	5dc0006f          	j	80000918 <generic_restore>
+
+80000340 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:279
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000340:	f8010113          	addi	sp,sp,-128
+80000344:	00112023          	sw	ra,0(sp)
+80000348:	00212223          	sw	sp,4(sp)
+8000034c:	00312423          	sw	gp,8(sp)
+80000350:	00412623          	sw	tp,12(sp)
+80000354:	00512823          	sw	t0,16(sp)
+80000358:	00612a23          	sw	t1,20(sp)
+8000035c:	00712c23          	sw	t2,24(sp)
+80000360:	00812e23          	sw	s0,28(sp)
+80000364:	02912023          	sw	s1,32(sp)
+80000368:	02a12223          	sw	a0,36(sp)
+8000036c:	02b12423          	sw	a1,40(sp)
+80000370:	02c12623          	sw	a2,44(sp)
+80000374:	02d12823          	sw	a3,48(sp)
+80000378:	02e12a23          	sw	a4,52(sp)
+8000037c:	02f12c23          	sw	a5,56(sp)
+80000380:	03012e23          	sw	a6,60(sp)
+80000384:	05112023          	sw	a7,64(sp)
+80000388:	05212223          	sw	s2,68(sp)
+8000038c:	05312423          	sw	s3,72(sp)
+80000390:	05412623          	sw	s4,76(sp)
+80000394:	05512823          	sw	s5,80(sp)
+80000398:	05612a23          	sw	s6,84(sp)
+8000039c:	05712c23          	sw	s7,88(sp)
+800003a0:	05812e23          	sw	s8,92(sp)
+800003a4:	07912023          	sw	s9,96(sp)
+800003a8:	07a12223          	sw	s10,100(sp)
+800003ac:	07b12423          	sw	s11,104(sp)
+800003b0:	07c12623          	sw	t3,108(sp)
+800003b4:	07d12823          	sw	t4,112(sp)
+800003b8:	07e12a23          	sw	t5,116(sp)
+800003bc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+  jal MGECI_IRQHandler
+800003c0:	349000ef          	jal	ra,80000f08 <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  j generic_restore
+800003c4:	5540006f          	j	80000918 <generic_restore>
+
+800003c8 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:284
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+800003c8:	f8010113          	addi	sp,sp,-128
+800003cc:	00112023          	sw	ra,0(sp)
+800003d0:	00212223          	sw	sp,4(sp)
+800003d4:	00312423          	sw	gp,8(sp)
+800003d8:	00412623          	sw	tp,12(sp)
+800003dc:	00512823          	sw	t0,16(sp)
+800003e0:	00612a23          	sw	t1,20(sp)
+800003e4:	00712c23          	sw	t2,24(sp)
+800003e8:	00812e23          	sw	s0,28(sp)
+800003ec:	02912023          	sw	s1,32(sp)
+800003f0:	02a12223          	sw	a0,36(sp)
+800003f4:	02b12423          	sw	a1,40(sp)
+800003f8:	02c12623          	sw	a2,44(sp)
+800003fc:	02d12823          	sw	a3,48(sp)
+80000400:	02e12a23          	sw	a4,52(sp)
+80000404:	02f12c23          	sw	a5,56(sp)
+80000408:	03012e23          	sw	a6,60(sp)
+8000040c:	05112023          	sw	a7,64(sp)
+80000410:	05212223          	sw	s2,68(sp)
+80000414:	05312423          	sw	s3,72(sp)
+80000418:	05412623          	sw	s4,76(sp)
+8000041c:	05512823          	sw	s5,80(sp)
+80000420:	05612a23          	sw	s6,84(sp)
+80000424:	05712c23          	sw	s7,88(sp)
+80000428:	05812e23          	sw	s8,92(sp)
+8000042c:	07912023          	sw	s9,96(sp)
+80000430:	07a12223          	sw	s10,100(sp)
+80000434:	07b12423          	sw	s11,104(sp)
+80000438:	07c12623          	sw	t3,108(sp)
+8000043c:	07d12823          	sw	t4,112(sp)
+80000440:	07e12a23          	sw	t5,116(sp)
+80000444:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+  jal MSYS_EI0_IRQHandler
+80000448:	694010ef          	jal	ra,80001adc <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  j generic_restore
+8000044c:	4cc0006f          	j	80000918 <generic_restore>
+
+80000450 <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:289
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+80000450:	f8010113          	addi	sp,sp,-128
+80000454:	00112023          	sw	ra,0(sp)
+80000458:	00212223          	sw	sp,4(sp)
+8000045c:	00312423          	sw	gp,8(sp)
+80000460:	00412623          	sw	tp,12(sp)
+80000464:	00512823          	sw	t0,16(sp)
+80000468:	00612a23          	sw	t1,20(sp)
+8000046c:	00712c23          	sw	t2,24(sp)
+80000470:	00812e23          	sw	s0,28(sp)
+80000474:	02912023          	sw	s1,32(sp)
+80000478:	02a12223          	sw	a0,36(sp)
+8000047c:	02b12423          	sw	a1,40(sp)
+80000480:	02c12623          	sw	a2,44(sp)
+80000484:	02d12823          	sw	a3,48(sp)
+80000488:	02e12a23          	sw	a4,52(sp)
+8000048c:	02f12c23          	sw	a5,56(sp)
+80000490:	03012e23          	sw	a6,60(sp)
+80000494:	05112023          	sw	a7,64(sp)
+80000498:	05212223          	sw	s2,68(sp)
+8000049c:	05312423          	sw	s3,72(sp)
+800004a0:	05412623          	sw	s4,76(sp)
+800004a4:	05512823          	sw	s5,80(sp)
+800004a8:	05612a23          	sw	s6,84(sp)
+800004ac:	05712c23          	sw	s7,88(sp)
+800004b0:	05812e23          	sw	s8,92(sp)
+800004b4:	07912023          	sw	s9,96(sp)
+800004b8:	07a12223          	sw	s10,100(sp)
+800004bc:	07b12423          	sw	s11,104(sp)
+800004c0:	07c12623          	sw	t3,108(sp)
+800004c4:	07d12823          	sw	t4,112(sp)
+800004c8:	07e12a23          	sw	t5,116(sp)
+800004cc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+  jal MSYS_EI1_IRQHandler
+800004d0:	28d000ef          	jal	ra,80000f5c <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  j generic_restore
+800004d4:	4440006f          	j	80000918 <generic_restore>
+
+800004d8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:294
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800004d8:	f8010113          	addi	sp,sp,-128
+800004dc:	00112023          	sw	ra,0(sp)
+800004e0:	00212223          	sw	sp,4(sp)
+800004e4:	00312423          	sw	gp,8(sp)
+800004e8:	00412623          	sw	tp,12(sp)
+800004ec:	00512823          	sw	t0,16(sp)
+800004f0:	00612a23          	sw	t1,20(sp)
+800004f4:	00712c23          	sw	t2,24(sp)
+800004f8:	00812e23          	sw	s0,28(sp)
+800004fc:	02912023          	sw	s1,32(sp)
+80000500:	02a12223          	sw	a0,36(sp)
+80000504:	02b12423          	sw	a1,40(sp)
+80000508:	02c12623          	sw	a2,44(sp)
+8000050c:	02d12823          	sw	a3,48(sp)
+80000510:	02e12a23          	sw	a4,52(sp)
+80000514:	02f12c23          	sw	a5,56(sp)
+80000518:	03012e23          	sw	a6,60(sp)
+8000051c:	05112023          	sw	a7,64(sp)
+80000520:	05212223          	sw	s2,68(sp)
+80000524:	05312423          	sw	s3,72(sp)
+80000528:	05412623          	sw	s4,76(sp)
+8000052c:	05512823          	sw	s5,80(sp)
+80000530:	05612a23          	sw	s6,84(sp)
+80000534:	05712c23          	sw	s7,88(sp)
+80000538:	05812e23          	sw	s8,92(sp)
+8000053c:	07912023          	sw	s9,96(sp)
+80000540:	07a12223          	sw	s10,100(sp)
+80000544:	07b12423          	sw	s11,104(sp)
+80000548:	07c12623          	sw	t3,108(sp)
+8000054c:	07d12823          	sw	t4,112(sp)
+80000550:	07e12a23          	sw	t5,116(sp)
+80000554:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+  jal MSYS_EI2_IRQHandler
+80000558:	221000ef          	jal	ra,80000f78 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  j generic_restore
+8000055c:	3bc0006f          	j	80000918 <generic_restore>
+
+80000560 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:299
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000560:	f8010113          	addi	sp,sp,-128
+80000564:	00112023          	sw	ra,0(sp)
+80000568:	00212223          	sw	sp,4(sp)
+8000056c:	00312423          	sw	gp,8(sp)
+80000570:	00412623          	sw	tp,12(sp)
+80000574:	00512823          	sw	t0,16(sp)
+80000578:	00612a23          	sw	t1,20(sp)
+8000057c:	00712c23          	sw	t2,24(sp)
+80000580:	00812e23          	sw	s0,28(sp)
+80000584:	02912023          	sw	s1,32(sp)
+80000588:	02a12223          	sw	a0,36(sp)
+8000058c:	02b12423          	sw	a1,40(sp)
+80000590:	02c12623          	sw	a2,44(sp)
+80000594:	02d12823          	sw	a3,48(sp)
+80000598:	02e12a23          	sw	a4,52(sp)
+8000059c:	02f12c23          	sw	a5,56(sp)
+800005a0:	03012e23          	sw	a6,60(sp)
+800005a4:	05112023          	sw	a7,64(sp)
+800005a8:	05212223          	sw	s2,68(sp)
+800005ac:	05312423          	sw	s3,72(sp)
+800005b0:	05412623          	sw	s4,76(sp)
+800005b4:	05512823          	sw	s5,80(sp)
+800005b8:	05612a23          	sw	s6,84(sp)
+800005bc:	05712c23          	sw	s7,88(sp)
+800005c0:	05812e23          	sw	s8,92(sp)
+800005c4:	07912023          	sw	s9,96(sp)
+800005c8:	07a12223          	sw	s10,100(sp)
+800005cc:	07b12423          	sw	s11,104(sp)
+800005d0:	07c12623          	sw	t3,108(sp)
+800005d4:	07d12823          	sw	t4,112(sp)
+800005d8:	07e12a23          	sw	t5,116(sp)
+800005dc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+  jal MSYS_EI3_IRQHandler
+800005e0:	1b5000ef          	jal	ra,80000f94 <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  j generic_restore
+800005e4:	3340006f          	j	80000918 <generic_restore>
+
+800005e8 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:304
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+800005e8:	f8010113          	addi	sp,sp,-128
+800005ec:	00112023          	sw	ra,0(sp)
+800005f0:	00212223          	sw	sp,4(sp)
+800005f4:	00312423          	sw	gp,8(sp)
+800005f8:	00412623          	sw	tp,12(sp)
+800005fc:	00512823          	sw	t0,16(sp)
+80000600:	00612a23          	sw	t1,20(sp)
+80000604:	00712c23          	sw	t2,24(sp)
+80000608:	00812e23          	sw	s0,28(sp)
+8000060c:	02912023          	sw	s1,32(sp)
+80000610:	02a12223          	sw	a0,36(sp)
+80000614:	02b12423          	sw	a1,40(sp)
+80000618:	02c12623          	sw	a2,44(sp)
+8000061c:	02d12823          	sw	a3,48(sp)
+80000620:	02e12a23          	sw	a4,52(sp)
+80000624:	02f12c23          	sw	a5,56(sp)
+80000628:	03012e23          	sw	a6,60(sp)
+8000062c:	05112023          	sw	a7,64(sp)
+80000630:	05212223          	sw	s2,68(sp)
+80000634:	05312423          	sw	s3,72(sp)
+80000638:	05412623          	sw	s4,76(sp)
+8000063c:	05512823          	sw	s5,80(sp)
+80000640:	05612a23          	sw	s6,84(sp)
+80000644:	05712c23          	sw	s7,88(sp)
+80000648:	05812e23          	sw	s8,92(sp)
+8000064c:	07912023          	sw	s9,96(sp)
+80000650:	07a12223          	sw	s10,100(sp)
+80000654:	07b12423          	sw	s11,104(sp)
+80000658:	07c12623          	sw	t3,108(sp)
+8000065c:	07d12823          	sw	t4,112(sp)
+80000660:	07e12a23          	sw	t5,116(sp)
+80000664:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+  jal MSYS_EI4_IRQHandler
+80000668:	149000ef          	jal	ra,80000fb0 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  j generic_restore
+8000066c:	2ac0006f          	j	80000918 <generic_restore>
+
+80000670 <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:309
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+80000670:	f8010113          	addi	sp,sp,-128
+80000674:	00112023          	sw	ra,0(sp)
+80000678:	00212223          	sw	sp,4(sp)
+8000067c:	00312423          	sw	gp,8(sp)
+80000680:	00412623          	sw	tp,12(sp)
+80000684:	00512823          	sw	t0,16(sp)
+80000688:	00612a23          	sw	t1,20(sp)
+8000068c:	00712c23          	sw	t2,24(sp)
+80000690:	00812e23          	sw	s0,28(sp)
+80000694:	02912023          	sw	s1,32(sp)
+80000698:	02a12223          	sw	a0,36(sp)
+8000069c:	02b12423          	sw	a1,40(sp)
+800006a0:	02c12623          	sw	a2,44(sp)
+800006a4:	02d12823          	sw	a3,48(sp)
+800006a8:	02e12a23          	sw	a4,52(sp)
+800006ac:	02f12c23          	sw	a5,56(sp)
+800006b0:	03012e23          	sw	a6,60(sp)
+800006b4:	05112023          	sw	a7,64(sp)
+800006b8:	05212223          	sw	s2,68(sp)
+800006bc:	05312423          	sw	s3,72(sp)
+800006c0:	05412623          	sw	s4,76(sp)
+800006c4:	05512823          	sw	s5,80(sp)
+800006c8:	05612a23          	sw	s6,84(sp)
+800006cc:	05712c23          	sw	s7,88(sp)
+800006d0:	05812e23          	sw	s8,92(sp)
+800006d4:	07912023          	sw	s9,96(sp)
+800006d8:	07a12223          	sw	s10,100(sp)
+800006dc:	07b12423          	sw	s11,104(sp)
+800006e0:	07c12623          	sw	t3,108(sp)
+800006e4:	07d12823          	sw	t4,112(sp)
+800006e8:	07e12a23          	sw	t5,116(sp)
+800006ec:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+  jal MSYS_EI5_IRQHandler
+800006f0:	0dd000ef          	jal	ra,80000fcc <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  j generic_restore
+800006f4:	2240006f          	j	80000918 <generic_restore>
+
+800006f8 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:314
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+800006f8:	f8010113          	addi	sp,sp,-128
+800006fc:	00112023          	sw	ra,0(sp)
+80000700:	00212223          	sw	sp,4(sp)
+80000704:	00312423          	sw	gp,8(sp)
+80000708:	00412623          	sw	tp,12(sp)
+8000070c:	00512823          	sw	t0,16(sp)
+80000710:	00612a23          	sw	t1,20(sp)
+80000714:	00712c23          	sw	t2,24(sp)
+80000718:	00812e23          	sw	s0,28(sp)
+8000071c:	02912023          	sw	s1,32(sp)
+80000720:	02a12223          	sw	a0,36(sp)
+80000724:	02b12423          	sw	a1,40(sp)
+80000728:	02c12623          	sw	a2,44(sp)
+8000072c:	02d12823          	sw	a3,48(sp)
+80000730:	02e12a23          	sw	a4,52(sp)
+80000734:	02f12c23          	sw	a5,56(sp)
+80000738:	03012e23          	sw	a6,60(sp)
+8000073c:	05112023          	sw	a7,64(sp)
+80000740:	05212223          	sw	s2,68(sp)
+80000744:	05312423          	sw	s3,72(sp)
+80000748:	05412623          	sw	s4,76(sp)
+8000074c:	05512823          	sw	s5,80(sp)
+80000750:	05612a23          	sw	s6,84(sp)
+80000754:	05712c23          	sw	s7,88(sp)
+80000758:	05812e23          	sw	s8,92(sp)
+8000075c:	07912023          	sw	s9,96(sp)
+80000760:	07a12223          	sw	s10,100(sp)
+80000764:	07b12423          	sw	s11,104(sp)
+80000768:	07c12623          	sw	t3,108(sp)
+8000076c:	07d12823          	sw	t4,112(sp)
+80000770:	07e12a23          	sw	t5,116(sp)
+80000774:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+  jal SUBSYS_IRQHandler
+80000778:	7c8000ef          	jal	ra,80000f40 <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  j generic_restore
+8000077c:	19c0006f          	j	80000918 <generic_restore>
+
+80000780 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:320
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+80000780:	f8010113          	addi	sp,sp,-128
+80000784:	00112023          	sw	ra,0(sp)
+80000788:	00212223          	sw	sp,4(sp)
+8000078c:	00312423          	sw	gp,8(sp)
+80000790:	00412623          	sw	tp,12(sp)
+80000794:	00512823          	sw	t0,16(sp)
+80000798:	00612a23          	sw	t1,20(sp)
+8000079c:	00712c23          	sw	t2,24(sp)
+800007a0:	00812e23          	sw	s0,28(sp)
+800007a4:	02912023          	sw	s1,32(sp)
+800007a8:	02a12223          	sw	a0,36(sp)
+800007ac:	02b12423          	sw	a1,40(sp)
+800007b0:	02c12623          	sw	a2,44(sp)
+800007b4:	02d12823          	sw	a3,48(sp)
+800007b8:	02e12a23          	sw	a4,52(sp)
+800007bc:	02f12c23          	sw	a5,56(sp)
+800007c0:	03012e23          	sw	a6,60(sp)
+800007c4:	05112023          	sw	a7,64(sp)
+800007c8:	05212223          	sw	s2,68(sp)
+800007cc:	05312423          	sw	s3,72(sp)
+800007d0:	05412623          	sw	s4,76(sp)
+800007d4:	05512823          	sw	s5,80(sp)
+800007d8:	05612a23          	sw	s6,84(sp)
+800007dc:	05712c23          	sw	s7,88(sp)
+800007e0:	05812e23          	sw	s8,92(sp)
+800007e4:	07912023          	sw	s9,96(sp)
+800007e8:	07a12223          	sw	s10,100(sp)
+800007ec:	07b12423          	sw	s11,104(sp)
+800007f0:	07c12623          	sw	t3,108(sp)
+800007f4:	07d12823          	sw	t4,112(sp)
+800007f8:	07e12a23          	sw	t5,116(sp)
+800007fc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+  jal MSYS_EI6_IRQHandler
+80000800:	001000ef          	jal	ra,80001000 <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  j generic_restore
+80000804:	1140006f          	j	80000918 <generic_restore>
+
+80000808 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:325
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000808:	f8010113          	addi	sp,sp,-128
+8000080c:	00112023          	sw	ra,0(sp)
+80000810:	00212223          	sw	sp,4(sp)
+80000814:	00312423          	sw	gp,8(sp)
+80000818:	00412623          	sw	tp,12(sp)
+8000081c:	00512823          	sw	t0,16(sp)
+80000820:	00612a23          	sw	t1,20(sp)
+80000824:	00712c23          	sw	t2,24(sp)
+80000828:	00812e23          	sw	s0,28(sp)
+8000082c:	02912023          	sw	s1,32(sp)
+80000830:	02a12223          	sw	a0,36(sp)
+80000834:	02b12423          	sw	a1,40(sp)
+80000838:	02c12623          	sw	a2,44(sp)
+8000083c:	02d12823          	sw	a3,48(sp)
+80000840:	02e12a23          	sw	a4,52(sp)
+80000844:	02f12c23          	sw	a5,56(sp)
+80000848:	03012e23          	sw	a6,60(sp)
+8000084c:	05112023          	sw	a7,64(sp)
+80000850:	05212223          	sw	s2,68(sp)
+80000854:	05312423          	sw	s3,72(sp)
+80000858:	05412623          	sw	s4,76(sp)
+8000085c:	05512823          	sw	s5,80(sp)
+80000860:	05612a23          	sw	s6,84(sp)
+80000864:	05712c23          	sw	s7,88(sp)
+80000868:	05812e23          	sw	s8,92(sp)
+8000086c:	07912023          	sw	s9,96(sp)
+80000870:	07a12223          	sw	s10,100(sp)
+80000874:	07b12423          	sw	s11,104(sp)
+80000878:	07c12623          	sw	t3,108(sp)
+8000087c:	07d12823          	sw	t4,112(sp)
+80000880:	07e12a23          	sw	t5,116(sp)
+80000884:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+  jal MSYS_EI7_IRQHandler
+80000888:	794000ef          	jal	ra,8000101c <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  j generic_restore
+8000088c:	08c0006f          	j	80000918 <generic_restore>
+
+80000890 <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:331
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+80000890:	f8010113          	addi	sp,sp,-128
+80000894:	00112023          	sw	ra,0(sp)
+80000898:	00212223          	sw	sp,4(sp)
+8000089c:	00312423          	sw	gp,8(sp)
+800008a0:	00412623          	sw	tp,12(sp)
+800008a4:	00512823          	sw	t0,16(sp)
+800008a8:	00612a23          	sw	t1,20(sp)
+800008ac:	00712c23          	sw	t2,24(sp)
+800008b0:	00812e23          	sw	s0,28(sp)
+800008b4:	02912023          	sw	s1,32(sp)
+800008b8:	02a12223          	sw	a0,36(sp)
+800008bc:	02b12423          	sw	a1,40(sp)
+800008c0:	02c12623          	sw	a2,44(sp)
+800008c4:	02d12823          	sw	a3,48(sp)
+800008c8:	02e12a23          	sw	a4,52(sp)
+800008cc:	02f12c23          	sw	a5,56(sp)
+800008d0:	03012e23          	sw	a6,60(sp)
+800008d4:	05112023          	sw	a7,64(sp)
+800008d8:	05212223          	sw	s2,68(sp)
+800008dc:	05312423          	sw	s3,72(sp)
+800008e0:	05412623          	sw	s4,76(sp)
+800008e4:	05512823          	sw	s5,80(sp)
+800008e8:	05612a23          	sw	s6,84(sp)
+800008ec:	05712c23          	sw	s7,88(sp)
+800008f0:	05812e23          	sw	s8,92(sp)
+800008f4:	07912023          	sw	s9,96(sp)
+800008f8:	07a12223          	sw	s10,100(sp)
+800008fc:	07b12423          	sw	s11,104(sp)
+80000900:	07c12623          	sw	t3,108(sp)
+80000904:	07d12823          	sw	t4,112(sp)
+80000908:	07e12a23          	sw	t5,116(sp)
+8000090c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+  jal SUBSYSR_IRQHandler
+80000910:	728000ef          	jal	ra,80001038 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  j generic_restore
+80000914:	0040006f          	j	80000918 <generic_restore>
+
+80000918 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:339
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000918:	00012083          	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+  LREG x2, 1 * REGBYTES(sp)
+8000091c:	00412103          	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x3, 2 * REGBYTES(sp)
+80000920:	00812183          	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x4, 3 * REGBYTES(sp)
+80000924:	00c12203          	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x5, 4 * REGBYTES(sp)
+80000928:	01012283          	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x6, 5 * REGBYTES(sp)
+8000092c:	01412303          	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x7, 6 * REGBYTES(sp)
+80000930:	01812383          	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x8, 7 * REGBYTES(sp)
+80000934:	01c12403          	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x9, 8 * REGBYTES(sp)
+80000938:	02012483          	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x10, 9 * REGBYTES(sp)
+8000093c:	02412503          	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x11, 10 * REGBYTES(sp)
+80000940:	02812583          	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x12, 11 * REGBYTES(sp)
+80000944:	02c12603          	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x13, 12 * REGBYTES(sp)
+80000948:	03012683          	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x14, 13 * REGBYTES(sp)
+8000094c:	03412703          	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x15, 14 * REGBYTES(sp)
+80000950:	03812783          	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x16, 15 * REGBYTES(sp)
+80000954:	03c12803          	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x17, 16 * REGBYTES(sp)
+80000958:	04012883          	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x18, 17 * REGBYTES(sp)
+8000095c:	04412903          	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x19, 18 * REGBYTES(sp)
+80000960:	04812983          	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x20, 19 * REGBYTES(sp)
+80000964:	04c12a03          	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x21, 20 * REGBYTES(sp)
+80000968:	05012a83          	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x22, 21 * REGBYTES(sp)
+8000096c:	05412b03          	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x23, 22 * REGBYTES(sp)
+80000970:	05812b83          	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x24, 23 * REGBYTES(sp)
+80000974:	05c12c03          	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x25, 24 * REGBYTES(sp)
+80000978:	06012c83          	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x26, 25 * REGBYTES(sp)
+8000097c:	06412d03          	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x27, 26 * REGBYTES(sp)
+80000980:	06812d83          	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x28, 27 * REGBYTES(sp)
+80000984:	06c12e03          	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x29, 28 * REGBYTES(sp)
+80000988:	07012e83          	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x30, 29 * REGBYTES(sp)
+8000098c:	07412f03          	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x31, 30 * REGBYTES(sp)
+80000990:	07812f83          	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:408
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+80000994:	08010113          	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  mret
+80000998:	30200073          	mret
+8000099c:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+800009a0 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:418
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+800009a0:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+  csrwi mie, 0
+800009a4:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  la ra, _start
+800009a8:	fffff097          	auipc	ra,0xfffff
+800009ac:	65808093          	addi	ra,ra,1624 # 80000000 <RAM_START_ADDRESS>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:424
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+800009b0:	0200c2b7          	lui	t0,0x200c
+800009b4:	ffc28293          	addi	t0,t0,-4 # 200bffc <RAM_SIZE+0x2003ffc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+  sw x0, 0(t0)
+800009b8:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:428
+#endif
+
+  csrr t0, misa
+800009bc:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+  andi t0, t0, A_EXTENSION_MASK
+800009c0:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+800009c4:	02029663          	bnez	t0,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:438
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+800009c8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+800009cc:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  li t1, MTVEC_VECTORED_MODE_VAL
+800009d0:	00100313          	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+800009d4:	00629e63          	bne	t0,t1,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:445
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+800009d8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+  andi t0, t0, 0xFFFFFFFC
+800009dc:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  la t1, trap_entry
+800009e0:	fffff317          	auipc	t1,0xfffff
+800009e4:	62430313          	addi	t1,t1,1572 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  bne t0, t1, vector_address_not_matching
+800009e8:	04629863          	bne	t0,t1,80000a38 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  j generic_reset_handling
+800009ec:	0100006f          	j	800009fc <generic_reset_handling>
+
+800009f0 <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:476
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+800009f0:	fffff297          	auipc	t0,0xfffff
+800009f4:	61428293          	addi	t0,t0,1556 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:482
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+800009f8:	30529073          	csrw	mtvec,t0
+
+800009fc <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:487
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+800009fc:	00001717          	auipc	a4,0x1
+80000a00:	20470713          	addi	a4,a4,516 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+    la a5, __sdata_start
+80000a04:	00001797          	auipc	a5,0x1
+80000a08:	1fc78793          	addi	a5,a5,508 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a6, __sdata_end
+80000a0c:	00001817          	auipc	a6,0x1
+80000a10:	1f480813          	addi	a6,a6,500 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+80000a14:	00f70863          	beq	a4,a5,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+80000a18:	01078663          	beq	a5,a6,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    call block_copy
+80000a1c:	00000097          	auipc	ra,0x0
+80000a20:	09c080e7          	jalr	156(ra) # 80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:496
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+80000a24:	00002197          	auipc	gp,0x2
+80000a28:	9dc18193          	addi	gp,gp,-1572 # 80002400 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:513
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+80000a2c:	010000ef          	jal	ra,80000a3c <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:515
+  /* Initialize stack pointer */
+  la sp, __stack_top
+80000a30:	10018113          	addi	sp,gp,256 # 80002500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:518
+
+  /* Jump into C code */
+  j _init
+80000a34:	4400006f          	j	80000e74 <_init>
+
+80000a38 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:523
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+80000a38:	00100073          	ebreak
+
+80000a3c <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:527
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+80000a3c:	00008293          	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+    la  a5, __bss_start
+80000a40:	8e018793          	addi	a5,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a6, __bss_end
+80000a44:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a48:	01078463          	beq	a5,a6,80000a50 <initializations+0x14>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    call zeroize_block
+80000a4c:	04c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:535
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000a50:	8c018793          	addi	a5,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+    la  a6, __sbss_end
+80000a54:	8e018813          	addi	a6,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a58:	01078c63          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    call zeroize_block
+80000a5c:	03c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:541
+
+/* Clear heap */
+    la  a5, __heap_start
+80000a60:	90018793          	addi	a5,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+    la  a6, __heap_end
+80000a64:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a68:	01078463          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    call zeroize_block
+80000a6c:	02c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:548
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000a70:	00001717          	auipc	a4,0x1
+80000a74:	19070713          	addi	a4,a4,400 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+    la  a5, __data_start
+80000a78:	00001797          	auipc	a5,0x1
+80000a7c:	18878793          	addi	a5,a5,392 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a6, __data_end
+80000a80:	8c018813          	addi	a6,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000a84:	00f70663          	beq	a4,a5,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000a88:	01078463          	beq	a5,a6,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    call block_copy
+80000a8c:	02c000ef          	jal	ra,80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:556
+
+1:
+    mv ra, t0           /* Retrieve ra */
+80000a90:	00028093          	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+    ret
+80000a94:	00008067          	ret
+
+80000a98 <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:560
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000a98:	04f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000a9c:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    andi a7, a7, 0x03u
+80000aa0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000aa4:	03104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000aa8 <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:565
+zeroize_loop:
+    sw x0, 0(a5)
+80000aa8:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+    add a5, a5, __SIZEOF_POINTER__
+80000aac:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    blt a5, a6, zeroize_loop
+80000ab0:	ff07cce3          	blt	a5,a6,80000aa8 <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    ret
+80000ab4:	00008067          	ret
+
+80000ab8 <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:571
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000ab8:	02f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000abc:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    andi a7, a7, 0x03u
+80000ac0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000ac4:	01104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000ac8 <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:576
+block_copy_loop:
+    lw a7, 0(a4)
+80000ac8:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+    sw a7, 0(a5)
+80000acc:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    addi a5, a5, 0x04
+80000ad0:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a4, a4, 0x04
+80000ad4:	00470713          	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    blt a5, a6, block_copy_loop
+80000ad8:	ff07c8e3          	blt	a5,a6,80000ac8 <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    j block_copy_exit
+80000adc:	0080006f          	j	80000ae4 <block_copy_exit>
+
+80000ae0 <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:584
+
+block_copy_error:
+    j block_copy_error
+80000ae0:	0000006f          	j	80000ae0 <block_copy_error>
+
+80000ae4 <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:587
+
+block_copy_exit:
+    ret
+80000ae4:	00008067          	ret
+
+80000ae8 <MRV_clear_soft_irq>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:730
+
+  @return
+  This function does not return any value.
+ */
+static inline void MRV_clear_soft_irq(void)
+{
+80000ae8:	ff010113          	addi	sp,sp,-16
+80000aec:	00812623          	sw	s0,12(sp)
+80000af0:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000af4:	000067b7          	lui	a5,0x6
+80000af8:	0207a703          	lw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+80000afc:	000067b7          	lui	a5,0x6
+80000b00:	ffd77713          	andi	a4,a4,-3
+80000b04:	02e7a023          	sw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:737
+#endif
+}
+80000b08:	00000013          	nop
+80000b0c:	00c12403          	lw	s0,12(sp)
+80000b10:	01010113          	addi	sp,sp,16
+80000b14:	00008067          	ret
+
+80000b18 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000b18:	fd010113          	addi	sp,sp,-48
+80000b1c:	02112623          	sw	ra,44(sp)
+80000b20:	02812423          	sw	s0,40(sp)
+80000b24:	03010413          	addi	s0,sp,48
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+80000b28:	08000793          	li	a5,128
+80000b2c:	3047b7f3          	csrrc	a5,mie,a5
+80000b30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MTIME;
+80000b34:	0200c7b7          	lui	a5,0x200c
+80000b38:	ff878793          	addi	a5,a5,-8 # 200bff8 <RAM_SIZE+0x2003ff8>
+80000b3c:	0007a783          	lw	a5,0(a5)
+80000b40:	fef42023          	sw	a5,-32(s0)
+80000b44:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000b48:	05c0006f          	j	80000ba4 <handle_m_timer_interrupt+0x8c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000b4c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b50:	0047a803          	lw	a6,4(a5)
+80000b54:	0007a783          	lw	a5,0(a5)
+80000b58:	8c018713          	addi	a4,gp,-1856 # 80001cc0 <__data_end>
+80000b5c:	00072583          	lw	a1,0(a4)
+80000b60:	00472603          	lw	a2,4(a4)
+80000b64:	00b786b3          	add	a3,a5,a1
+80000b68:	00068513          	mv	a0,a3
+80000b6c:	00f53533          	sltu	a0,a0,a5
+80000b70:	00c80733          	add	a4,a6,a2
+80000b74:	00e507b3          	add	a5,a0,a4
+80000b78:	00078713          	mv	a4,a5
+80000b7c:	00068793          	mv	a5,a3
+80000b80:	00070813          	mv	a6,a4
+80000b84:	8c818713          	addi	a4,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b88:	00f72023          	sw	a5,0(a4)
+80000b8c:	01072223          	sw	a6,4(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:205
+
+#ifndef NDEBUG
+        d_tick += 1;
+80000b90:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000b94:	0007a783          	lw	a5,0(a5)
+80000b98:	00178713          	addi	a4,a5,1
+80000b9c:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000ba0:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000ba4:	fe042783          	lw	a5,-32(s0)
+80000ba8:	fe442803          	lw	a6,-28(s0)
+80000bac:	00500593          	li	a1,5
+80000bb0:	00000613          	li	a2,0
+80000bb4:	00b786b3          	add	a3,a5,a1
+80000bb8:	00068513          	mv	a0,a3
+80000bbc:	00f53533          	sltu	a0,a0,a5
+80000bc0:	00c80733          	add	a4,a6,a2
+80000bc4:	00e507b3          	add	a5,a0,a4
+80000bc8:	00078713          	mv	a4,a5
+80000bcc:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000bd0:	0047a803          	lw	a6,4(a5)
+80000bd4:	0007a783          	lw	a5,0(a5)
+80000bd8:	00070593          	mv	a1,a4
+80000bdc:	00080613          	mv	a2,a6
+80000be0:	f6b666e3          	bltu	a2,a1,80000b4c <handle_m_timer_interrupt+0x34>
+80000be4:	00070593          	mv	a1,a4
+80000be8:	00080613          	mv	a2,a6
+80000bec:	00c59663          	bne	a1,a2,80000bf8 <handle_m_timer_interrupt+0xe0>
+80000bf0:	00068713          	mv	a4,a3
+80000bf4:	f4e7ece3          	bltu	a5,a4,80000b4c <handle_m_timer_interrupt+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+80000bf8:	020047b7          	lui	a5,0x2004
+80000bfc:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c00:	fff00713          	li	a4,-1
+80000c04:	00e7a023          	sw	a4,0(a5)
+80000c08:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c0c:	0047a803          	lw	a6,4(a5)
+80000c10:	0007a783          	lw	a5,0(a5)
+80000c14:	02004737          	lui	a4,0x2004
+80000c18:	00f72023          	sw	a5,0(a4) # 2004000 <RAM_SIZE+0x1ffc000>
+80000c1c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c20:	0047a803          	lw	a6,4(a5)
+80000c24:	0007a783          	lw	a5,0(a5)
+80000c28:	00085313          	srli	t1,a6,0x0
+80000c2c:	00000393          	li	t2,0
+80000c30:	020047b7          	lui	a5,0x2004
+80000c34:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c38:	00030713          	mv	a4,t1
+80000c3c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000c40:	290000ef          	jal	ra,80000ed0 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000c44:	08000793          	li	a5,128
+80000c48:	3047a7f3          	csrrs	a5,mie,a5
+80000c4c:	fcf42e23          	sw	a5,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+80000c50:	00000013          	nop
+80000c54:	02c12083          	lw	ra,44(sp)
+80000c58:	02812403          	lw	s0,40(sp)
+80000c5c:	03010113          	addi	sp,sp,48
+80000c60:	00008067          	ret
+
+80000c64 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+80000c64:	ff010113          	addi	sp,sp,-16
+80000c68:	00112623          	sw	ra,12(sp)
+80000c6c:	00812423          	sw	s0,8(sp)
+80000c70:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+80000c74:	244000ef          	jal	ra,80000eb8 <Software_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:233
+    MRV_clear_soft_irq();
+80000c78:	e71ff0ef          	jal	ra,80000ae8 <MRV_clear_soft_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+}
+80000c7c:	00000013          	nop
+80000c80:	00c12083          	lw	ra,12(sp)
+80000c84:	00812403          	lw	s0,8(sp)
+80000c88:	01010113          	addi	sp,sp,16
+80000c8c:	00008067          	ret
+
+80000c90 <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:305
+
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+80000c90:	fc010113          	addi	sp,sp,-64
+80000c94:	02112e23          	sw	ra,60(sp)
+80000c98:	02812c23          	sw	s0,56(sp)
+80000c9c:	04010413          	addi	s0,sp,64
+80000ca0:	00050793          	mv	a5,a0
+80000ca4:	fcf407a3          	sb	a5,-49(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+    uint64_t mhart_id = read_csr(mhartid);
+80000ca8:	f14027f3          	csrr	a5,mhartid
+80000cac:	fef42623          	sw	a5,-20(s0)
+80000cb0:	fec42783          	lw	a5,-20(s0)
+80000cb4:	fef42023          	sw	a5,-32(s0)
+80000cb8:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+80000cbc:	fcf44703          	lbu	a4,-49(s0)
+80000cc0:	01f00793          	li	a5,31
+80000cc4:	00e7f463          	bgeu	a5,a4,80000ccc <handle_local_ei_interrupts+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307 (discriminator 1)
+80000cc8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+80000ccc:	fcf44703          	lbu	a4,-49(s0)
+80000cd0:	00f00793          	li	a5,15
+80000cd4:	00e7e463          	bltu	a5,a4,80000cdc <handle_local_ei_interrupts+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308 (discriminator 1)
+80000cd8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+80000cdc:	fcf44783          	lbu	a5,-49(s0)
+80000ce0:	ff078793          	addi	a5,a5,-16
+80000ce4:	fcf40fa3          	sb	a5,-33(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+80000ce8:	fdf44783          	lbu	a5,-33(s0)
+80000cec:	00001717          	auipc	a4,0x1
+80000cf0:	ed470713          	addi	a4,a4,-300 # 80001bc0 <local_irq_handler_table>
+80000cf4:	00279793          	slli	a5,a5,0x2
+80000cf8:	00f707b3          	add	a5,a4,a5
+80000cfc:	0007a783          	lw	a5,0(a5)
+80000d00:	000780e7          	jalr	a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:312
+}
+80000d04:	00000013          	nop
+80000d08:	03c12083          	lw	ra,60(sp)
+80000d0c:	03812403          	lw	s0,56(sp)
+80000d10:	04010113          	addi	sp,sp,64
+80000d14:	00008067          	ret
+
+80000d18 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+
+/*------------------------------------------------------------------------------
+ * Trap handler. This function is invoked in the non-vectored mode.
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+80000d18:	fa010113          	addi	sp,sp,-96
+80000d1c:	04112e23          	sw	ra,92(sp)
+80000d20:	04812c23          	sw	s0,88(sp)
+80000d24:	06010413          	addi	s0,sp,96
+80000d28:	faa42623          	sw	a0,-84(s0)
+80000d2c:	fab42423          	sw	a1,-88(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:321
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+80000d30:	fac42703          	lw	a4,-84(s0)
+80000d34:	00070793          	mv	a5,a4
+80000d38:	00000813          	li	a6,0
+80000d3c:	80000737          	lui	a4,0x80000
+80000d40:	00e7f733          	and	a4,a5,a4
+80000d44:	fee42423          	sw	a4,-24(s0)
+80000d48:	00087793          	andi	a5,a6,0
+80000d4c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+
+    if (is_interrupt)
+80000d50:	fe842783          	lw	a5,-24(s0)
+80000d54:	fec42703          	lw	a4,-20(s0)
+80000d58:	00e7e7b3          	or	a5,a5,a4
+80000d5c:	0a078063          	beqz	a5,80000dfc <handle_trap+0xe4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+80000d60:	fac42703          	lw	a4,-84(s0)
+80000d64:	800007b7          	lui	a5,0x80000
+80000d68:	ff07c793          	xori	a5,a5,-16
+80000d6c:	00f777b3          	and	a5,a4,a5
+80000d70:	02078663          	beqz	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+80000d74:	fac42703          	lw	a4,-84(s0)
+80000d78:	800007b7          	lui	a5,0x80000
+80000d7c:	fe07c793          	xori	a5,a5,-32
+80000d80:	00f777b3          	and	a5,a4,a5
+80000d84:	00079c63          	bnez	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000d88:	fac42783          	lw	a5,-84(s0)
+80000d8c:	0ff7f793          	andi	a5,a5,255
+80000d90:	00078513          	mv	a0,a5
+80000d94:	efdff0ef          	jal	ra,80000c90 <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+#endif  /* NDEBUG */
+    }
+}
+80000d98:	0c80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000d9c:	fac42703          	lw	a4,-84(s0)
+80000da0:	800007b7          	lui	a5,0x80000
+80000da4:	fff7c793          	not	a5,a5
+80000da8:	00f77733          	and	a4,a4,a5
+80000dac:	00b00793          	li	a5,11
+80000db0:	00f71663          	bne	a4,a5,80000dbc <handle_trap+0xa4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+            External_IRQHandler();
+80000db4:	138000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000db8:	0a80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000dbc:	fac42703          	lw	a4,-84(s0)
+80000dc0:	800007b7          	lui	a5,0x80000
+80000dc4:	fff7c793          	not	a5,a5
+80000dc8:	00f77733          	and	a4,a4,a5
+80000dcc:	00300793          	li	a5,3
+80000dd0:	00f71663          	bne	a4,a5,80000ddc <handle_trap+0xc4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+            handle_m_soft_interrupt();
+80000dd4:	e91ff0ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000dd8:	0880006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+80000ddc:	fac42703          	lw	a4,-84(s0)
+80000de0:	800007b7          	lui	a5,0x80000
+80000de4:	fff7c793          	not	a5,a5
+80000de8:	00f77733          	and	a4,a4,a5
+80000dec:	00700793          	li	a5,7
+80000df0:	06f71863          	bne	a4,a5,80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+            handle_m_timer_interrupt();
+80000df4:	d25ff0ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000df8:	0680006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:382
+         uintptr_t mip      = read_csr(mip);
+80000dfc:	344027f3          	csrr	a5,mip
+80000e00:	fef42223          	sw	a5,-28(s0)
+80000e04:	fe442783          	lw	a5,-28(s0)
+80000e08:	fef42023          	sw	a5,-32(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:385
+         uintptr_t mtval = read_csr(mtval);
+80000e0c:	343027f3          	csrr	a5,mtval
+80000e10:	fcf42e23          	sw	a5,-36(s0)
+80000e14:	fdc42783          	lw	a5,-36(s0)
+80000e18:	fcf42c23          	sw	a5,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:388
+         uintptr_t mtvec    = read_csr(mtvec);
+80000e1c:	305027f3          	csrr	a5,mtvec
+80000e20:	fcf42a23          	sw	a5,-44(s0)
+80000e24:	fd442783          	lw	a5,-44(s0)
+80000e28:	fcf42823          	sw	a5,-48(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:391
+         uintptr_t mscratch = read_csr(mscratch);
+80000e2c:	340027f3          	csrr	a5,mscratch
+80000e30:	fcf42623          	sw	a5,-52(s0)
+80000e34:	fcc42783          	lw	a5,-52(s0)
+80000e38:	fcf42423          	sw	a5,-56(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:394
+         uintptr_t mstatus  = read_csr(mstatus);
+80000e3c:	300027f3          	csrr	a5,mstatus
+80000e40:	fcf42223          	sw	a5,-60(s0)
+80000e44:	fc442783          	lw	a5,-60(s0)
+80000e48:	fcf42023          	sw	a5,-64(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:397
+         uintptr_t mmepc  = read_csr(mepc);
+80000e4c:	341027f3          	csrr	a5,mepc
+80000e50:	faf42e23          	sw	a5,-68(s0)
+80000e54:	fbc42783          	lw	a5,-68(s0)
+80000e58:	faf42c23          	sw	a5,-72(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:400
+        __asm__("ebreak");
+80000e5c:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000e60:	00000013          	nop
+80000e64:	05c12083          	lw	ra,92(sp)
+80000e68:	05812403          	lw	s0,88(sp)
+80000e6c:	06010113          	addi	sp,sp,96
+80000e70:	00008067          	ret
+
+80000e74 <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:21
+#endif
+
+extern void main(void);
+
+void _init(void)
+{
+80000e74:	ff010113          	addi	sp,sp,-16
+80000e78:	00112623          	sw	ra,12(sp)
+80000e7c:	00812423          	sw	s0,8(sp)
+80000e80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+80000e84:	4b1000ef          	jal	ra,80001b34 <main>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:28
+}
+80000e88:	00000013          	nop
+80000e8c:	00c12083          	lw	ra,12(sp)
+80000e90:	00812403          	lw	s0,8(sp)
+80000e94:	01010113          	addi	sp,sp,16
+80000e98:	00008067          	ret
+
+80000e9c <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:33
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+80000e9c:	ff010113          	addi	sp,sp,-16
+80000ea0:	00812623          	sw	s0,12(sp)
+80000ea4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+}
+80000ea8:	00000013          	nop
+80000eac:	00c12403          	lw	s0,12(sp)
+80000eb0:	01010113          	addi	sp,sp,16
+80000eb4:	00008067          	ret
+
+80000eb8 <Software_IRQHandler>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000eb8:	ff010113          	addi	sp,sp,-16
+80000ebc:	00112623          	sw	ra,12(sp)
+80000ec0:	00812423          	sw	s0,8(sp)
+80000ec4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000ec8:	00a00513          	li	a0,10
+80000ecc:	188000ef          	jal	ra,80001054 <_exit>
+
+80000ed0 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:28
+}
+
+__attribute__((weak)) void SysTick_Handler(void)
+{
+80000ed0:	ff010113          	addi	sp,sp,-16
+80000ed4:	00812623          	sw	s0,12(sp)
+80000ed8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:30
+    /* Default handler */
+}
+80000edc:	00000013          	nop
+80000ee0:	00c12403          	lw	s0,12(sp)
+80000ee4:	01010113          	addi	sp,sp,16
+80000ee8:	00008067          	ret
+
+80000eec <External_IRQHandler>:
+External_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:195
+    return(0U); /* Default handler */
+}
+
+#else
+__attribute__((weak)) void External_IRQHandler(void)
+{
+80000eec:	ff010113          	addi	sp,sp,-16
+80000ef0:	00812623          	sw	s0,12(sp)
+80000ef4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:196
+}
+80000ef8:	00000013          	nop
+80000efc:	00c12403          	lw	s0,12(sp)
+80000f00:	01010113          	addi	sp,sp,16
+80000f04:	00008067          	ret
+
+80000f08 <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:198
+__attribute__((weak)) void MGECI_IRQHandler(void)
+{
+80000f08:	ff010113          	addi	sp,sp,-16
+80000f0c:	00812623          	sw	s0,12(sp)
+80000f10:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:199
+}
+80000f14:	00000013          	nop
+80000f18:	00c12403          	lw	s0,12(sp)
+80000f1c:	01010113          	addi	sp,sp,16
+80000f20:	00008067          	ret
+
+80000f24 <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:201
+__attribute__((weak)) void MGEUI_IRQHandler(void)
+{
+80000f24:	ff010113          	addi	sp,sp,-16
+80000f28:	00812623          	sw	s0,12(sp)
+80000f2c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:202
+}
+80000f30:	00000013          	nop
+80000f34:	00c12403          	lw	s0,12(sp)
+80000f38:	01010113          	addi	sp,sp,16
+80000f3c:	00008067          	ret
+
+80000f40 <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:204
+__attribute__((weak)) void SUBSYS_IRQHandler(void)
+{
+80000f40:	ff010113          	addi	sp,sp,-16
+80000f44:	00812623          	sw	s0,12(sp)
+80000f48:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:205
+}
+80000f4c:	00000013          	nop
+80000f50:	00c12403          	lw	s0,12(sp)
+80000f54:	01010113          	addi	sp,sp,16
+80000f58:	00008067          	ret
+
+80000f5c <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:210
+__attribute__((weak)) void MSYS_EI0_IRQHandler(void)
+{
+}
+__attribute__((weak)) void MSYS_EI1_IRQHandler(void)
+{
+80000f5c:	ff010113          	addi	sp,sp,-16
+80000f60:	00812623          	sw	s0,12(sp)
+80000f64:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:211
+}
+80000f68:	00000013          	nop
+80000f6c:	00c12403          	lw	s0,12(sp)
+80000f70:	01010113          	addi	sp,sp,16
+80000f74:	00008067          	ret
+
+80000f78 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:213
+__attribute__((weak)) void MSYS_EI2_IRQHandler(void)
+{
+80000f78:	ff010113          	addi	sp,sp,-16
+80000f7c:	00812623          	sw	s0,12(sp)
+80000f80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:214
+}
+80000f84:	00000013          	nop
+80000f88:	00c12403          	lw	s0,12(sp)
+80000f8c:	01010113          	addi	sp,sp,16
+80000f90:	00008067          	ret
+
+80000f94 <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:216
+__attribute__((weak)) void MSYS_EI3_IRQHandler(void)
+{
+80000f94:	ff010113          	addi	sp,sp,-16
+80000f98:	00812623          	sw	s0,12(sp)
+80000f9c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:217
+}
+80000fa0:	00000013          	nop
+80000fa4:	00c12403          	lw	s0,12(sp)
+80000fa8:	01010113          	addi	sp,sp,16
+80000fac:	00008067          	ret
+
+80000fb0 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:219
+__attribute__((weak)) void MSYS_EI4_IRQHandler(void)
+{
+80000fb0:	ff010113          	addi	sp,sp,-16
+80000fb4:	00812623          	sw	s0,12(sp)
+80000fb8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:220
+}
+80000fbc:	00000013          	nop
+80000fc0:	00c12403          	lw	s0,12(sp)
+80000fc4:	01010113          	addi	sp,sp,16
+80000fc8:	00008067          	ret
+
+80000fcc <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:222
+__attribute__((weak)) void MSYS_EI5_IRQHandler(void)
+{
+80000fcc:	ff010113          	addi	sp,sp,-16
+80000fd0:	00812623          	sw	s0,12(sp)
+80000fd4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:223
+}
+80000fd8:	00000013          	nop
+80000fdc:	00c12403          	lw	s0,12(sp)
+80000fe0:	01010113          	addi	sp,sp,16
+80000fe4:	00008067          	ret
+
+80000fe8 <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:225
+__attribute__((weak)) void Reserved_IRQHandler(void)
+{
+80000fe8:	ff010113          	addi	sp,sp,-16
+80000fec:	00112623          	sw	ra,12(sp)
+80000ff0:	00812423          	sw	s0,8(sp)
+80000ff4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:226
+    _exit(10);
+80000ff8:	00a00513          	li	a0,10
+80000ffc:	058000ef          	jal	ra,80001054 <_exit>
+
+80001000 <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:230
+}
+#ifndef MIV_RV32_V3_0 /* For MIV_RV32 v3.0 */
+__attribute__((weak)) void MSYS_EI6_IRQHandler(void)
+{
+80001000:	ff010113          	addi	sp,sp,-16
+80001004:	00812623          	sw	s0,12(sp)
+80001008:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:231
+}
+8000100c:	00000013          	nop
+80001010:	00c12403          	lw	s0,12(sp)
+80001014:	01010113          	addi	sp,sp,16
+80001018:	00008067          	ret
+
+8000101c <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:233
+__attribute__((weak)) void MSYS_EI7_IRQHandler(void)
+{
+8000101c:	ff010113          	addi	sp,sp,-16
+80001020:	00812623          	sw	s0,12(sp)
+80001024:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:234
+}
+80001028:	00000013          	nop
+8000102c:	00c12403          	lw	s0,12(sp)
+80001030:	01010113          	addi	sp,sp,16
+80001034:	00008067          	ret
+
+80001038 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:236
+__attribute__((weak)) void SUBSYSR_IRQHandler(void)
+{
+80001038:	ff010113          	addi	sp,sp,-16
+8000103c:	00812623          	sw	s0,12(sp)
+80001040:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:237
+}
+80001044:	00000013          	nop
+80001048:	00c12403          	lw	s0,12(sp)
+8000104c:	01010113          	addi	sp,sp,16
+80001050:	00008067          	ret
+
+80001054 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:142
+#ifdef GDB_TESTING
+void __attribute__((optimize("O0"))) _exit(int code)
+#else
+void _exit(int code)
+#endif
+{
+80001054:	fe010113          	addi	sp,sp,-32
+80001058:	00812e23          	sw	s0,28(sp)
+8000105c:	02010413          	addi	s0,sp,32
+80001060:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80001064:	0000006f          	j	80001064 <_exit+0x10>
+
+80001068 <MRV_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:616
+
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+80001068:	fe010113          	addi	sp,sp,-32
+8000106c:	00812e23          	sw	s0,28(sp)
+80001070:	02010413          	addi	s0,sp,32
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80001074:	300467f3          	csrrsi	a5,mstatus,8
+80001078:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:618
+}
+8000107c:	00000013          	nop
+80001080:	01c12403          	lw	s0,28(sp)
+80001084:	02010113          	addi	sp,sp,32
+80001088:	00008067          	ret
+
+8000108c <HAL_enable_interrupts>:
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:22
+#endif
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+8000108c:	ff010113          	addi	sp,sp,-16
+80001090:	00112623          	sw	ra,12(sp)
+80001094:	00812423          	sw	s0,8(sp)
+80001098:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:23
+    MRV_enable_interrupts();
+8000109c:	fcdff0ef          	jal	ra,80001068 <MRV_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:24
+}
+800010a0:	00000013          	nop
+800010a4:	00c12083          	lw	ra,12(sp)
+800010a8:	00812403          	lw	s0,8(sp)
+800010ac:	01010113          	addi	sp,sp,16
+800010b0:	00008067          	ret
+
+800010b4 <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+800010b4:	00b52023          	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:40
+    ret
+800010b8:	00008067          	ret
+
+800010bc <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+800010bc:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:52
+    ret
+800010c0:	00008067          	ret
+
+800010c4 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+800010c4:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+800010c8:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+800010cc:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+800010d0:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+800010d4:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+800010d8:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+800010dc:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+800010e0:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+800010e4:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:73
+    ret
+800010e8:	00008067          	ret
+
+800010ec <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+800010ec:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+800010f0:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+800010f4:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:90
+    ret
+800010f8:	00008067          	ret
+
+800010fc <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+800010fc:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:101
+    ret
+80001100:	00008067          	ret
+
+80001104 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+80001104:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:113
+    ret
+80001108:	00008067          	ret
+
+8000110c <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+8000110c:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80001110:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80001114:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80001118:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+8000111c:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+80001120:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80001124:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80001128:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+8000112c:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:135
+    ret
+80001130:	00008067          	ret
+
+80001134 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80001134:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80001138:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+8000113c:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:152
+    ret
+80001140:	00008067          	ret
+
+80001144 <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+80001144:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:163
+    ret
+80001148:	00008067          	ret
+
+8000114c <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+8000114c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:175
+    ret
+80001150:	00008067          	ret
+
+80001154 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80001154:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+80001158:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+8000115c:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80001160:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80001164:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80001168:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+8000116c:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80001170:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80001174:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:196
+    ret
+80001178:	00008067          	ret
+
+8000117c <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+8000117c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+80001180:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80001184:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:213
+    ret
+80001188:	00008067          	ret
+
+8000118c <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+    UART_instance_t * this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+)
+{
+8000118c:	fd010113          	addi	sp,sp,-48
+80001190:	02112623          	sw	ra,44(sp)
+80001194:	02812423          	sw	s0,40(sp)
+80001198:	03010413          	addi	s0,sp,48
+8000119c:	fca42e23          	sw	a0,-36(s0)
+800011a0:	fcb42c23          	sw	a1,-40(s0)
+800011a4:	00060793          	mv	a5,a2
+800011a8:	00068713          	mv	a4,a3
+800011ac:	fcf41b23          	sh	a5,-42(s0)
+800011b0:	00070793          	mv	a5,a4
+800011b4:	fcf40aa3          	sb	a5,-43(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49
+    uint8_t rx_full;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+800011b8:	fdc42783          	lw	a5,-36(s0)
+800011bc:	00079463          	bnez	a5,800011c4 <UART_init+0x38>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49 (discriminator 1)
+800011c0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+800011c4:	fd544703          	lbu	a4,-43(s0)
+800011c8:	00700793          	li	a5,7
+800011cc:	00e7f463          	bgeu	a5,a4,800011d4 <UART_init+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50 (discriminator 1)
+800011d0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+800011d4:	fd645703          	lhu	a4,-42(s0)
+800011d8:	000027b7          	lui	a5,0x2
+800011dc:	00f76463          	bltu	a4,a5,800011e4 <UART_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51 (discriminator 1)
+800011e0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+800011e4:	fdc42783          	lw	a5,-36(s0)
+800011e8:	16078463          	beqz	a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+800011ec:	fd544703          	lbu	a4,-43(s0)
+800011f0:	00700793          	li	a5,7
+800011f4:	14e7ee63          	bltu	a5,a4,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+800011f8:	fd645703          	lhu	a4,-42(s0)
+800011fc:	000027b7          	lui	a5,0x2
+80001200:	14f77863          	bgeu	a4,a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80001204:	fd842783          	lw	a5,-40(s0)
+80001208:	00878713          	addi	a4,a5,8 # 2008 <STACK_SIZE+0x1808>
+8000120c:	fd645783          	lhu	a5,-42(s0)
+80001210:	0ff7f793          	andi	a5,a5,255
+80001214:	00078593          	mv	a1,a5
+80001218:	00070513          	mv	a0,a4
+8000121c:	f29ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80001220:	fd842783          	lw	a5,-40(s0)
+80001224:	00c78693          	addi	a3,a5,12
+80001228:	fd544703          	lbu	a4,-43(s0)
+8000122c:	fd645783          	lhu	a5,-42(s0)
+80001230:	4057d793          	srai	a5,a5,0x5
+80001234:	7f87f793          	andi	a5,a5,2040
+80001238:	00f767b3          	or	a5,a4,a5
+8000123c:	00078593          	mv	a1,a5
+80001240:	00068513          	mv	a0,a3
+80001244:	f01ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+                                           (uint_fast8_t)((baud_value &
+                                   BAUDVALUE_MSB) >> BAUDVALUE_SHIFT ) );
+    
+        this_uart->base_address = base_addr;
+80001248:	fdc42783          	lw	a5,-36(s0)
+8000124c:	fd842703          	lw	a4,-40(s0)
+80001250:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:77
+#ifndef NDEBUG
+        {
+            uint8_t  config;
+            uint8_t  temp;
+            uint16_t baud_val;
+            baud_val = HAL_get_8bit_reg( this_uart->base_address, CTRL1 );
+80001254:	fdc42783          	lw	a5,-36(s0)
+80001258:	0007a783          	lw	a5,0(a5)
+8000125c:	00878793          	addi	a5,a5,8
+80001260:	00078513          	mv	a0,a5
+80001264:	ee9ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001268:	00050793          	mv	a5,a0
+8000126c:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:78
+            config =  HAL_get_8bit_reg( this_uart->base_address, CTRL2 );
+80001270:	fdc42783          	lw	a5,-36(s0)
+80001274:	0007a783          	lw	a5,0(a5)
+80001278:	00c78793          	addi	a5,a5,12
+8000127c:	00078513          	mv	a0,a5
+80001280:	ecdff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001284:	00050793          	mv	a5,a0
+80001288:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:82
+            /*
+             * To resolve operator precedence between & and <<
+             */
+            temp =  ( config  &  (uint8_t)(CTRL2_BAUDVALUE_MASK ) );
+8000128c:	feb44783          	lbu	a5,-21(s0)
+80001290:	ff87f793          	andi	a5,a5,-8
+80001294:	fef40523          	sb	a5,-22(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:83
+            baud_val |= (uint16_t)( (uint16_t)(temp) << BAUDVALUE_SHIFT );
+80001298:	fea44783          	lbu	a5,-22(s0)
+8000129c:	01079793          	slli	a5,a5,0x10
+800012a0:	0107d793          	srli	a5,a5,0x10
+800012a4:	00579793          	slli	a5,a5,0x5
+800012a8:	01079713          	slli	a4,a5,0x10
+800012ac:	01075713          	srli	a4,a4,0x10
+800012b0:	fec45783          	lhu	a5,-20(s0)
+800012b4:	00f767b3          	or	a5,a4,a5
+800012b8:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:84
+            config &= (uint8_t)(~CTRL2_BAUDVALUE_MASK);
+800012bc:	feb44783          	lbu	a5,-21(s0)
+800012c0:	0077f793          	andi	a5,a5,7
+800012c4:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85
+            HAL_ASSERT( baud_val == baud_value );
+800012c8:	fec45703          	lhu	a4,-20(s0)
+800012cc:	fd645783          	lhu	a5,-42(s0)
+800012d0:	00f70463          	beq	a4,a5,800012d8 <UART_init+0x14c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85 (discriminator 1)
+800012d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86
+            HAL_ASSERT( config == line_config );
+800012d8:	feb44703          	lbu	a4,-21(s0)
+800012dc:	fd544783          	lbu	a5,-43(s0)
+800012e0:	00f70463          	beq	a4,a5,800012e8 <UART_init+0x15c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86 (discriminator 1)
+800012e4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800012e8:	fdc42783          	lw	a5,-36(s0)
+800012ec:	0007a783          	lw	a5,0(a5)
+800012f0:	01078793          	addi	a5,a5,16
+800012f4:	00078513          	mv	a0,a5
+800012f8:	e55ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800012fc:	00050793          	mv	a5,a0
+80001300:	0027f793          	andi	a5,a5,2
+80001304:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+80001308:	0380006f          	j	80001340 <UART_init+0x1b4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+8000130c:	fdc42783          	lw	a5,-36(s0)
+80001310:	0007a783          	lw	a5,0(a5)
+80001314:	00478793          	addi	a5,a5,4
+80001318:	00078513          	mv	a0,a5
+8000131c:	e31ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80001320:	fdc42783          	lw	a5,-36(s0)
+80001324:	0007a783          	lw	a5,0(a5)
+80001328:	01078793          	addi	a5,a5,16
+8000132c:	00078513          	mv	a0,a5
+80001330:	e1dff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001334:	00050793          	mv	a5,a0
+80001338:	0027f793          	andi	a5,a5,2
+8000133c:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+80001340:	fef44783          	lbu	a5,-17(s0)
+80001344:	fc0794e3          	bnez	a5,8000130c <UART_init+0x180>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+80001348:	fdc42783          	lw	a5,-36(s0)
+8000134c:	00078223          	sb	zero,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+80001350:	00000013          	nop
+80001354:	02c12083          	lw	ra,44(sp)
+80001358:	02812403          	lw	s0,40(sp)
+8000135c:	03010113          	addi	sp,sp,48
+80001360:	00008067          	ret
+
+80001364 <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+UART_polled_tx_string
+( 
+    UART_instance_t * this_uart, 
+    const uint8_t * p_sz_string
+)
+{
+80001364:	fd010113          	addi	sp,sp,-48
+80001368:	02112623          	sw	ra,44(sp)
+8000136c:	02812423          	sw	s0,40(sp)
+80001370:	03010413          	addi	s0,sp,48
+80001374:	fca42e23          	sw	a0,-36(s0)
+80001378:	fcb42c23          	sw	a1,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243
+    uint32_t char_idx;
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+8000137c:	fdc42783          	lw	a5,-36(s0)
+80001380:	00079463          	bnez	a5,80001388 <UART_polled_tx_string+0x24>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243 (discriminator 1)
+80001384:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+80001388:	fd842783          	lw	a5,-40(s0)
+8000138c:	00079463          	bnez	a5,80001394 <UART_polled_tx_string+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244 (discriminator 1)
+80001390:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+80001394:	fdc42783          	lw	a5,-36(s0)
+80001398:	08078063          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+8000139c:	fd842783          	lw	a5,-40(s0)
+800013a0:	06078c63          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:248
+    {
+        char_idx = 0U;
+800013a4:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+800013a8:	05c0006f          	j	80001404 <UART_polled_tx_string+0xa0>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+        {
+            /* Wait for UART to become ready to transmit. */
+            do {
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800013ac:	fdc42783          	lw	a5,-36(s0)
+800013b0:	0007a783          	lw	a5,0(a5)
+800013b4:	01078793          	addi	a5,a5,16
+800013b8:	00078513          	mv	a0,a5
+800013bc:	d91ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800013c0:	00050793          	mv	a5,a0
+800013c4:	0017f793          	andi	a5,a5,1
+800013c8:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+                                                              STATUS_TXRDY_MASK;
+            } while ( !tx_ready );
+800013cc:	feb44783          	lbu	a5,-21(s0)
+800013d0:	fc078ee3          	beqz	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            /* Send next character in the buffer. */
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+800013d4:	fdc42783          	lw	a5,-36(s0)
+800013d8:	0007a683          	lw	a3,0(a5)
+800013dc:	fd842703          	lw	a4,-40(s0)
+800013e0:	fec42783          	lw	a5,-20(s0)
+800013e4:	00f707b3          	add	a5,a4,a5
+800013e8:	0007c783          	lbu	a5,0(a5)
+800013ec:	00078593          	mv	a1,a5
+800013f0:	00068513          	mv	a0,a3
+800013f4:	d51ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+800013f8:	fec42783          	lw	a5,-20(s0)
+800013fc:	00178793          	addi	a5,a5,1
+80001400:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+80001404:	fd842703          	lw	a4,-40(s0)
+80001408:	fec42783          	lw	a5,-20(s0)
+8000140c:	00f707b3          	add	a5,a4,a5
+80001410:	0007c783          	lbu	a5,0(a5)
+80001414:	f8079ce3          	bnez	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+        }
+    }
+}
+80001418:	00000013          	nop
+8000141c:	02c12083          	lw	ra,44(sp)
+80001420:	02812403          	lw	s0,40(sp)
+80001424:	03010113          	addi	sp,sp,48
+80001428:	00008067          	ret
+
+8000142c <TMR_init>:
+TMR_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:30
+    addr_t address,
+    uint8_t mode,
+    uint32_t prescale,
+    uint32_t load_value
+)
+{
+8000142c:	fd010113          	addi	sp,sp,-48
+80001430:	02112623          	sw	ra,44(sp)
+80001434:	02812423          	sw	s0,40(sp)
+80001438:	03010413          	addi	s0,sp,48
+8000143c:	fea42623          	sw	a0,-20(s0)
+80001440:	feb42423          	sw	a1,-24(s0)
+80001444:	00060793          	mv	a5,a2
+80001448:	fed42023          	sw	a3,-32(s0)
+8000144c:	fce42e23          	sw	a4,-36(s0)
+80001450:	fef403a3          	sb	a5,-25(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001454:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001458:	0007a783          	lw	a5,0(a5)
+8000145c:	fec42703          	lw	a4,-20(s0)
+80001460:	00f71463          	bne	a4,a5,80001468 <TMR_init+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31 (discriminator 1)
+80001464:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32
+    HAL_ASSERT( prescale <= PRESCALER_DIV_1024 )
+80001468:	fe042703          	lw	a4,-32(s0)
+8000146c:	00900793          	li	a5,9
+80001470:	00e7f463          	bgeu	a5,a4,80001478 <TMR_init+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32 (discriminator 1)
+80001474:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33
+    HAL_ASSERT( load_value != 0 )
+80001478:	fdc42783          	lw	a5,-36(s0)
+8000147c:	00079463          	bnez	a5,80001484 <TMR_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33 (discriminator 1)
+80001480:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:35
+    
+    this_timer->base_address = address;
+80001484:	fec42783          	lw	a5,-20(s0)
+80001488:	fe842703          	lw	a4,-24(s0)
+8000148c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:38
+
+    /* Disable interrupts. */
+    HAL_set_32bit_reg_field( address, InterruptEnable,0 );
+80001490:	fe842783          	lw	a5,-24(s0)
+80001494:	00878793          	addi	a5,a5,8
+80001498:	00000693          	li	a3,0
+8000149c:	00200613          	li	a2,2
+800014a0:	00100593          	li	a1,1
+800014a4:	00078513          	mv	a0,a5
+800014a8:	c1dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:41
+
+    /* Disable timer. */
+    HAL_set_32bit_reg_field( address, TimerEnable, 0 );
+800014ac:	fe842783          	lw	a5,-24(s0)
+800014b0:	00878793          	addi	a5,a5,8
+800014b4:	00000693          	li	a3,0
+800014b8:	00100613          	li	a2,1
+800014bc:	00000593          	li	a1,0
+800014c0:	00078513          	mv	a0,a5
+800014c4:	c01ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:44
+
+    /* Clear pending interrupt. */
+    HAL_set_32bit_reg( address, TimerIntClr, 1 );
+800014c8:	fe842783          	lw	a5,-24(s0)
+800014cc:	01078793          	addi	a5,a5,16
+800014d0:	00100593          	li	a1,1
+800014d4:	00078513          	mv	a0,a5
+800014d8:	bddff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:47
+
+    /* Configure prescaler and load value. */    
+    HAL_set_32bit_reg( address, TimerPrescale, prescale );
+800014dc:	fe842783          	lw	a5,-24(s0)
+800014e0:	00c78793          	addi	a5,a5,12
+800014e4:	fe042583          	lw	a1,-32(s0)
+800014e8:	00078513          	mv	a0,a5
+800014ec:	bc9ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:48
+    HAL_set_32bit_reg( address, TimerLoad, load_value );
+800014f0:	fdc42583          	lw	a1,-36(s0)
+800014f4:	fe842503          	lw	a0,-24(s0)
+800014f8:	bbdff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:51
+
+    /* Set the interrupt mode. */
+    if ( mode == TMR_CONTINUOUS_MODE )
+800014fc:	fe744783          	lbu	a5,-25(s0)
+80001500:	02079263          	bnez	a5,80001524 <TMR_init+0xf8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:53
+    {
+        HAL_set_32bit_reg_field( address, TimerMode, 0 );
+80001504:	fe842783          	lw	a5,-24(s0)
+80001508:	00878793          	addi	a5,a5,8
+8000150c:	00000693          	li	a3,0
+80001510:	00400613          	li	a2,4
+80001514:	00200593          	li	a1,2
+80001518:	00078513          	mv	a0,a5
+8000151c:	ba9ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+    else
+    {
+        /* TMR_ONE_SHOT_MODE */
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+    }
+}
+80001520:	0200006f          	j	80001540 <TMR_init+0x114>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:58
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+80001524:	fe842783          	lw	a5,-24(s0)
+80001528:	00878793          	addi	a5,a5,8
+8000152c:	00100693          	li	a3,1
+80001530:	00400613          	li	a2,4
+80001534:	00200593          	li	a1,2
+80001538:	00078513          	mv	a0,a5
+8000153c:	b89ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+}
+80001540:	00000013          	nop
+80001544:	02c12083          	lw	ra,44(sp)
+80001548:	02812403          	lw	s0,40(sp)
+8000154c:	03010113          	addi	sp,sp,48
+80001550:	00008067          	ret
+
+80001554 <TMR_start>:
+TMR_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:71
+void
+TMR_start
+(
+    timer_instance_t * this_timer
+)
+{
+80001554:	fe010113          	addi	sp,sp,-32
+80001558:	00112e23          	sw	ra,28(sp)
+8000155c:	00812c23          	sw	s0,24(sp)
+80001560:	02010413          	addi	s0,sp,32
+80001564:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001568:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+8000156c:	0007a783          	lw	a5,0(a5)
+80001570:	fec42703          	lw	a4,-20(s0)
+80001574:	00f71463          	bne	a4,a5,8000157c <TMR_start+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72 (discriminator 1)
+80001578:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:74
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 );
+8000157c:	fec42783          	lw	a5,-20(s0)
+80001580:	0007a783          	lw	a5,0(a5)
+80001584:	00878793          	addi	a5,a5,8
+80001588:	00100693          	li	a3,1
+8000158c:	00100613          	li	a2,1
+80001590:	00000593          	li	a1,0
+80001594:	00078513          	mv	a0,a5
+80001598:	b2dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:75
+}
+8000159c:	00000013          	nop
+800015a0:	01c12083          	lw	ra,28(sp)
+800015a4:	01812403          	lw	s0,24(sp)
+800015a8:	02010113          	addi	sp,sp,32
+800015ac:	00008067          	ret
+
+800015b0 <TMR_enable_int>:
+TMR_enable_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:102
+void
+TMR_enable_int
+(
+    timer_instance_t * this_timer
+)
+{
+800015b0:	fe010113          	addi	sp,sp,-32
+800015b4:	00112e23          	sw	ra,28(sp)
+800015b8:	00812c23          	sw	s0,24(sp)
+800015bc:	02010413          	addi	s0,sp,32
+800015c0:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+800015c4:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+800015c8:	0007a783          	lw	a5,0(a5)
+800015cc:	fec42703          	lw	a4,-20(s0)
+800015d0:	00f71463          	bne	a4,a5,800015d8 <TMR_enable_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103 (discriminator 1)
+800015d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:105
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 );
+800015d8:	fec42783          	lw	a5,-20(s0)
+800015dc:	0007a783          	lw	a5,0(a5)
+800015e0:	00878793          	addi	a5,a5,8
+800015e4:	00100693          	li	a3,1
+800015e8:	00200613          	li	a2,2
+800015ec:	00100593          	li	a1,1
+800015f0:	00078513          	mv	a0,a5
+800015f4:	ad1ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:106
+}
+800015f8:	00000013          	nop
+800015fc:	01c12083          	lw	ra,28(sp)
+80001600:	01812403          	lw	s0,24(sp)
+80001604:	02010113          	addi	sp,sp,32
+80001608:	00008067          	ret
+
+8000160c <TMR_clear_int>:
+TMR_clear_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:117
+void
+TMR_clear_int
+(
+    timer_instance_t * this_timer
+)
+{
+8000160c:	fe010113          	addi	sp,sp,-32
+80001610:	00112e23          	sw	ra,28(sp)
+80001614:	00812c23          	sw	s0,24(sp)
+80001618:	02010413          	addi	s0,sp,32
+8000161c:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001620:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001624:	0007a783          	lw	a5,0(a5)
+80001628:	fec42703          	lw	a4,-20(s0)
+8000162c:	00f71463          	bne	a4,a5,80001634 <TMR_clear_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118 (discriminator 1)
+80001630:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:120
+    
+    HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 );
+80001634:	fec42783          	lw	a5,-20(s0)
+80001638:	0007a783          	lw	a5,0(a5)
+8000163c:	01078793          	addi	a5,a5,16
+80001640:	00100593          	li	a1,1
+80001644:	00078513          	mv	a0,a5
+80001648:	a6dff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:121
+}
+8000164c:	00000013          	nop
+80001650:	01c12083          	lw	ra,28(sp)
+80001654:	01812403          	lw	s0,24(sp)
+80001658:	02010113          	addi	sp,sp,32
+8000165c:	00008067          	ret
+
+80001660 <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+80001660:	fd010113          	addi	sp,sp,-48
+80001664:	02112623          	sw	ra,44(sp)
+80001668:	02812423          	sw	s0,40(sp)
+8000166c:	03010413          	addi	s0,sp,48
+80001670:	fca42e23          	sw	a0,-36(s0)
+80001674:	fcb42c23          	sw	a1,-40(s0)
+80001678:	fcc42a23          	sw	a2,-44(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:38
+    uint8_t i = 0;
+8000167c:	fe0407a3          	sb	zero,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:39
+    addr_t cfg_reg_addr = base_addr;
+80001680:	fd842783          	lw	a5,-40(s0)
+80001684:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    
+    this_gpio->base_addr = base_addr;
+80001688:	fdc42783          	lw	a5,-36(s0)
+8000168c:	fd842703          	lw	a4,-40(s0)
+80001690:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+80001694:	fdc42783          	lw	a5,-36(s0)
+80001698:	fd442703          	lw	a4,-44(s0)
+8000169c:	00e7a223          	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016a0:	fe0407a3          	sb	zero,-17(s0)
+800016a4:	fd842783          	lw	a5,-40(s0)
+800016a8:	fef42423          	sw	a5,-24(s0)
+800016ac:	0280006f          	j	800016d4 <GPIO_init+0x74>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+800016b0:	00000593          	li	a1,0
+800016b4:	fe842503          	lw	a0,-24(s0)
+800016b8:	a8dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+800016bc:	fe842783          	lw	a5,-24(s0)
+800016c0:	00478793          	addi	a5,a5,4
+800016c4:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016c8:	fef44783          	lbu	a5,-17(s0)
+800016cc:	00178793          	addi	a5,a5,1
+800016d0:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 1)
+800016d4:	fef44703          	lbu	a4,-17(s0)
+800016d8:	01f00793          	li	a5,31
+800016dc:	fce7fae3          	bgeu	a5,a4,800016b0 <GPIO_init+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+800016e0:	fdc42783          	lw	a5,-36(s0)
+800016e4:	0047a783          	lw	a5,4(a5)
+800016e8:	00100713          	li	a4,1
+800016ec:	02e78663          	beq	a5,a4,80001718 <GPIO_init+0xb8>
+800016f0:	06078263          	beqz	a5,80001754 <GPIO_init+0xf4>
+800016f4:	00200713          	li	a4,2
+800016f8:	0ce79063          	bne	a5,a4,800017b8 <GPIO_init+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+800016fc:	fdc42783          	lw	a5,-36(s0)
+80001700:	0007a783          	lw	a5,0(a5)
+80001704:	08078793          	addi	a5,a5,128
+80001708:	fff00593          	li	a1,-1
+8000170c:	00078513          	mv	a0,a5
+80001710:	9a5ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:55
+            break;
+80001714:	0ac0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+80001718:	fdc42783          	lw	a5,-36(s0)
+8000171c:	0007a783          	lw	a5,0(a5)
+80001720:	08078713          	addi	a4,a5,128
+80001724:	000107b7          	lui	a5,0x10
+80001728:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+8000172c:	00070513          	mv	a0,a4
+80001730:	9cdff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80001734:	fdc42783          	lw	a5,-36(s0)
+80001738:	0007a783          	lw	a5,0(a5)
+8000173c:	08478713          	addi	a4,a5,132
+80001740:	000107b7          	lui	a5,0x10
+80001744:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+80001748:	00070513          	mv	a0,a4
+8000174c:	9b1ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:60
+            break;
+80001750:	0700006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+80001754:	fdc42783          	lw	a5,-36(s0)
+80001758:	0007a783          	lw	a5,0(a5)
+8000175c:	08078793          	addi	a5,a5,128
+80001760:	0ff00593          	li	a1,255
+80001764:	00078513          	mv	a0,a5
+80001768:	9ddff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+8000176c:	fdc42783          	lw	a5,-36(s0)
+80001770:	0007a783          	lw	a5,0(a5)
+80001774:	08478793          	addi	a5,a5,132
+80001778:	0ff00593          	li	a1,255
+8000177c:	00078513          	mv	a0,a5
+80001780:	9c5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+80001784:	fdc42783          	lw	a5,-36(s0)
+80001788:	0007a783          	lw	a5,0(a5)
+8000178c:	08878793          	addi	a5,a5,136
+80001790:	0ff00593          	li	a1,255
+80001794:	00078513          	mv	a0,a5
+80001798:	9adff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+8000179c:	fdc42783          	lw	a5,-36(s0)
+800017a0:	0007a783          	lw	a5,0(a5)
+800017a4:	08c78793          	addi	a5,a5,140
+800017a8:	0ff00593          	li	a1,255
+800017ac:	00078513          	mv	a0,a5
+800017b0:	995ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:67
+            break;
+800017b4:	00c0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:70 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+800017b8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:71 (discriminator 1)
+            break;
+800017bc:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+    }
+}
+800017c0:	00000013          	nop
+800017c4:	02c12083          	lw	ra,44(sp)
+800017c8:	02812403          	lw	s0,40(sp)
+800017cc:	03010113          	addi	sp,sp,48
+800017d0:	00008067          	ret
+
+800017d4 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+void GPIO_set_outputs
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+800017d4:	fe010113          	addi	sp,sp,-32
+800017d8:	00112e23          	sw	ra,28(sp)
+800017dc:	00812c23          	sw	s0,24(sp)
+800017e0:	02010413          	addi	s0,sp,32
+800017e4:	fea42623          	sw	a0,-20(s0)
+800017e8:	feb42423          	sw	a1,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+800017ec:	fec42783          	lw	a5,-20(s0)
+800017f0:	0047a783          	lw	a5,4(a5)
+800017f4:	00100713          	li	a4,1
+800017f8:	02e78663          	beq	a5,a4,80001824 <GPIO_set_outputs+0x50>
+800017fc:	06078c63          	beqz	a5,80001874 <GPIO_set_outputs+0xa0>
+80001800:	00200713          	li	a4,2
+80001804:	10e79063          	bne	a5,a4,80001904 <GPIO_set_outputs+0x130>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80001808:	fec42783          	lw	a5,-20(s0)
+8000180c:	0007a783          	lw	a5,0(a5)
+80001810:	0a078793          	addi	a5,a5,160
+80001814:	fe842583          	lw	a1,-24(s0)
+80001818:	00078513          	mv	a0,a5
+8000181c:	899ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:119
+            break;
+80001820:	0ec0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+80001824:	fec42783          	lw	a5,-20(s0)
+80001828:	0007a783          	lw	a5,0(a5)
+8000182c:	0a078793          	addi	a5,a5,160
+80001830:	fe842703          	lw	a4,-24(s0)
+80001834:	01071713          	slli	a4,a4,0x10
+80001838:	01075713          	srli	a4,a4,0x10
+8000183c:	00070593          	mv	a1,a4
+80001840:	00078513          	mv	a0,a5
+80001844:	8b9ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80001848:	fec42783          	lw	a5,-20(s0)
+8000184c:	0007a783          	lw	a5,0(a5)
+80001850:	0a478713          	addi	a4,a5,164
+80001854:	fe842783          	lw	a5,-24(s0)
+80001858:	0107d793          	srli	a5,a5,0x10
+8000185c:	01079793          	slli	a5,a5,0x10
+80001860:	0107d793          	srli	a5,a5,0x10
+80001864:	00078593          	mv	a1,a5
+80001868:	00070513          	mv	a0,a4
+8000186c:	891ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:124
+            break;
+80001870:	09c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+80001874:	fec42783          	lw	a5,-20(s0)
+80001878:	0007a783          	lw	a5,0(a5)
+8000187c:	0a078793          	addi	a5,a5,160
+80001880:	fe842703          	lw	a4,-24(s0)
+80001884:	0ff77713          	andi	a4,a4,255
+80001888:	00070593          	mv	a1,a4
+8000188c:	00078513          	mv	a0,a5
+80001890:	8b5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+80001894:	fec42783          	lw	a5,-20(s0)
+80001898:	0007a783          	lw	a5,0(a5)
+8000189c:	0a478713          	addi	a4,a5,164
+800018a0:	fe842783          	lw	a5,-24(s0)
+800018a4:	0087d793          	srli	a5,a5,0x8
+800018a8:	0ff7f793          	andi	a5,a5,255
+800018ac:	00078593          	mv	a1,a5
+800018b0:	00070513          	mv	a0,a4
+800018b4:	891ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+800018b8:	fec42783          	lw	a5,-20(s0)
+800018bc:	0007a783          	lw	a5,0(a5)
+800018c0:	0a878713          	addi	a4,a5,168
+800018c4:	fe842783          	lw	a5,-24(s0)
+800018c8:	0107d793          	srli	a5,a5,0x10
+800018cc:	0ff7f793          	andi	a5,a5,255
+800018d0:	00078593          	mv	a1,a5
+800018d4:	00070513          	mv	a0,a4
+800018d8:	86dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+800018dc:	fec42783          	lw	a5,-20(s0)
+800018e0:	0007a783          	lw	a5,0(a5)
+800018e4:	0ac78713          	addi	a4,a5,172
+800018e8:	fe842783          	lw	a5,-24(s0)
+800018ec:	0187d793          	srli	a5,a5,0x18
+800018f0:	0ff7f793          	andi	a5,a5,255
+800018f4:	00078593          	mv	a1,a5
+800018f8:	00070513          	mv	a0,a4
+800018fc:	849ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:131
+            break;
+80001900:	00c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:134 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001904:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:135 (discriminator 1)
+            break;
+80001908:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145
+     * the expected value may indicate that some of the GPIOs may not exist due to
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+8000190c:	fec42503          	lw	a0,-20(s0)
+80001910:	028000ef          	jal	ra,80001938 <GPIO_get_outputs>
+80001914:	00050713          	mv	a4,a0
+80001918:	fe842783          	lw	a5,-24(s0)
+8000191c:	00e78463          	beq	a5,a4,80001924 <GPIO_set_outputs+0x150>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145 (discriminator 1)
+80001920:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001924:	00000013          	nop
+80001928:	01c12083          	lw	ra,28(sp)
+8000192c:	01812403          	lw	s0,24(sp)
+80001930:	02010113          	addi	sp,sp,32
+80001934:	00008067          	ret
+
+80001938 <GPIO_get_outputs>:
+GPIO_get_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:193
+ */
+uint32_t GPIO_get_outputs
+(
+    gpio_instance_t *   this_gpio
+)
+{
+80001938:	fd010113          	addi	sp,sp,-48
+8000193c:	02112623          	sw	ra,44(sp)
+80001940:	02812423          	sw	s0,40(sp)
+80001944:	03010413          	addi	s0,sp,48
+80001948:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:194
+    uint32_t gpio_out = 0;
+8000194c:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:196
+    
+    switch( this_gpio->apb_bus_width )
+80001950:	fdc42783          	lw	a5,-36(s0)
+80001954:	0047a783          	lw	a5,4(a5)
+80001958:	00100713          	li	a4,1
+8000195c:	02e78663          	beq	a5,a4,80001988 <GPIO_get_outputs+0x50>
+80001960:	08078063          	beqz	a5,800019e0 <GPIO_get_outputs+0xa8>
+80001964:	00200713          	li	a4,2
+80001968:	12e79463          	bne	a5,a4,80001a90 <GPIO_get_outputs+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:199
+    {
+        case GPIO_APB_32_BITS_BUS:
+            gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
+8000196c:	fdc42783          	lw	a5,-36(s0)
+80001970:	0007a783          	lw	a5,0(a5)
+80001974:	0a078793          	addi	a5,a5,160
+80001978:	00078513          	mv	a0,a5
+8000197c:	f40ff0ef          	jal	ra,800010bc <HW_get_32bit_reg>
+80001980:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:200
+            break;
+80001984:	1140006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:203
+            
+        case GPIO_APB_16_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+80001988:	fdc42783          	lw	a5,-36(s0)
+8000198c:	0007a783          	lw	a5,0(a5)
+80001990:	0a078793          	addi	a5,a5,160
+80001994:	00078513          	mv	a0,a5
+80001998:	f6cff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+8000199c:	00050793          	mv	a5,a0
+800019a0:	00078713          	mv	a4,a5
+800019a4:	fec42783          	lw	a5,-20(s0)
+800019a8:	00e7e7b3          	or	a5,a5,a4
+800019ac:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:204
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
+800019b0:	fdc42783          	lw	a5,-36(s0)
+800019b4:	0007a783          	lw	a5,0(a5)
+800019b8:	0a478793          	addi	a5,a5,164
+800019bc:	00078513          	mv	a0,a5
+800019c0:	f44ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019c4:	00050793          	mv	a5,a0
+800019c8:	01079793          	slli	a5,a5,0x10
+800019cc:	00078713          	mv	a4,a5
+800019d0:	fec42783          	lw	a5,-20(s0)
+800019d4:	00e7e7b3          	or	a5,a5,a4
+800019d8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:205
+            break;
+800019dc:	0bc0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:208
+            
+        case GPIO_APB_8_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+800019e0:	fdc42783          	lw	a5,-36(s0)
+800019e4:	0007a783          	lw	a5,0(a5)
+800019e8:	0a078793          	addi	a5,a5,160
+800019ec:	00078513          	mv	a0,a5
+800019f0:	f14ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019f4:	00050793          	mv	a5,a0
+800019f8:	00078713          	mv	a4,a5
+800019fc:	fec42783          	lw	a5,-20(s0)
+80001a00:	00e7e7b3          	or	a5,a5,a4
+80001a04:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:209
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
+80001a08:	fdc42783          	lw	a5,-36(s0)
+80001a0c:	0007a783          	lw	a5,0(a5)
+80001a10:	0a478793          	addi	a5,a5,164
+80001a14:	00078513          	mv	a0,a5
+80001a18:	eecff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a1c:	00050793          	mv	a5,a0
+80001a20:	00879793          	slli	a5,a5,0x8
+80001a24:	00078713          	mv	a4,a5
+80001a28:	fec42783          	lw	a5,-20(s0)
+80001a2c:	00e7e7b3          	or	a5,a5,a4
+80001a30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:210
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
+80001a34:	fdc42783          	lw	a5,-36(s0)
+80001a38:	0007a783          	lw	a5,0(a5)
+80001a3c:	0a878793          	addi	a5,a5,168
+80001a40:	00078513          	mv	a0,a5
+80001a44:	ec0ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a48:	00050793          	mv	a5,a0
+80001a4c:	01079793          	slli	a5,a5,0x10
+80001a50:	00078713          	mv	a4,a5
+80001a54:	fec42783          	lw	a5,-20(s0)
+80001a58:	00e7e7b3          	or	a5,a5,a4
+80001a5c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:211
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
+80001a60:	fdc42783          	lw	a5,-36(s0)
+80001a64:	0007a783          	lw	a5,0(a5)
+80001a68:	0ac78793          	addi	a5,a5,172
+80001a6c:	00078513          	mv	a0,a5
+80001a70:	e94ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a74:	00050793          	mv	a5,a0
+80001a78:	01879793          	slli	a5,a5,0x18
+80001a7c:	00078713          	mv	a4,a5
+80001a80:	fec42783          	lw	a5,-20(s0)
+80001a84:	00e7e7b3          	or	a5,a5,a4
+80001a88:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:212
+            break;
+80001a8c:	00c0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:215 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001a90:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:216 (discriminator 1)
+            break;
+80001a94:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:219
+    }
+    
+    return gpio_out;
+80001a98:	fec42783          	lw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:220
+}
+80001a9c:	00078513          	mv	a0,a5
+80001aa0:	02c12083          	lw	ra,44(sp)
+80001aa4:	02812403          	lw	s0,40(sp)
+80001aa8:	03010113          	addi	sp,sp,48
+80001aac:	00008067          	ret
+
+80001ab0 <MRV_enable_local_irq>:
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:586
+{
+80001ab0:	fd010113          	addi	sp,sp,-48
+80001ab4:	02812623          	sw	s0,44(sp)
+80001ab8:	03010413          	addi	s0,sp,48
+80001abc:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80001ac0:	fdc42783          	lw	a5,-36(s0)
+80001ac4:	3047a7f3          	csrrs	a5,mie,a5
+80001ac8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:588
+}
+80001acc:	00000013          	nop
+80001ad0:	02c12403          	lw	s0,44(sp)
+80001ad4:	03010113          	addi	sp,sp,48
+80001ad8:	00008067          	ret
+
+80001adc <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:48
+/*--------------------------------------------------------------------------------------------------
+ * Interrupt handler for the MIV_RV32 MSYS_EI interrupt connected to CoreTimer 0
+ */
+uint8_t
+MSYS_EI0_IRQHandler(void)
+{
+80001adc:	ff010113          	addi	sp,sp,-16
+80001ae0:	00112623          	sw	ra,12(sp)
+80001ae4:	00812423          	sw	s0,8(sp)
+80001ae8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:61
+     */
+
+    /* LEDs 1 - 4 are connected to GPIO pins 0 - 3.
+     * Invert the state of GPIO pins 0 - 3 every time the interrupt is triggered
+     */
+    gpio_pins_state = gpio_pins_state ^ (GPIO_0_MASK | GPIO_1_MASK | GPIO_2_MASK | GPIO_3_MASK);
+80001aec:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001af0:	0007a783          	lw	a5,0(a5)
+80001af4:	00f7c713          	xori	a4,a5,15
+80001af8:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001afc:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:63
+
+    GPIO_set_outputs(&g_gpio, gpio_pins_state);
+80001b00:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001b04:	0007a783          	lw	a5,0(a5)
+80001b08:	00078593          	mv	a1,a5
+80001b0c:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b10:	cc5ff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:66
+
+    /* Clear the interrupt within the timer */
+    TMR_clear_int(&g_core_timer_0);
+80001b14:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001b18:	af5ff0ef          	jal	ra,8000160c <TMR_clear_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:67
+    return (EXT_IRQ_KEEP_ENABLED);
+80001b1c:	00000793          	li	a5,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:68
+}
+80001b20:	00078513          	mv	a0,a5
+80001b24:	00c12083          	lw	ra,12(sp)
+80001b28:	00812403          	lw	s0,8(sp)
+80001b2c:	01010113          	addi	sp,sp,16
+80001b30:	00008067          	ret
+
+80001b34 <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:72
+
+int
+main(void)
+{
+80001b34:	ff010113          	addi	sp,sp,-16
+80001b38:	00112623          	sw	ra,12(sp)
+80001b3c:	00812423          	sw	s0,8(sp)
+80001b40:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:74
+    /* Initialise the UART and print the greeting message*/
+    UART_init(&g_core_uart_0, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, DATA_8_BITS | NO_PARITY);
+80001b44:	00100693          	li	a3,1
+80001b48:	01a00613          	li	a2,26
+80001b4c:	710005b7          	lui	a1,0x71000
+80001b50:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b54:	e38ff0ef          	jal	ra,8000118c <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:76
+
+    UART_polled_tx_string(&g_core_uart_0, g_message);
+80001b58:	00000597          	auipc	a1,0x0
+80001b5c:	0a858593          	addi	a1,a1,168 # 80001c00 <__data_load>
+80001b60:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b64:	801ff0ef          	jal	ra,80001364 <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:79
+
+    /* Enable local interrupt for the MSYS_EI interrupt pin */
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
+80001b68:	01000537          	lui	a0,0x1000
+80001b6c:	f45ff0ef          	jal	ra,80001ab0 <MRV_enable_local_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:82
+
+    /* Initialise the GPIO */
+    GPIO_init(&g_gpio, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+80001b70:	00200613          	li	a2,2
+80001b74:	750005b7          	lui	a1,0x75000
+80001b78:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b7c:	ae5ff0ef          	jal	ra,80001660 <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:85
+
+    /* Configure the GPIOs, turn them all off initially */
+    GPIO_set_outputs(&g_gpio, 0x00u);
+80001b80:	00000593          	li	a1,0
+80001b84:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b88:	c4dff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:88
+
+    /* Initialise and configure the timer */
+    TMR_init(&g_core_timer_0,
+80001b8c:	000147b7          	lui	a5,0x14
+80001b90:	c9a78713          	addi	a4,a5,-870 # 13c9a <RAM_SIZE+0xbc9a>
+80001b94:	00900693          	li	a3,9
+80001b98:	00000613          	li	a2,0
+80001b9c:	730005b7          	lui	a1,0x73000
+80001ba0:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001ba4:	889ff0ef          	jal	ra,8000142c <TMR_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:95
+             TMR_CONTINUOUS_MODE,
+             PRESCALER_DIV_1024,
+             TIMER_LOAD_VALUE);
+
+    /* Enable interrupts in general.*/
+    HAL_enable_interrupts();
+80001ba8:	ce4ff0ef          	jal	ra,8000108c <HAL_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:98
+
+    /* Enable the timer to generate interrupts */
+    TMR_enable_int(&g_core_timer_0);
+80001bac:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb0:	a01ff0ef          	jal	ra,800015b0 <TMR_enable_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:101
+
+    /* Start the timer */
+    TMR_start(&g_core_timer_0);
+80001bb4:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb8:	99dff0ef          	jal	ra,80001554 <TMR_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:103 (discriminator 1)
+
+    while (1u)
+80001bbc:	0000006f          	j	80001bbc <main+0x88>
+
+80001bc0 <local_irq_handler_table>:
+80001bc0:	80000f24 80000f08 80000f40 80001038     $.......@...8...
+80001bd0:	80000fe8 80000fe8 80000fe8 80000fe8     ................
+80001be0:	80001adc 80000f5c 80000f78 80000f94     ....\...x.......
+80001bf0:	80000fb0 80000fcc 80001000 8000101c     ................
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.hex
index 832f5fb..40f9a4d 100644
--- a/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.hex
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.hex
@@ -1,256 +1,525 @@
-:100000006F0000566F00C0080000000000000000F4
-:10001000C1A8000000000000000000000000000077
-:1000200021A200000000000000000000000000000D
-:1000300081A200000000000000000000000000009D
-:100040000000000095AA000065AA00000000000062
-:1000500000000000000000000000000095A9000062
-:1000600061AE0000D5A2000025A40000B5A40000E8
-:1000700045AC0000D5AC000025AE0000D1A60000C4
-:1000800021A1000013000000130000001300000075
-:10009000197106C006C00AC20EC412C616C81ACA12
-:1000A0001ECC22CE26D02AD22ED432D636D83ADA58
-:1000B0003EDC42DEC6C0CAC2CEC4D2C6D6C8DACA88
-:1000C000DECCE2CEE6D0EAD2EED4F2D6F6D8FADA38
-:1000D000FEDC73252034F3251034EF00E06F2DA9EA
-:1000E000197106C006C00AC20EC412C616C81ACAC2
-:1000F0001ECC22CE26D02AD22ED432D636D83ADA08
-:100100003EDC42DEC6C0CAC2CEC4D2C6D6C8DACA37
-:10011000DECCE2CEE6D0EAD2EED4F2D6F6D8FADAE7
-:10012000FEDCEF006068CDAE197106C006C00AC2E1
-:100130000EC412C616C81ACA1ECC22CE26D02AD287
-:100140002ED432D636D83ADA3EDC42DEC6C0CAC237
-:10015000CEC4D2C6D6C8DACADECCE2CEE6D0EAD267
-:10016000EED4F2D6F6D8FADAFEDCEF00C05A6DA66D
-:10017000197106C006C00AC20EC412C616C81ACA31
-:100180001ECC22CE26D02AD22ED432D636D83ADA77
-:100190003EDC42DEC6C0CAC2CEC4D2C6D6C8DACAA7
-:1001A000DECCE2CEE6D0EAD2EED4F2D6F6D8FADA57
-:1001B000FEDCEF0060678DA6197106C006C00AC29A
-:1001C0000EC412C616C81ACA1ECC22CE26D02AD2F7
-:1001D0002ED432D636D83ADA3EDC42DEC6C0CAC2A7
-:1001E000CEC4D2C6D6C8DACADECCE2CEE6D0EAD2D7
-:1001F000EED4F2D6F6D8FADAFEDCEF00206329AEB0
-:10020000197106C006C00AC20EC412C616C81ACAA0
-:100210001ECC22CE26D02AD22ED432D636D83ADAE6
-:100220003EDC42DEC6C0CAC2CEC4D2C6D6C8DACA16
-:10023000DECCE2CEE6D0EAD2EED4F2D6F6D8FADAC6
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-:100250000EC412C616C81ACA1ECC22CE26D02AD266
-:100260002ED432D636D83ADA3EDC42DEC6C0CAC216
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-:10028000EED4F2D6F6D8FADAFEDCEF00605A69A4B2
-:10029000197106C006C00AC20EC412C616C81ACA10
-:1002A0001ECC22CE26D02AD22ED432D636D83ADA56
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-:1002D000FEDCEF00005689A4197106C006C00AC2F0
-:1002E0000EC412C616C81ACA1ECC22CE26D02AD2D6
-:1002F0002ED432D636D83ADA3EDC42DEC6C0CAC286
-:10030000CEC4D2C6D6C8DACADECCE2CEE6D0EAD2B5
-:10031000EED4F2D6F6D8FADAFEDCEF00A051EDAA60
-:10032000197106C006C00AC20EC412C616C81ACA7F
-:100330001ECC22CE26D02AD22ED432D636D83ADAC5
-:100340003EDC42DEC6C0CAC2CEC4D2C6D6C8DACAF5
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-:10048000FEDCEF00C03B49A8197106C006C00AC2D5
-:100490000EC412C616C81ACA1ECC22CE26D02AD224
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-:1004D000197106C006C00AC20EC412C616C81ACACE
-:1004E0001ECC22CE26D02AD22ED432D636D83ADA14
-:1004F0003EDC42DEC6C0CAC2CEC4D2C6D6C8DACA44
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-:10056000735000307350403097000000938080A992
-:10057000B7C200029382C2FF23A00200F322103010
-:1005800093F2120063940202F322503093F232008D
-:100590000543639D6200F322503093F2C2FF1703BC
-:1005A0000000130363A66396620439A0970200005B
-:1005B000938282A573905230171700001307879B10
-:1005C00097470000938707A417480000130888A4E2
-:1005D0006308F7006386070197000000E7802008A2
-:1005E00097410000938101223120138101D06F00D7
-:1005F000E022029086829387018A138801906383A8
-:1006000007013528938701871388018A638A0701C8
-:100610003D20938701901388019063830701052093
-:100620001717000013070796938701811388018726
-:100630006305F700638307010D2096808280636F56
-:10064000F802B368F80093F838006349100323A058
-:1006500007009107E3CD07FF82806361F802B3686A
-:10066000F80093F83800634B10018328070023A09B
-:10067000170191071107E3CA07FF11A001A08280AB
-:10068000814693870187138781870146D4C354C36A
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.lst
new file mode 100644
index 0000000..758e7b6
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG1/hex/miv-rv32i-systick-blinky.lst
@@ -0,0 +1,5195 @@
+
+miv-rv32i-systick-blinky.elf:     file format elf32-littleriscv
+miv-rv32i-systick-blinky.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00002034 memsz 0x00002034 flags r-x
+    LOAD off    0x00004000 vaddr 0x80004000 paddr 0x80002040 align 2**12
+         filesz 0x00000070 memsz 0x000000a0 flags rw-
+    LOAD off    0x000040a0 vaddr 0x800040a0 paddr 0x800020b0 align 2**12
+         filesz 0x00000000 memsz 0x00000060 flags rw-
+    LOAD off    0x00004100 vaddr 0x80004100 paddr 0x800020b0 align 2**12
+         filesz 0x00000000 memsz 0x00000400 flags rw-
+
+Sections:
+Idx Name                       Size      VMA       LMA       File off  Algn  Flags
+  0 .entry                     00000560  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text                      00001ad0  80000560  80000560  00001560  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata2._global_impure_ptr 00000004  80002030  80002030  00003030  2**2  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .sdata                     00000010  80004000  80002040  00004000  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .data                      00000060  80004010  80002050  00004010  2**4  CONTENTS, ALLOC, LOAD, DATA
+  5 .sbss                      00000030  80004070  800020b0  00004070  2**4  ALLOC
+  6 .bss                       00000060  800040a0  800020b0  000040a0  2**4  ALLOC
+  7 .heap                      00000000  80004100  80004100  00004070  2**4  CONTENTS
+  8 .stack                     00000400  80004100  800020b0  00004100  2**4  ALLOC
+  9 .riscv.attributes          00000026  00000000  00000000  00004070  2**0  CONTENTS, READONLY
+ 10 .comment                   00000051  00000000  00000000  00004096  2**0  CONTENTS, READONLY
+ 11 .debug_line                000034f7  00000000  00000000  000040e7  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_info                00003c3c  00000000  00000000  000075de  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev              00001098  00000000  00000000  0000b21a  2**0  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges             000002b0  00000000  00000000  0000c2b8  2**3  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_str                 00001394  00000000  00000000  0000c568  2**0  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_ranges              00000310  00000000  00000000  0000d900  2**3  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_loc                 00001863  00000000  00000000  0000dc10  2**0  CONTENTS, READONLY, DEBUGGING
+ 18 .debug_frame               000010b8  00000000  00000000  0000f474  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+80000560 l    d  .text	00000000 .text
+80002030 l    d  .sdata2._global_impure_ptr	00000000 .sdata2._global_impure_ptr
+80004000 l    d  .sdata	00000000 .sdata
+80004010 l    d  .data	00000000 .data
+80004070 l    d  .sbss	00000000 .sbss
+800040a0 l    d  .bss	00000000 .bss
+80004100 l    d  .heap	00000000 .heap
+80004100 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_loc	00000000 .debug_loc
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+80000560 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+800000e0 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+80000128 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+80000170 l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800001b8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000200 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+800004d0 l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+800003f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+80000248 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+80000290 l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800002d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000320 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+80000368 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+800003b0 l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+80000440 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000488 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000518 l       .entry	00000000 generic_restore
+800005ac l       .text	00000000 ima_cores_setup
+800005f2 l       .text	00000000 vector_address_not_matching
+800005b8 l       .text	00000000 generic_reset_handling
+8000065a l       .text	00000000 block_copy
+800005f4 l       .text	00000000 initializations
+8000063e l       .text	00000000 zeroize_block
+8000067c l       .text	00000000 block_copy_error
+8000064e l       .text	00000000 zeroize_loop
+8000066a l       .text	00000000 block_copy_loop
+8000067e l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000680 l     F .text	0000002a MRV_read_mtime
+80004070 l     O .sbss	00000008 g_systick_cmp_value
+80004078 l     O .sbss	00000008 g_systick_increment
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+80000830 l     F .text	00000008 Software_IRQHandler.localalias.0
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+80004000 l     O .sdata	00000004 curbrk.2478
+00000000 l    df *ABS*	00000000 hal_irq.c
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80004084 l     O .sbss	00000004 interrupt_counter.2878
+80004088 l     O .sbss	00000004 val.2879
+00000000 l    df *ABS*	00000000 printf.c
+00000000 l    df *ABS*	00000000 sysisatty.c
+00000000 l    df *ABS*	00000000 writer.c
+00000000 l    df *ABS*	00000000 findfp.c
+80000cfc l     F .text	00000068 std
+00000000 l    df *ABS*	00000000 fwalk.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 nano-vfprintf.c
+80000ffa l     F .text	00000028 __sfputc_r
+00000000 l    df *ABS*	00000000 nano-vfprintf_i.c
+00000000 l    df *ABS*	00000000 sbrkr.c
+00000000 l    df *ABS*	00000000 stdio.c
+00000000 l    df *ABS*	00000000 wbuf.c
+00000000 l    df *ABS*	00000000 wsetup.c
+00000000 l    df *ABS*	00000000 closer.c
+00000000 l    df *ABS*	00000000 fflush.c
+00000000 l    df *ABS*	00000000 lseekr.c
+00000000 l    df *ABS*	00000000 makebuf.c
+00000000 l    df *ABS*	00000000 memchr.c
+00000000 l    df *ABS*	00000000 mlock.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 readr.c
+00000000 l    df *ABS*	00000000 fstatr.c
+00000000 l    df *ABS*	00000000 isattyr.c
+00000000 l    df *ABS*	00000000 impure.c
+80004010 l     O .data	00000060 impure_data
+00000000 l    df *ABS*	00000000 reent.c
+80001d82 g     F .text	0000002a _isatty_r
+80001b42 g     F .text	0000002e _lseek_r
+00000400 g       *ABS*	00000000 STACK_SIZE
+80000c8c g     F .text	00000042 printf
+80004800 g       .sdata	00000000 __global_pointer$
+800009d0 g     F .text	0000006e UART_get_rx
+80001758 g     F .text	00000036 __sseek
+80000db2 g     F .text	0000006a __sinit
+80001794 g     F .text	000000c2 __swbuf_r
+80000d6e g     F .text	00000044 __sfmoreglue
+80001c82 g     F .text	00000002 __malloc_unlock
+80002050 g       *ABS*	00000000 __data_load
+80000bc6 g     F .text	00000036 SysTick_Handler
+80004004 g     O .sdata	00000004 g_hello_msg
+8000095a g       .text	00000000 HW_get_8bit_reg_field
+80004070 g       .sbss	00000000 __sbss_start
+800040a0 g     O .bss	00000040 g_rx_buff
+800007cc g     F .text	0000001c handle_local_ei_interrupts
+80001d56 g     F .text	0000002c _fstat_r
+800040f0 g     O .bss	00000004 errno
+800008be g       .text	00000000 HW_set_32bit_reg
+800040e0 g     O .bss	00000008 g_gpio_out
+80000d64 g     F .text	0000000a _cleanup_r
+80004000 g       .sdata	00000000 __sdata_start
+80000848  w    F .text	00000002 MSYS_EI4_IRQHandler
+800040e8 g     O .bss	00000008 g_uart
+80000938 g       .text	00000000 HW_set_8bit_reg_field
+8000083e  w    F .text	00000002 SUBSYS_IRQHandler
+80000cce g     F .text	00000002 isatty
+8000088c g     F .text	0000001c _fstat
+800007e8 g     F .text	00000044 handle_trap
+8000084e  w    F .text	00000002 MSYS_EI6_IRQHandler
+800016ae g     F .text	0000002a _sbrk_r
+80000852  w    F .text	00000002 SUBSYSR_IRQHandler
+80001d28 g     F .text	0000002e _read_r
+800006aa g     F .text	0000009c MRV_systick_config
+8000083a  w    F .text	00000002 MGECI_IRQHandler
+80004100 g       .heap	00000000 _heap_end
+80001db0 g     O .text	00000040 local_irq_handler_table
+80000850  w    F .text	00000002 MSYS_EI7_IRQHandler
+80000882 g     F .text	00000006 _isatty
+80002030 g     O .sdata2._global_impure_ptr	00000004 _global_impure_ptr
+80004100 g       .bss	00000000 __bss_end
+80000856 g     F .text	0000002c _sbrk
+8000082c g     F .text	00000002 _init
+8000092c g       .text	00000000 HW_set_8bit_reg
+80000932 g       .text	00000000 HW_get_8bit_reg
+80000842  w    F .text	00000002 MSYS_EI1_IRQHandler
+800040a0 g       .sbss	00000000 __sbss_end
+800008c6 g       .text	00000000 HW_set_32bit_reg_field
+80004500 g       .stack	00000000 __stack_top
+80001f8c g     O .text	00000020 __sf_fake_stderr
+80000a3e g     F .text	00000038 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001022 g     F .text	00000042 __sfputs_r
+80001c66 g     F .text	0000001a memchr
+80001c84 g     F .text	000000a4 _free_r
+80000b26 g     F .text	00000096 GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+800008a8 g     F .text	00000008 _lseek
+80000746 g     F .text	00000072 handle_m_timer_interrupt
+80002040 g       *ABS*	00000000 __sdata_load
+80004070 g       .data	00000000 __data_end
+800008e8 g       .text	00000000 HW_get_32bit_reg_field
+80001968 g     F .text	0000002a _close_r
+80000a76 g     F .text	000000b0 GPIO_init
+80001856 g     F .text	00000112 __swsetup_r
+80000e1c g     F .text	0000009e __sfp
+800016d8 g     F .text	00000030 __sread
+80001c80 g     F .text	00000002 __malloc_lock
+80001adc g     F .text	00000066 _fflush_r
+80001fac g     O .text	00000020 __sf_fake_stdin
+800040a0 g       .bss	00000000 __bss_start
+800008b8 g     F .text	00000006 HAL_enable_interrupts
+80000c7c g     F .text	00000010 memset
+80000bfc g     F .text	00000080 main
+8000084a  w    F .text	00000002 MSYS_EI5_IRQHandler
+8000178e g     F .text	00000006 __sclose
+80000f26 g     F .text	000000d4 _malloc_r
+8000083c  w    F .text	00000002 MGEUI_IRQHandler
+800008f8 g       .text	00000000 HW_get_16bit_reg
+80004010 g       .sdata	00000000 __sdata_end
+80004100 g       .heap	00000000 __heap_end
+80004080 g     O .sbss	00000001 g_rx_size
+8000082e g     F .text	00000002 _fini
+80000c8c g     F .text	00000042 iprintf
+80000cd0 g     F .text	0000002c _write_r
+800008fe g       .text	00000000 HW_set_16bit_reg_field
+80000844  w    F .text	00000002 MSYS_EI2_IRQHandler
+80001300 g     F .text	0000010c _printf_common
+80004008 g     O .sdata	00000004 _impure_ptr
+80004100 g       .stack	00000000 __stack_bottom
+80001992 g     F .text	0000014a __sflush_r
+80000bbc g     F .text	0000000a Software_IRQHandler
+80004100 g       .heap	00000000 __heap_start
+80001b70 g     F .text	00000058 __swhatbuf_r
+800008b4 g     F .text	00000004 _write
+80004100 g       .bss	00000000 _end
+8000084c  w    F .text	00000002 Reserved_IRQHandler
+80001708 g     F .text	00000050 __swrite
+80001064 g     F .text	0000029c _vfiprintf_r
+80000eba g     F .text	0000006c _fwalk_reent
+80000966 g     F .text	0000006a UART_init
+80001fcc g     O .text	00000020 __sf_fake_stdout
+800008c2 g       .text	00000000 HW_get_32bit_reg
+800008b0 g     F .text	00000004 _read
+80000854 g     F .text	00000002 _exit
+800008f2 g       .text	00000000 HW_set_16bit_reg
+80001bc8 g     F .text	0000009e __smakebuf_r
+8000140c g     F .text	000002a2 _printf_i
+80000846  w    F .text	00000002 MSYS_EI3_IRQHandler
+80004090 g     O .sbss	00000004 __malloc_sbrk_start
+80000838  w    F .text	00000002 External_IRQHandler
+80004010 g       .data	00000000 __data_start
+8000408c g     O .sbss	00000004 __malloc_free_list
+80001064 g     F .text	0000029c _vfprintf_r
+800007b8 g     F .text	00000014 handle_m_soft_interrupt
+80000920 g       .text	00000000 HW_get_16bit_reg_field
+80000888 g     F .text	00000004 _close
+80000840  w    F .text	00000002 MSYS_EI0_IRQHandler
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:114
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	5600006f          	j	80000560 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:125
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:131
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	a8c1                	j	800000e0 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:140
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	a221                	j	80000128 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:149
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	a281                	j	80000170 <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:160
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	aa95                	j	800001b8 <vector_MGEUI_trap_handler>
+	...
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:166
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	aa65                	j	80000200 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:178
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	a995                	j	800004d0 <vector_SUBSYSR_IRQHandler>
+	...
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:185
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	ae61                	j	800003f8 <vector_SUBSYS_IRQHandler>
+	...
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:192
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	a2d5                	j	80000248 <vector_MSYS_EI0_trap_handler>
+	...
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:198
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	a425                	j	80000290 <vector_MSYS_EI1_trap_handler>
+	...
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:204
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	a4b5                	j	800002d8 <vector_MSYS_EI2_trap_handler>
+	...
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:210
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	ac45                	j	80000320 <vector_MSYS_EI3_trap_handler>
+	...
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:216
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	acd5                	j	80000368 <vector_MSYS_EI4_trap_handler>
+	...
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:222
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	ae25                	j	800003b0 <vector_MSYS_EI5_trap_handler>
+	...
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:229
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	a6d1                	j	80000440 <vector_MSYS_EI6_trap_handler>
+	...
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:239
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	a121                	j	80000488 <vector_MSYS_EI7_trap_handler>
+80000082:	0000                	unimp
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	7119                	addi	sp,sp,-128
+80000092:	c006                	sw	ra,0(sp)
+80000094:	c006                	sw	ra,0(sp)
+80000096:	c20a                	sw	sp,4(sp)
+80000098:	c40e                	sw	gp,8(sp)
+8000009a:	c612                	sw	tp,12(sp)
+8000009c:	c816                	sw	t0,16(sp)
+8000009e:	ca1a                	sw	t1,20(sp)
+800000a0:	cc1e                	sw	t2,24(sp)
+800000a2:	ce22                	sw	s0,28(sp)
+800000a4:	d026                	sw	s1,32(sp)
+800000a6:	d22a                	sw	a0,36(sp)
+800000a8:	d42e                	sw	a1,40(sp)
+800000aa:	d632                	sw	a2,44(sp)
+800000ac:	d836                	sw	a3,48(sp)
+800000ae:	da3a                	sw	a4,52(sp)
+800000b0:	dc3e                	sw	a5,56(sp)
+800000b2:	de42                	sw	a6,60(sp)
+800000b4:	c0c6                	sw	a7,64(sp)
+800000b6:	c2ca                	sw	s2,68(sp)
+800000b8:	c4ce                	sw	s3,72(sp)
+800000ba:	c6d2                	sw	s4,76(sp)
+800000bc:	c8d6                	sw	s5,80(sp)
+800000be:	cada                	sw	s6,84(sp)
+800000c0:	ccde                	sw	s7,88(sp)
+800000c2:	cee2                	sw	s8,92(sp)
+800000c4:	d0e6                	sw	s9,96(sp)
+800000c6:	d2ea                	sw	s10,100(sp)
+800000c8:	d4ee                	sw	s11,104(sp)
+800000ca:	d6f2                	sw	t3,108(sp)
+800000cc:	d8f6                	sw	t4,112(sp)
+800000ce:	dafa                	sw	t5,116(sp)
+800000d0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a0, mcause
+800000d2:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  csrr a1, mepc
+800000d6:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  jal handle_trap
+800000da:	70e000ef          	jal	ra,800007e8 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:252
+  j generic_restore
+800000de:	a92d                	j	80000518 <generic_restore>
+
+800000e0 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+800000e0:	7119                	addi	sp,sp,-128
+800000e2:	c006                	sw	ra,0(sp)
+800000e4:	c006                	sw	ra,0(sp)
+800000e6:	c20a                	sw	sp,4(sp)
+800000e8:	c40e                	sw	gp,8(sp)
+800000ea:	c612                	sw	tp,12(sp)
+800000ec:	c816                	sw	t0,16(sp)
+800000ee:	ca1a                	sw	t1,20(sp)
+800000f0:	cc1e                	sw	t2,24(sp)
+800000f2:	ce22                	sw	s0,28(sp)
+800000f4:	d026                	sw	s1,32(sp)
+800000f6:	d22a                	sw	a0,36(sp)
+800000f8:	d42e                	sw	a1,40(sp)
+800000fa:	d632                	sw	a2,44(sp)
+800000fc:	d836                	sw	a3,48(sp)
+800000fe:	da3a                	sw	a4,52(sp)
+80000100:	dc3e                	sw	a5,56(sp)
+80000102:	de42                	sw	a6,60(sp)
+80000104:	c0c6                	sw	a7,64(sp)
+80000106:	c2ca                	sw	s2,68(sp)
+80000108:	c4ce                	sw	s3,72(sp)
+8000010a:	c6d2                	sw	s4,76(sp)
+8000010c:	c8d6                	sw	s5,80(sp)
+8000010e:	cada                	sw	s6,84(sp)
+80000110:	ccde                	sw	s7,88(sp)
+80000112:	cee2                	sw	s8,92(sp)
+80000114:	d0e6                	sw	s9,96(sp)
+80000116:	d2ea                	sw	s10,100(sp)
+80000118:	d4ee                	sw	s11,104(sp)
+8000011a:	d6f2                	sw	t3,108(sp)
+8000011c:	d8f6                	sw	t4,112(sp)
+8000011e:	dafa                	sw	t5,116(sp)
+80000120:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  jal handle_m_soft_interrupt
+80000122:	696000ef          	jal	ra,800007b8 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:257
+  j generic_restore
+80000126:	aecd                	j	80000518 <generic_restore>
+
+80000128 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+80000128:	7119                	addi	sp,sp,-128
+8000012a:	c006                	sw	ra,0(sp)
+8000012c:	c006                	sw	ra,0(sp)
+8000012e:	c20a                	sw	sp,4(sp)
+80000130:	c40e                	sw	gp,8(sp)
+80000132:	c612                	sw	tp,12(sp)
+80000134:	c816                	sw	t0,16(sp)
+80000136:	ca1a                	sw	t1,20(sp)
+80000138:	cc1e                	sw	t2,24(sp)
+8000013a:	ce22                	sw	s0,28(sp)
+8000013c:	d026                	sw	s1,32(sp)
+8000013e:	d22a                	sw	a0,36(sp)
+80000140:	d42e                	sw	a1,40(sp)
+80000142:	d632                	sw	a2,44(sp)
+80000144:	d836                	sw	a3,48(sp)
+80000146:	da3a                	sw	a4,52(sp)
+80000148:	dc3e                	sw	a5,56(sp)
+8000014a:	de42                	sw	a6,60(sp)
+8000014c:	c0c6                	sw	a7,64(sp)
+8000014e:	c2ca                	sw	s2,68(sp)
+80000150:	c4ce                	sw	s3,72(sp)
+80000152:	c6d2                	sw	s4,76(sp)
+80000154:	c8d6                	sw	s5,80(sp)
+80000156:	cada                	sw	s6,84(sp)
+80000158:	ccde                	sw	s7,88(sp)
+8000015a:	cee2                	sw	s8,92(sp)
+8000015c:	d0e6                	sw	s9,96(sp)
+8000015e:	d2ea                	sw	s10,100(sp)
+80000160:	d4ee                	sw	s11,104(sp)
+80000162:	d6f2                	sw	t3,108(sp)
+80000164:	d8f6                	sw	t4,112(sp)
+80000166:	dafa                	sw	t5,116(sp)
+80000168:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  jal handle_m_timer_interrupt
+8000016a:	5dc000ef          	jal	ra,80000746 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:262
+  j generic_restore
+8000016e:	a66d                	j	80000518 <generic_restore>
+
+80000170 <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:265
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+80000170:	7119                	addi	sp,sp,-128
+80000172:	c006                	sw	ra,0(sp)
+80000174:	c006                	sw	ra,0(sp)
+80000176:	c20a                	sw	sp,4(sp)
+80000178:	c40e                	sw	gp,8(sp)
+8000017a:	c612                	sw	tp,12(sp)
+8000017c:	c816                	sw	t0,16(sp)
+8000017e:	ca1a                	sw	t1,20(sp)
+80000180:	cc1e                	sw	t2,24(sp)
+80000182:	ce22                	sw	s0,28(sp)
+80000184:	d026                	sw	s1,32(sp)
+80000186:	d22a                	sw	a0,36(sp)
+80000188:	d42e                	sw	a1,40(sp)
+8000018a:	d632                	sw	a2,44(sp)
+8000018c:	d836                	sw	a3,48(sp)
+8000018e:	da3a                	sw	a4,52(sp)
+80000190:	dc3e                	sw	a5,56(sp)
+80000192:	de42                	sw	a6,60(sp)
+80000194:	c0c6                	sw	a7,64(sp)
+80000196:	c2ca                	sw	s2,68(sp)
+80000198:	c4ce                	sw	s3,72(sp)
+8000019a:	c6d2                	sw	s4,76(sp)
+8000019c:	c8d6                	sw	s5,80(sp)
+8000019e:	cada                	sw	s6,84(sp)
+800001a0:	ccde                	sw	s7,88(sp)
+800001a2:	cee2                	sw	s8,92(sp)
+800001a4:	d0e6                	sw	s9,96(sp)
+800001a6:	d2ea                	sw	s10,100(sp)
+800001a8:	d4ee                	sw	s11,104(sp)
+800001aa:	d6f2                	sw	t3,108(sp)
+800001ac:	d8f6                	sw	t4,112(sp)
+800001ae:	dafa                	sw	t5,116(sp)
+800001b0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:269
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800001b2:	686000ef          	jal	ra,80000838 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:271
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800001b6:	a68d                	j	80000518 <generic_restore>
+
+800001b8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800001b8:	7119                	addi	sp,sp,-128
+800001ba:	c006                	sw	ra,0(sp)
+800001bc:	c006                	sw	ra,0(sp)
+800001be:	c20a                	sw	sp,4(sp)
+800001c0:	c40e                	sw	gp,8(sp)
+800001c2:	c612                	sw	tp,12(sp)
+800001c4:	c816                	sw	t0,16(sp)
+800001c6:	ca1a                	sw	t1,20(sp)
+800001c8:	cc1e                	sw	t2,24(sp)
+800001ca:	ce22                	sw	s0,28(sp)
+800001cc:	d026                	sw	s1,32(sp)
+800001ce:	d22a                	sw	a0,36(sp)
+800001d0:	d42e                	sw	a1,40(sp)
+800001d2:	d632                	sw	a2,44(sp)
+800001d4:	d836                	sw	a3,48(sp)
+800001d6:	da3a                	sw	a4,52(sp)
+800001d8:	dc3e                	sw	a5,56(sp)
+800001da:	de42                	sw	a6,60(sp)
+800001dc:	c0c6                	sw	a7,64(sp)
+800001de:	c2ca                	sw	s2,68(sp)
+800001e0:	c4ce                	sw	s3,72(sp)
+800001e2:	c6d2                	sw	s4,76(sp)
+800001e4:	c8d6                	sw	s5,80(sp)
+800001e6:	cada                	sw	s6,84(sp)
+800001e8:	ccde                	sw	s7,88(sp)
+800001ea:	cee2                	sw	s8,92(sp)
+800001ec:	d0e6                	sw	s9,96(sp)
+800001ee:	d2ea                	sw	s10,100(sp)
+800001f0:	d4ee                	sw	s11,104(sp)
+800001f2:	d6f2                	sw	t3,108(sp)
+800001f4:	d8f6                	sw	t4,112(sp)
+800001f6:	dafa                	sw	t5,116(sp)
+800001f8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  jal MGEUI_IRQHandler
+800001fa:	642000ef          	jal	ra,8000083c <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:277
+  j generic_restore
+800001fe:	ae29                	j	80000518 <generic_restore>
+
+80000200 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000200:	7119                	addi	sp,sp,-128
+80000202:	c006                	sw	ra,0(sp)
+80000204:	c006                	sw	ra,0(sp)
+80000206:	c20a                	sw	sp,4(sp)
+80000208:	c40e                	sw	gp,8(sp)
+8000020a:	c612                	sw	tp,12(sp)
+8000020c:	c816                	sw	t0,16(sp)
+8000020e:	ca1a                	sw	t1,20(sp)
+80000210:	cc1e                	sw	t2,24(sp)
+80000212:	ce22                	sw	s0,28(sp)
+80000214:	d026                	sw	s1,32(sp)
+80000216:	d22a                	sw	a0,36(sp)
+80000218:	d42e                	sw	a1,40(sp)
+8000021a:	d632                	sw	a2,44(sp)
+8000021c:	d836                	sw	a3,48(sp)
+8000021e:	da3a                	sw	a4,52(sp)
+80000220:	dc3e                	sw	a5,56(sp)
+80000222:	de42                	sw	a6,60(sp)
+80000224:	c0c6                	sw	a7,64(sp)
+80000226:	c2ca                	sw	s2,68(sp)
+80000228:	c4ce                	sw	s3,72(sp)
+8000022a:	c6d2                	sw	s4,76(sp)
+8000022c:	c8d6                	sw	s5,80(sp)
+8000022e:	cada                	sw	s6,84(sp)
+80000230:	ccde                	sw	s7,88(sp)
+80000232:	cee2                	sw	s8,92(sp)
+80000234:	d0e6                	sw	s9,96(sp)
+80000236:	d2ea                	sw	s10,100(sp)
+80000238:	d4ee                	sw	s11,104(sp)
+8000023a:	d6f2                	sw	t3,108(sp)
+8000023c:	d8f6                	sw	t4,112(sp)
+8000023e:	dafa                	sw	t5,116(sp)
+80000240:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  jal MGECI_IRQHandler
+80000242:	5f8000ef          	jal	ra,8000083a <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:282
+  j generic_restore
+80000246:	acc9                	j	80000518 <generic_restore>
+
+80000248 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+80000248:	7119                	addi	sp,sp,-128
+8000024a:	c006                	sw	ra,0(sp)
+8000024c:	c006                	sw	ra,0(sp)
+8000024e:	c20a                	sw	sp,4(sp)
+80000250:	c40e                	sw	gp,8(sp)
+80000252:	c612                	sw	tp,12(sp)
+80000254:	c816                	sw	t0,16(sp)
+80000256:	ca1a                	sw	t1,20(sp)
+80000258:	cc1e                	sw	t2,24(sp)
+8000025a:	ce22                	sw	s0,28(sp)
+8000025c:	d026                	sw	s1,32(sp)
+8000025e:	d22a                	sw	a0,36(sp)
+80000260:	d42e                	sw	a1,40(sp)
+80000262:	d632                	sw	a2,44(sp)
+80000264:	d836                	sw	a3,48(sp)
+80000266:	da3a                	sw	a4,52(sp)
+80000268:	dc3e                	sw	a5,56(sp)
+8000026a:	de42                	sw	a6,60(sp)
+8000026c:	c0c6                	sw	a7,64(sp)
+8000026e:	c2ca                	sw	s2,68(sp)
+80000270:	c4ce                	sw	s3,72(sp)
+80000272:	c6d2                	sw	s4,76(sp)
+80000274:	c8d6                	sw	s5,80(sp)
+80000276:	cada                	sw	s6,84(sp)
+80000278:	ccde                	sw	s7,88(sp)
+8000027a:	cee2                	sw	s8,92(sp)
+8000027c:	d0e6                	sw	s9,96(sp)
+8000027e:	d2ea                	sw	s10,100(sp)
+80000280:	d4ee                	sw	s11,104(sp)
+80000282:	d6f2                	sw	t3,108(sp)
+80000284:	d8f6                	sw	t4,112(sp)
+80000286:	dafa                	sw	t5,116(sp)
+80000288:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  jal MSYS_EI0_IRQHandler
+8000028a:	5b6000ef          	jal	ra,80000840 <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:287
+  j generic_restore
+8000028e:	a469                	j	80000518 <generic_restore>
+
+80000290 <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+80000290:	7119                	addi	sp,sp,-128
+80000292:	c006                	sw	ra,0(sp)
+80000294:	c006                	sw	ra,0(sp)
+80000296:	c20a                	sw	sp,4(sp)
+80000298:	c40e                	sw	gp,8(sp)
+8000029a:	c612                	sw	tp,12(sp)
+8000029c:	c816                	sw	t0,16(sp)
+8000029e:	ca1a                	sw	t1,20(sp)
+800002a0:	cc1e                	sw	t2,24(sp)
+800002a2:	ce22                	sw	s0,28(sp)
+800002a4:	d026                	sw	s1,32(sp)
+800002a6:	d22a                	sw	a0,36(sp)
+800002a8:	d42e                	sw	a1,40(sp)
+800002aa:	d632                	sw	a2,44(sp)
+800002ac:	d836                	sw	a3,48(sp)
+800002ae:	da3a                	sw	a4,52(sp)
+800002b0:	dc3e                	sw	a5,56(sp)
+800002b2:	de42                	sw	a6,60(sp)
+800002b4:	c0c6                	sw	a7,64(sp)
+800002b6:	c2ca                	sw	s2,68(sp)
+800002b8:	c4ce                	sw	s3,72(sp)
+800002ba:	c6d2                	sw	s4,76(sp)
+800002bc:	c8d6                	sw	s5,80(sp)
+800002be:	cada                	sw	s6,84(sp)
+800002c0:	ccde                	sw	s7,88(sp)
+800002c2:	cee2                	sw	s8,92(sp)
+800002c4:	d0e6                	sw	s9,96(sp)
+800002c6:	d2ea                	sw	s10,100(sp)
+800002c8:	d4ee                	sw	s11,104(sp)
+800002ca:	d6f2                	sw	t3,108(sp)
+800002cc:	d8f6                	sw	t4,112(sp)
+800002ce:	dafa                	sw	t5,116(sp)
+800002d0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  jal MSYS_EI1_IRQHandler
+800002d2:	570000ef          	jal	ra,80000842 <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:292
+  j generic_restore
+800002d6:	a489                	j	80000518 <generic_restore>
+
+800002d8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800002d8:	7119                	addi	sp,sp,-128
+800002da:	c006                	sw	ra,0(sp)
+800002dc:	c006                	sw	ra,0(sp)
+800002de:	c20a                	sw	sp,4(sp)
+800002e0:	c40e                	sw	gp,8(sp)
+800002e2:	c612                	sw	tp,12(sp)
+800002e4:	c816                	sw	t0,16(sp)
+800002e6:	ca1a                	sw	t1,20(sp)
+800002e8:	cc1e                	sw	t2,24(sp)
+800002ea:	ce22                	sw	s0,28(sp)
+800002ec:	d026                	sw	s1,32(sp)
+800002ee:	d22a                	sw	a0,36(sp)
+800002f0:	d42e                	sw	a1,40(sp)
+800002f2:	d632                	sw	a2,44(sp)
+800002f4:	d836                	sw	a3,48(sp)
+800002f6:	da3a                	sw	a4,52(sp)
+800002f8:	dc3e                	sw	a5,56(sp)
+800002fa:	de42                	sw	a6,60(sp)
+800002fc:	c0c6                	sw	a7,64(sp)
+800002fe:	c2ca                	sw	s2,68(sp)
+80000300:	c4ce                	sw	s3,72(sp)
+80000302:	c6d2                	sw	s4,76(sp)
+80000304:	c8d6                	sw	s5,80(sp)
+80000306:	cada                	sw	s6,84(sp)
+80000308:	ccde                	sw	s7,88(sp)
+8000030a:	cee2                	sw	s8,92(sp)
+8000030c:	d0e6                	sw	s9,96(sp)
+8000030e:	d2ea                	sw	s10,100(sp)
+80000310:	d4ee                	sw	s11,104(sp)
+80000312:	d6f2                	sw	t3,108(sp)
+80000314:	d8f6                	sw	t4,112(sp)
+80000316:	dafa                	sw	t5,116(sp)
+80000318:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  jal MSYS_EI2_IRQHandler
+8000031a:	52a000ef          	jal	ra,80000844 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:297
+  j generic_restore
+8000031e:	aaed                	j	80000518 <generic_restore>
+
+80000320 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000320:	7119                	addi	sp,sp,-128
+80000322:	c006                	sw	ra,0(sp)
+80000324:	c006                	sw	ra,0(sp)
+80000326:	c20a                	sw	sp,4(sp)
+80000328:	c40e                	sw	gp,8(sp)
+8000032a:	c612                	sw	tp,12(sp)
+8000032c:	c816                	sw	t0,16(sp)
+8000032e:	ca1a                	sw	t1,20(sp)
+80000330:	cc1e                	sw	t2,24(sp)
+80000332:	ce22                	sw	s0,28(sp)
+80000334:	d026                	sw	s1,32(sp)
+80000336:	d22a                	sw	a0,36(sp)
+80000338:	d42e                	sw	a1,40(sp)
+8000033a:	d632                	sw	a2,44(sp)
+8000033c:	d836                	sw	a3,48(sp)
+8000033e:	da3a                	sw	a4,52(sp)
+80000340:	dc3e                	sw	a5,56(sp)
+80000342:	de42                	sw	a6,60(sp)
+80000344:	c0c6                	sw	a7,64(sp)
+80000346:	c2ca                	sw	s2,68(sp)
+80000348:	c4ce                	sw	s3,72(sp)
+8000034a:	c6d2                	sw	s4,76(sp)
+8000034c:	c8d6                	sw	s5,80(sp)
+8000034e:	cada                	sw	s6,84(sp)
+80000350:	ccde                	sw	s7,88(sp)
+80000352:	cee2                	sw	s8,92(sp)
+80000354:	d0e6                	sw	s9,96(sp)
+80000356:	d2ea                	sw	s10,100(sp)
+80000358:	d4ee                	sw	s11,104(sp)
+8000035a:	d6f2                	sw	t3,108(sp)
+8000035c:	d8f6                	sw	t4,112(sp)
+8000035e:	dafa                	sw	t5,116(sp)
+80000360:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  jal MSYS_EI3_IRQHandler
+80000362:	4e4000ef          	jal	ra,80000846 <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:302
+  j generic_restore
+80000366:	aa4d                	j	80000518 <generic_restore>
+
+80000368 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+80000368:	7119                	addi	sp,sp,-128
+8000036a:	c006                	sw	ra,0(sp)
+8000036c:	c006                	sw	ra,0(sp)
+8000036e:	c20a                	sw	sp,4(sp)
+80000370:	c40e                	sw	gp,8(sp)
+80000372:	c612                	sw	tp,12(sp)
+80000374:	c816                	sw	t0,16(sp)
+80000376:	ca1a                	sw	t1,20(sp)
+80000378:	cc1e                	sw	t2,24(sp)
+8000037a:	ce22                	sw	s0,28(sp)
+8000037c:	d026                	sw	s1,32(sp)
+8000037e:	d22a                	sw	a0,36(sp)
+80000380:	d42e                	sw	a1,40(sp)
+80000382:	d632                	sw	a2,44(sp)
+80000384:	d836                	sw	a3,48(sp)
+80000386:	da3a                	sw	a4,52(sp)
+80000388:	dc3e                	sw	a5,56(sp)
+8000038a:	de42                	sw	a6,60(sp)
+8000038c:	c0c6                	sw	a7,64(sp)
+8000038e:	c2ca                	sw	s2,68(sp)
+80000390:	c4ce                	sw	s3,72(sp)
+80000392:	c6d2                	sw	s4,76(sp)
+80000394:	c8d6                	sw	s5,80(sp)
+80000396:	cada                	sw	s6,84(sp)
+80000398:	ccde                	sw	s7,88(sp)
+8000039a:	cee2                	sw	s8,92(sp)
+8000039c:	d0e6                	sw	s9,96(sp)
+8000039e:	d2ea                	sw	s10,100(sp)
+800003a0:	d4ee                	sw	s11,104(sp)
+800003a2:	d6f2                	sw	t3,108(sp)
+800003a4:	d8f6                	sw	t4,112(sp)
+800003a6:	dafa                	sw	t5,116(sp)
+800003a8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  jal MSYS_EI4_IRQHandler
+800003aa:	49e000ef          	jal	ra,80000848 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:307
+  j generic_restore
+800003ae:	a2ad                	j	80000518 <generic_restore>
+
+800003b0 <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+800003b0:	7119                	addi	sp,sp,-128
+800003b2:	c006                	sw	ra,0(sp)
+800003b4:	c006                	sw	ra,0(sp)
+800003b6:	c20a                	sw	sp,4(sp)
+800003b8:	c40e                	sw	gp,8(sp)
+800003ba:	c612                	sw	tp,12(sp)
+800003bc:	c816                	sw	t0,16(sp)
+800003be:	ca1a                	sw	t1,20(sp)
+800003c0:	cc1e                	sw	t2,24(sp)
+800003c2:	ce22                	sw	s0,28(sp)
+800003c4:	d026                	sw	s1,32(sp)
+800003c6:	d22a                	sw	a0,36(sp)
+800003c8:	d42e                	sw	a1,40(sp)
+800003ca:	d632                	sw	a2,44(sp)
+800003cc:	d836                	sw	a3,48(sp)
+800003ce:	da3a                	sw	a4,52(sp)
+800003d0:	dc3e                	sw	a5,56(sp)
+800003d2:	de42                	sw	a6,60(sp)
+800003d4:	c0c6                	sw	a7,64(sp)
+800003d6:	c2ca                	sw	s2,68(sp)
+800003d8:	c4ce                	sw	s3,72(sp)
+800003da:	c6d2                	sw	s4,76(sp)
+800003dc:	c8d6                	sw	s5,80(sp)
+800003de:	cada                	sw	s6,84(sp)
+800003e0:	ccde                	sw	s7,88(sp)
+800003e2:	cee2                	sw	s8,92(sp)
+800003e4:	d0e6                	sw	s9,96(sp)
+800003e6:	d2ea                	sw	s10,100(sp)
+800003e8:	d4ee                	sw	s11,104(sp)
+800003ea:	d6f2                	sw	t3,108(sp)
+800003ec:	d8f6                	sw	t4,112(sp)
+800003ee:	dafa                	sw	t5,116(sp)
+800003f0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  jal MSYS_EI5_IRQHandler
+800003f2:	458000ef          	jal	ra,8000084a <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:312
+  j generic_restore
+800003f6:	a20d                	j	80000518 <generic_restore>
+
+800003f8 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+800003f8:	7119                	addi	sp,sp,-128
+800003fa:	c006                	sw	ra,0(sp)
+800003fc:	c006                	sw	ra,0(sp)
+800003fe:	c20a                	sw	sp,4(sp)
+80000400:	c40e                	sw	gp,8(sp)
+80000402:	c612                	sw	tp,12(sp)
+80000404:	c816                	sw	t0,16(sp)
+80000406:	ca1a                	sw	t1,20(sp)
+80000408:	cc1e                	sw	t2,24(sp)
+8000040a:	ce22                	sw	s0,28(sp)
+8000040c:	d026                	sw	s1,32(sp)
+8000040e:	d22a                	sw	a0,36(sp)
+80000410:	d42e                	sw	a1,40(sp)
+80000412:	d632                	sw	a2,44(sp)
+80000414:	d836                	sw	a3,48(sp)
+80000416:	da3a                	sw	a4,52(sp)
+80000418:	dc3e                	sw	a5,56(sp)
+8000041a:	de42                	sw	a6,60(sp)
+8000041c:	c0c6                	sw	a7,64(sp)
+8000041e:	c2ca                	sw	s2,68(sp)
+80000420:	c4ce                	sw	s3,72(sp)
+80000422:	c6d2                	sw	s4,76(sp)
+80000424:	c8d6                	sw	s5,80(sp)
+80000426:	cada                	sw	s6,84(sp)
+80000428:	ccde                	sw	s7,88(sp)
+8000042a:	cee2                	sw	s8,92(sp)
+8000042c:	d0e6                	sw	s9,96(sp)
+8000042e:	d2ea                	sw	s10,100(sp)
+80000430:	d4ee                	sw	s11,104(sp)
+80000432:	d6f2                	sw	t3,108(sp)
+80000434:	d8f6                	sw	t4,112(sp)
+80000436:	dafa                	sw	t5,116(sp)
+80000438:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  jal SUBSYS_IRQHandler
+8000043a:	404000ef          	jal	ra,8000083e <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:317
+  j generic_restore
+8000043e:	a8e9                	j	80000518 <generic_restore>
+
+80000440 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+80000440:	7119                	addi	sp,sp,-128
+80000442:	c006                	sw	ra,0(sp)
+80000444:	c006                	sw	ra,0(sp)
+80000446:	c20a                	sw	sp,4(sp)
+80000448:	c40e                	sw	gp,8(sp)
+8000044a:	c612                	sw	tp,12(sp)
+8000044c:	c816                	sw	t0,16(sp)
+8000044e:	ca1a                	sw	t1,20(sp)
+80000450:	cc1e                	sw	t2,24(sp)
+80000452:	ce22                	sw	s0,28(sp)
+80000454:	d026                	sw	s1,32(sp)
+80000456:	d22a                	sw	a0,36(sp)
+80000458:	d42e                	sw	a1,40(sp)
+8000045a:	d632                	sw	a2,44(sp)
+8000045c:	d836                	sw	a3,48(sp)
+8000045e:	da3a                	sw	a4,52(sp)
+80000460:	dc3e                	sw	a5,56(sp)
+80000462:	de42                	sw	a6,60(sp)
+80000464:	c0c6                	sw	a7,64(sp)
+80000466:	c2ca                	sw	s2,68(sp)
+80000468:	c4ce                	sw	s3,72(sp)
+8000046a:	c6d2                	sw	s4,76(sp)
+8000046c:	c8d6                	sw	s5,80(sp)
+8000046e:	cada                	sw	s6,84(sp)
+80000470:	ccde                	sw	s7,88(sp)
+80000472:	cee2                	sw	s8,92(sp)
+80000474:	d0e6                	sw	s9,96(sp)
+80000476:	d2ea                	sw	s10,100(sp)
+80000478:	d4ee                	sw	s11,104(sp)
+8000047a:	d6f2                	sw	t3,108(sp)
+8000047c:	d8f6                	sw	t4,112(sp)
+8000047e:	dafa                	sw	t5,116(sp)
+80000480:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  jal MSYS_EI6_IRQHandler
+80000482:	3cc000ef          	jal	ra,8000084e <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:323
+  j generic_restore
+80000486:	a849                	j	80000518 <generic_restore>
+
+80000488 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000488:	7119                	addi	sp,sp,-128
+8000048a:	c006                	sw	ra,0(sp)
+8000048c:	c006                	sw	ra,0(sp)
+8000048e:	c20a                	sw	sp,4(sp)
+80000490:	c40e                	sw	gp,8(sp)
+80000492:	c612                	sw	tp,12(sp)
+80000494:	c816                	sw	t0,16(sp)
+80000496:	ca1a                	sw	t1,20(sp)
+80000498:	cc1e                	sw	t2,24(sp)
+8000049a:	ce22                	sw	s0,28(sp)
+8000049c:	d026                	sw	s1,32(sp)
+8000049e:	d22a                	sw	a0,36(sp)
+800004a0:	d42e                	sw	a1,40(sp)
+800004a2:	d632                	sw	a2,44(sp)
+800004a4:	d836                	sw	a3,48(sp)
+800004a6:	da3a                	sw	a4,52(sp)
+800004a8:	dc3e                	sw	a5,56(sp)
+800004aa:	de42                	sw	a6,60(sp)
+800004ac:	c0c6                	sw	a7,64(sp)
+800004ae:	c2ca                	sw	s2,68(sp)
+800004b0:	c4ce                	sw	s3,72(sp)
+800004b2:	c6d2                	sw	s4,76(sp)
+800004b4:	c8d6                	sw	s5,80(sp)
+800004b6:	cada                	sw	s6,84(sp)
+800004b8:	ccde                	sw	s7,88(sp)
+800004ba:	cee2                	sw	s8,92(sp)
+800004bc:	d0e6                	sw	s9,96(sp)
+800004be:	d2ea                	sw	s10,100(sp)
+800004c0:	d4ee                	sw	s11,104(sp)
+800004c2:	d6f2                	sw	t3,108(sp)
+800004c4:	d8f6                	sw	t4,112(sp)
+800004c6:	dafa                	sw	t5,116(sp)
+800004c8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  jal MSYS_EI7_IRQHandler
+800004ca:	386000ef          	jal	ra,80000850 <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:328
+  j generic_restore
+800004ce:	a0a9                	j	80000518 <generic_restore>
+
+800004d0 <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+800004d0:	7119                	addi	sp,sp,-128
+800004d2:	c006                	sw	ra,0(sp)
+800004d4:	c006                	sw	ra,0(sp)
+800004d6:	c20a                	sw	sp,4(sp)
+800004d8:	c40e                	sw	gp,8(sp)
+800004da:	c612                	sw	tp,12(sp)
+800004dc:	c816                	sw	t0,16(sp)
+800004de:	ca1a                	sw	t1,20(sp)
+800004e0:	cc1e                	sw	t2,24(sp)
+800004e2:	ce22                	sw	s0,28(sp)
+800004e4:	d026                	sw	s1,32(sp)
+800004e6:	d22a                	sw	a0,36(sp)
+800004e8:	d42e                	sw	a1,40(sp)
+800004ea:	d632                	sw	a2,44(sp)
+800004ec:	d836                	sw	a3,48(sp)
+800004ee:	da3a                	sw	a4,52(sp)
+800004f0:	dc3e                	sw	a5,56(sp)
+800004f2:	de42                	sw	a6,60(sp)
+800004f4:	c0c6                	sw	a7,64(sp)
+800004f6:	c2ca                	sw	s2,68(sp)
+800004f8:	c4ce                	sw	s3,72(sp)
+800004fa:	c6d2                	sw	s4,76(sp)
+800004fc:	c8d6                	sw	s5,80(sp)
+800004fe:	cada                	sw	s6,84(sp)
+80000500:	ccde                	sw	s7,88(sp)
+80000502:	cee2                	sw	s8,92(sp)
+80000504:	d0e6                	sw	s9,96(sp)
+80000506:	d2ea                	sw	s10,100(sp)
+80000508:	d4ee                	sw	s11,104(sp)
+8000050a:	d6f2                	sw	t3,108(sp)
+8000050c:	d8f6                	sw	t4,112(sp)
+8000050e:	dafa                	sw	t5,116(sp)
+80000510:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  jal SUBSYSR_IRQHandler
+80000512:	340000ef          	jal	ra,80000852 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:334
+  j generic_restore
+80000516:	a009                	j	80000518 <generic_restore>
+
+80000518 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000518:	4082                	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x2, 1 * REGBYTES(sp)
+8000051a:	4112                	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x3, 2 * REGBYTES(sp)
+8000051c:	41a2                	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x4, 3 * REGBYTES(sp)
+8000051e:	4232                	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x5, 4 * REGBYTES(sp)
+80000520:	42c2                	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x6, 5 * REGBYTES(sp)
+80000522:	4352                	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x7, 6 * REGBYTES(sp)
+80000524:	43e2                	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x8, 7 * REGBYTES(sp)
+80000526:	4472                	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x9, 8 * REGBYTES(sp)
+80000528:	5482                	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x10, 9 * REGBYTES(sp)
+8000052a:	5512                	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x11, 10 * REGBYTES(sp)
+8000052c:	55a2                	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x12, 11 * REGBYTES(sp)
+8000052e:	5632                	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x13, 12 * REGBYTES(sp)
+80000530:	56c2                	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x14, 13 * REGBYTES(sp)
+80000532:	5752                	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x15, 14 * REGBYTES(sp)
+80000534:	57e2                	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x16, 15 * REGBYTES(sp)
+80000536:	5872                	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x17, 16 * REGBYTES(sp)
+80000538:	4886                	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x18, 17 * REGBYTES(sp)
+8000053a:	4916                	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x19, 18 * REGBYTES(sp)
+8000053c:	49a6                	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x20, 19 * REGBYTES(sp)
+8000053e:	4a36                	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x21, 20 * REGBYTES(sp)
+80000540:	4ac6                	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x22, 21 * REGBYTES(sp)
+80000542:	4b56                	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x23, 22 * REGBYTES(sp)
+80000544:	4be6                	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x24, 23 * REGBYTES(sp)
+80000546:	4c76                	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x25, 24 * REGBYTES(sp)
+80000548:	5c86                	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x26, 25 * REGBYTES(sp)
+8000054a:	5d16                	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x27, 26 * REGBYTES(sp)
+8000054c:	5da6                	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x28, 27 * REGBYTES(sp)
+8000054e:	5e36                	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x29, 28 * REGBYTES(sp)
+80000550:	5ec6                	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x30, 29 * REGBYTES(sp)
+80000552:	5f56                	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:370
+  LREG x31, 30 * REGBYTES(sp)
+80000554:	5fe6                	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+80000556:	6109                	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:410
+  mret
+80000558:	30200073          	mret
+8000055c:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+80000560 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+80000560:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  csrwi mie, 0
+80000564:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:421
+  la ra, _start
+80000568:	00000097          	auipc	ra,0x0
+8000056c:	a9808093          	addi	ra,ra,-1384 # 80000000 <_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+80000570:	0200c2b7          	lui	t0,0x200c
+80000574:	ffc28293          	addi	t0,t0,-4 # 200bffc <STACK_SIZE+0x200bbfc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:426
+  sw x0, 0(t0)
+80000578:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+#endif
+
+  csrr t0, misa
+8000057c:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  andi t0, t0, A_EXTENSION_MASK
+80000580:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:431
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+80000584:	02029463          	bnez	t0,800005ac <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+80000588:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+8000058c:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  li t1, MTVEC_VECTORED_MODE_VAL
+80000590:	4305                	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:442
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+80000592:	00629d63          	bne	t0,t1,800005ac <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+80000596:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  andi t0, t0, 0xFFFFFFFC
+8000059a:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  la t1, trap_entry
+8000059e:	00000317          	auipc	t1,0x0
+800005a2:	a6630313          	addi	t1,t1,-1434 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  bne t0, t1, vector_address_not_matching
+800005a6:	04629663          	bne	t0,t1,800005f2 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:450
+  j generic_reset_handling
+800005aa:	a039                	j	800005b8 <generic_reset_handling>
+
+800005ac <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:477
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+800005ac:	00000297          	auipc	t0,0x0
+800005b0:	a5828293          	addi	t0,t0,-1448 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:483
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+800005b4:	30529073          	csrw	mtvec,t0
+
+800005b8 <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+800005b8:	00002717          	auipc	a4,0x2
+800005bc:	a8870713          	addi	a4,a4,-1400 # 80002040 <__sdata_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a5, __sdata_start
+800005c0:	00004797          	auipc	a5,0x4
+800005c4:	a4078793          	addi	a5,a5,-1472 # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    la a6, __sdata_end
+800005c8:	00004817          	auipc	a6,0x4
+800005cc:	a4880813          	addi	a6,a6,-1464 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+800005d0:	00f70863          	beq	a4,a5,800005e0 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+800005d4:	01078663          	beq	a5,a6,800005e0 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:493
+    call block_copy
+800005d8:	00000097          	auipc	ra,0x0
+800005dc:	082080e7          	jalr	130(ra) # 8000065a <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:497
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+800005e0:	00004197          	auipc	gp,0x4
+800005e4:	22018193          	addi	gp,gp,544 # 80004800 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:514
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+800005e8:	2031                	jal	800005f4 <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:516
+  /* Initialize stack pointer */
+  la sp, __stack_top
+800005ea:	d0018113          	addi	sp,gp,-768 # 80004500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:519
+
+  /* Jump into C code */
+  j _init
+800005ee:	23e0006f          	j	8000082c <_init>
+
+800005f2 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:524
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+800005f2:	9002                	ebreak
+
+800005f4 <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+800005f4:	8286                	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a5, __bss_start
+800005f6:	8a018793          	addi	a5,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    la  a6, __bss_end
+800005fa:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    beq a5, a6, 1f     /* Section start and end address are the same */
+800005fe:	01078363          	beq	a5,a6,80000604 <initializations+0x10>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:532
+    call zeroize_block
+80000602:	2835                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000604:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    la  a6, __sbss_end
+80000608:	8a018813          	addi	a6,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    beq a5, a6, 1f     /* Section start and end address are the same */
+8000060c:	01078a63          	beq	a5,a6,80000620 <initializations+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:539
+    call zeroize_block
+80000610:	203d                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+
+/* Clear heap */
+    la  a5, __heap_start
+80000612:	90018793          	addi	a5,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    la  a6, __heap_end
+80000616:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    beq a5, a6, 1f     /* Section start and end address are the same */
+8000061a:	01078363          	beq	a5,a6,80000620 <initializations+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:545
+    call zeroize_block
+8000061e:	2005                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000620:	00002717          	auipc	a4,0x2
+80000624:	a3070713          	addi	a4,a4,-1488 # 80002050 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a5, __data_start
+80000628:	81018793          	addi	a5,gp,-2032 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    la  a6, __data_end
+8000062c:	87018813          	addi	a6,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000630:	00f70563          	beq	a4,a5,8000063a <initializations+0x46>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000634:	01078363          	beq	a5,a6,8000063a <initializations+0x46>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:554
+    call block_copy
+80000638:	200d                	jal	8000065a <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+
+1:
+    mv ra, t0           /* Retrieve ra */
+8000063a:	8096                	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:558
+    ret
+8000063c:	8082                	ret
+
+8000063e <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+8000063e:	02f86f63          	bltu	a6,a5,8000067c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000642:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    andi a7, a7, 0x03u
+80000646:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:564
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+8000064a:	03104963          	bgtz	a7,8000067c <block_copy_error>
+
+8000064e <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+zeroize_loop:
+    sw x0, 0(a5)
+8000064e:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    add a5, a5, __SIZEOF_POINTER__
+80000652:	0791                	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    blt a5, a6, zeroize_loop
+80000654:	ff07cde3          	blt	a5,a6,8000064e <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:569
+    ret
+80000658:	8082                	ret
+
+8000065a <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+8000065a:	02f86163          	bltu	a6,a5,8000067c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    or a7, a6, a5                   /* Check if start or end is unalined */
+8000065e:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    andi a7, a7, 0x03u
+80000662:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:575
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000666:	01104b63          	bgtz	a7,8000067c <block_copy_error>
+
+8000066a <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+block_copy_loop:
+    lw a7, 0(a4)
+8000066a:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    sw a7, 0(a5)
+8000066e:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a5, a5, 0x04
+80000672:	0791                	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    addi a4, a4, 0x04
+80000674:	0711                	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    blt a5, a6, block_copy_loop
+80000676:	ff07cae3          	blt	a5,a6,8000066a <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:582
+    j block_copy_exit
+8000067a:	a011                	j	8000067e <block_copy_exit>
+
+8000067c <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:585
+
+block_copy_error:
+    j block_copy_error
+8000067c:	a001                	j	8000067c <block_copy_error>
+
+8000067e <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:588
+
+block_copy_exit:
+    ret
+8000067e:	8082                	ret
+
+80000680 <MRV_read_mtime>:
+MRV_read_mtime():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:684
+
+/***************************************************************************//**
+  The MRV_read_mtime() function returns the current MTIME register value.
+ */
+static inline uint64_t MRV_read_mtime(void)
+{
+80000680:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:685
+    volatile uint32_t hi = 0u;
+80000682:	c402                	sw	zero,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:686
+    volatile uint32_t lo = 0u;
+80000684:	c602                	sw	zero,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691
+
+    /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
+     * returned value could be wrong. */
+    do {
+        hi = MTIMEH;
+80000686:	0200c7b7          	lui	a5,0x200c
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691 (discriminator 1)
+8000068a:	ffc7a683          	lw	a3,-4(a5) # 200bffc <STACK_SIZE+0x200bbfc>
+8000068e:	c436                	sw	a3,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:692 (discriminator 1)
+        lo = MTIME;
+80000690:	ff87a683          	lw	a3,-8(a5)
+80000694:	c636                	sw	a3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:693 (discriminator 1)
+    } while(hi != MTIMEH);
+80000696:	ffc7a603          	lw	a2,-4(a5)
+8000069a:	46a2                	lw	a3,8(sp)
+8000069c:	fed617e3          	bne	a2,a3,8000068a <MRV_read_mtime+0xa>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:695
+
+    return((((uint64_t)MTIMEH) << 32u) | lo);
+800006a0:	ffc7a583          	lw	a1,-4(a5)
+800006a4:	4532                	lw	a0,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:696
+}
+800006a6:	0141                	addi	sp,sp,16
+800006a8:	8082                	ret
+
+800006aa <MRV_systick_config>:
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+
+/*------------------------------------------------------------------------------
+ * Configure the machine timer to generate an interrupt.
+ */
+uint32_t MRV_systick_config(uint64_t ticks)
+{
+800006aa:	1141                	addi	sp,sp,-16
+800006ac:	c422                	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    uint32_t ret_val = ERROR;
+    uint64_t remainder = ticks;
+    g_systick_increment = 0U;
+800006ae:	4701                	li	a4,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006b0:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+{
+800006b4:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006b6:	87818413          	addi	s0,gp,-1928 # 80004078 <g_systick_increment>
+800006ba:	4681                	li	a3,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006bc:	c3d8                	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006be:	c058                	sw	a4,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006c0:	c394                	sw	a3,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006c2:	c014                	sw	a3,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:169
+
+    while (remainder >= MTIME_PRESCALER)
+800006c4:	4781                	li	a5,0
+800006c6:	4701                	li	a4,0
+800006c8:	4601                	li	a2,0
+800006ca:	02005837          	lui	a6,0x2005
+800006ce:	00178893          	addi	a7,a5,1
+800006d2:	00082303          	lw	t1,0(a6) # 2005000 <STACK_SIZE+0x2004c00>
+800006d6:	00f8b6b3          	sltu	a3,a7,a5
+800006da:	96ba                	add	a3,a3,a4
+800006dc:	e9a9                	bnez	a1,8000072e <MRV_systick_config+0x84>
+800006de:	04657863          	bgeu	a0,t1,8000072e <MRV_systick_config+0x84>
+800006e2:	c609                	beqz	a2,800006ec <MRV_systick_config+0x42>
+800006e4:	86f1ac23          	sw	a5,-1928(gp) # 80004078 <g_systick_increment>
+800006e8:	86e1ae23          	sw	a4,-1924(gp) # 8000407c <g_systick_increment+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:175
+    {
+        remainder -= MTIME_PRESCALER;
+        g_systick_increment++;
+    }
+
+    g_systick_cmp_value = g_systick_increment + MRV_read_mtime();
+800006ec:	3f51                	jal	80000680 <MRV_read_mtime>
+800006ee:	401c                	lw	a5,0(s0)
+800006f0:	4054                	lw	a3,4(s0)
+800006f2:	00f50733          	add	a4,a0,a5
+800006f6:	00a73533          	sltu	a0,a4,a0
+800006fa:	95b6                	add	a1,a1,a3
+800006fc:	95aa                	add	a1,a1,a0
+800006fe:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000702:	86b1aa23          	sw	a1,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+
+    if (g_systick_increment > 0U)
+80000706:	8fd5                	or	a5,a5,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:164
+    uint32_t ret_val = ERROR;
+80000708:	4505                	li	a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+    if (g_systick_increment > 0U)
+8000070a:	cf91                	beqz	a5,80000726 <MRV_systick_config+0x7c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:179
+    {
+        WRITE_MTIMECMP(g_systick_cmp_value);
+8000070c:	020047b7          	lui	a5,0x2004
+80000710:	56fd                	li	a3,-1
+80000712:	c3d4                	sw	a3,4(a5)
+80000714:	c398                	sw	a4,0(a5)
+80000716:	c3cc                	sw	a1,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:180
+        set_csr(mie, MIP_MTIP);
+80000718:	08000793          	li	a5,128
+8000071c:	3047a7f3          	csrrs	a5,mie,a5
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80000720:	300467f3          	csrrsi	a5,mstatus,8
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:182
+        MRV_enable_interrupts();
+        ret_val = SUCCESS;
+80000724:	4501                	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:186
+    }
+
+    return ret_val;
+}
+80000726:	40b2                	lw	ra,12(sp)
+80000728:	4422                	lw	s0,8(sp)
+8000072a:	0141                	addi	sp,sp,16
+8000072c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:171
+        remainder -= MTIME_PRESCALER;
+8000072e:	00082783          	lw	a5,0(a6)
+80000732:	4605                	li	a2,1
+80000734:	40f507b3          	sub	a5,a0,a5
+80000738:	00f53733          	sltu	a4,a0,a5
+8000073c:	8d99                	sub	a1,a1,a4
+8000073e:	853e                	mv	a0,a5
+80000740:	8736                	mv	a4,a3
+80000742:	87c6                	mv	a5,a7
+80000744:	b769                	j	800006ce <MRV_systick_config+0x24>
+
+80000746 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000746:	1141                	addi	sp,sp,-16
+80000748:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+8000074a:	08000793          	li	a5,128
+8000074e:	3047b7f3          	csrrc	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MRV_read_mtime();
+80000752:	373d                	jal	80000680 <MRV_read_mtime>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000754:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+80000758:	4398                	lw	a4,0(a5)
+8000075a:	00550613          	addi	a2,a0,5
+8000075e:	43dc                	lw	a5,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000760:	87818693          	addi	a3,gp,-1928 # 80004078 <g_systick_increment>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000764:	00a63533          	sltu	a0,a2,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000768:	0006a803          	lw	a6,0(a3)
+8000076c:	0046a883          	lw	a7,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000770:	95aa                	add	a1,a1,a0
+80000772:	4681                	li	a3,0
+80000774:	02b7e963          	bltu	a5,a1,800007a6 <handle_m_timer_interrupt+0x60>
+80000778:	00f59463          	bne	a1,a5,80000780 <handle_m_timer_interrupt+0x3a>
+8000077c:	02c76563          	bltu	a4,a2,800007a6 <handle_m_timer_interrupt+0x60>
+80000780:	c689                	beqz	a3,8000078a <handle_m_timer_interrupt+0x44>
+80000782:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000786:	86f1aa23          	sw	a5,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+8000078a:	020046b7          	lui	a3,0x2004
+8000078e:	567d                	li	a2,-1
+80000790:	c2d0                	sw	a2,4(a3)
+80000792:	c298                	sw	a4,0(a3)
+80000794:	c2dc                	sw	a5,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000796:	2905                	jal	80000bc6 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000798:	08000793          	li	a5,128
+8000079c:	3047a7f3          	csrrs	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+800007a0:	40b2                	lw	ra,12(sp)
+800007a2:	0141                	addi	sp,sp,16
+800007a4:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+800007a6:	010706b3          	add	a3,a4,a6
+800007aa:	00e6b533          	sltu	a0,a3,a4
+800007ae:	97c6                	add	a5,a5,a7
+800007b0:	8736                	mv	a4,a3
+800007b2:	97aa                	add	a5,a5,a0
+800007b4:	4685                	li	a3,1
+800007b6:	bf7d                	j	80000774 <handle_m_timer_interrupt+0x2e>
+
+800007b8 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+800007b8:	1141                	addi	sp,sp,-16
+800007ba:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+800007bc:	2101                	jal	80000bbc <Software_IRQHandler>
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+800007be:	6719                	lui	a4,0x6
+800007c0:	531c                	lw	a5,32(a4)
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+    MRV_clear_soft_irq();
+}
+800007c2:	40b2                	lw	ra,12(sp)
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+800007c4:	9bf5                	andi	a5,a5,-3
+800007c6:	d31c                	sw	a5,32(a4)
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+800007c8:	0141                	addi	sp,sp,16
+800007ca:	8082                	ret
+
+800007cc <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+    uint64_t mhart_id = read_csr(mhartid);
+800007cc:	f14027f3          	csrr	a5,mhartid
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+800007d0:	1541                	addi	a0,a0,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+800007d2:	0ff57513          	andi	a0,a0,255
+800007d6:	050a                	slli	a0,a0,0x2
+800007d8:	00001797          	auipc	a5,0x1
+800007dc:	5d878793          	addi	a5,a5,1496 # 80001db0 <local_irq_handler_table>
+800007e0:	953e                	add	a0,a0,a5
+800007e2:	00052303          	lw	t1,0(a0)
+800007e6:	8302                	jr	t1
+
+800007e8 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+
+    if (is_interrupt)
+800007e8:	02055d63          	bgez	a0,80000822 <handle_trap+0x3a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+800007ec:	800007b7          	lui	a5,0x80000
+800007f0:	ff07c713          	xori	a4,a5,-16
+800007f4:	8f69                	and	a4,a4,a0
+800007f6:	cb01                	beqz	a4,80000806 <handle_trap+0x1e>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+800007f8:	fe07c793          	xori	a5,a5,-32
+800007fc:	8fe9                	and	a5,a5,a0
+800007fe:	e781                	bnez	a5,80000806 <handle_trap+0x1e>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000800:	0ff57513          	andi	a0,a0,255
+80000804:	b7e1                	j	800007cc <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000806:	0506                	slli	a0,a0,0x1
+80000808:	8105                	srli	a0,a0,0x1
+8000080a:	47ad                	li	a5,11
+8000080c:	00f51363          	bne	a0,a5,80000812 <handle_trap+0x2a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+#else
+        if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+#endif
+        {
+#ifndef MIV_LEGACY_RV32
+            External_IRQHandler();
+80000810:	a025                	j	80000838 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+#else
+            handle_m_ext_interrupt();
+#endif
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000812:	478d                	li	a5,3
+80000814:	00f51363          	bne	a0,a5,8000081a <handle_trap+0x32>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+        {
+            handle_m_soft_interrupt();
+80000818:	b745                	j	800007b8 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+8000081a:	479d                	li	a5,7
+8000081c:	00f51763          	bne	a0,a5,8000082a <handle_trap+0x42>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+        {
+            handle_m_timer_interrupt();
+80000820:	b71d                	j	80000746 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000822:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+         uintptr_t mmepc  = read_csr(mepc);
+
+        /* breakpoint */
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+80000824:	0505                	addi	a0,a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000826:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+        _exit(1 + mcause);
+80000828:	2035                	jal	80000854 <_exit>
+8000082a:	8082                	ret
+
+8000082c <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+8000082c:	aec1                	j	80000bfc <main>
+
+8000082e <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+}
+8000082e:	8082                	ret
+
+80000830 <Software_IRQHandler.localalias.0>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000830:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000832:	4529                	li	a0,10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+{
+80000834:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000836:	2839                	jal	80000854 <_exit>
+
+80000838 <External_IRQHandler>:
+External_IRQHandler():
+80000838:	8082                	ret
+
+8000083a <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+8000083a:	8082                	ret
+
+8000083c <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+8000083c:	8082                	ret
+
+8000083e <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+8000083e:	8082                	ret
+
+80000840 <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+80000840:	8082                	ret
+
+80000842 <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+80000842:	8082                	ret
+
+80000844 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+80000844:	8082                	ret
+
+80000846 <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+80000846:	8082                	ret
+
+80000848 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+80000848:	8082                	ret
+
+8000084a <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+8000084a:	8082                	ret
+
+8000084c <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+8000084c:	b7d5                	j	80000830 <Software_IRQHandler.localalias.0>
+
+8000084e <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+8000084e:	8082                	ret
+
+80000850 <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+80000850:	8082                	ret
+
+80000852 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+80000852:	8082                	ret
+
+80000854 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80000854:	a001                	j	80000854 <_exit>
+
+80000856 <_sbrk>:
+_sbrk():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169
+     * You need to set HEAP_SIZE to a non-zero value in your linker script if
+     * the following assertion fires.
+     */
+    ASSERT(&__heap_end > &__heap_start);
+
+    if (((curbrk + incr) < &_end) || ((curbrk + incr) > &_heap_end))
+80000856:	00003797          	auipc	a5,0x3
+8000085a:	7aa78793          	addi	a5,a5,1962 # 80004000 <__sdata_start>
+8000085e:	439c                	lw	a5,0(a5)
+80000860:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+80000864:	953e                	add	a0,a0,a5
+80000866:	00e56c63          	bltu	a0,a4,8000087e <_sbrk+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169 (discriminator 1)
+8000086a:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+8000086e:	00a76863          	bltu	a4,a0,8000087e <_sbrk+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:176
+        errno = ENOMEM;
+        ret = ((char *) - 1);
+    }
+    else
+    {
+        curbrk += incr;
+80000872:	00003717          	auipc	a4,0x3
+80000876:	78a72723          	sw	a0,1934(a4) # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:188
+     * assertion fires.
+     * */
+    ASSERT(curbrk <= &__heap_end);
+
+    return(ret);
+}
+8000087a:	853e                	mv	a0,a5
+8000087c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:172
+        ret = ((char *) - 1);
+8000087e:	57fd                	li	a5,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:187
+    return(ret);
+80000880:	bfed                	j	8000087a <_sbrk+0x24>
+
+80000882 <_isatty>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:205
+        errno = EBADF;
+        ret = 0;
+    }
+
+    return(ret);
+}
+80000882:	00352513          	slti	a0,a0,3
+80000886:	8082                	ret
+
+80000888 <_close>:
+_close():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:226
+}
+
+int _close(int fd)
+{
+    return stub(EBADF);
+}
+80000888:	557d                	li	a0,-1
+8000088a:	8082                	ret
+
+8000088c <_fstat>:
+_fstat():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:239
+{
+    return stub(EAGAIN);
+}
+
+int _fstat(int fd, struct stat *st)
+{
+8000088c:	1101                	addi	sp,sp,-32
+8000088e:	ce06                	sw	ra,28(sp)
+80000890:	c62e                	sw	a1,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:242
+    int ret = 0;
+
+    if (isatty(fd))
+80000892:	2935                	jal	80000cce <isatty>
+80000894:	c901                	beqz	a0,800008a4 <_fstat+0x18>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+    {
+        st->st_mode = S_IFCHR;
+80000896:	45b2                	lw	a1,12(sp)
+80000898:	6789                	lui	a5,0x2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:245
+        ret = 0;
+8000089a:	4501                	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+        st->st_mode = S_IFCHR;
+8000089c:	c1dc                	sw	a5,4(a1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:253
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+8000089e:	40f2                	lw	ra,28(sp)
+800008a0:	6105                	addi	sp,sp,32
+800008a2:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:249
+        ret = stub(EBADF);
+800008a4:	557d                	li	a0,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:252
+    return ret;
+800008a6:	bfe5                	j	8000089e <_fstat+0x12>
+
+800008a8 <_lseek>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:194
+    if (fd <= 2)    /* one of stdin, stdout, stderr */
+800008a8:	00352513          	slti	a0,a0,3
+_lseek():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:283
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+800008ac:	157d                	addi	a0,a0,-1
+800008ae:	8082                	ret
+
+800008b0 <_read>:
+_read():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:313
+        return  count;          /* Filled the buffer */
+    }
+#endif
+
+    return stub(EBADF);
+}
+800008b0:	557d                	li	a0,-1
+800008b2:	8082                	ret
+
+800008b4 <_write>:
+_write():
+800008b4:	557d                	li	a0,-1
+800008b6:	8082                	ret
+
+800008b8 <HAL_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+    set_csr(mstatus, MSTATUS_MIE);
+800008b8:	300467f3          	csrrsi	a5,mstatus,8
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hal_irq.c:24
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+    MRV_enable_interrupts();
+}
+800008bc:	8082                	ret
+
+800008be <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+800008be:	c10c                	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:40
+    ret
+800008c0:	8082                	ret
+
+800008c2 <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+800008c2:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:52
+    ret
+800008c4:	8082                	ret
+
+800008c6 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+800008c6:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+800008c8:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+800008cc:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+800008d0:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+800008d4:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+800008d6:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+800008da:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+800008de:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+800008e2:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:73
+    ret
+800008e6:	8082                	ret
+
+800008e8 <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+800008e8:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+800008ea:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+800008ec:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:90
+    ret
+800008f0:	8082                	ret
+
+800008f2 <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+800008f2:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:101
+    ret
+800008f6:	8082                	ret
+
+800008f8 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+800008f8:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:113
+    ret
+800008fc:	8082                	ret
+
+800008fe <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+800008fe:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80000900:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80000904:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80000908:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+8000090c:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+8000090e:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80000912:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80000916:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+8000091a:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:135
+    ret
+8000091e:	8082                	ret
+
+80000920 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80000920:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80000924:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+80000926:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:152
+    ret
+8000092a:	8082                	ret
+
+8000092c <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+8000092c:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:163
+    ret
+80000930:	8082                	ret
+
+80000932 <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+80000932:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:175
+    ret
+80000936:	8082                	ret
+
+80000938 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80000938:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+8000093a:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+8000093e:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80000942:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80000946:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80000948:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+8000094c:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80000950:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80000954:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:196
+    ret
+80000958:	8082                	ret
+
+8000095a <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+8000095a:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+8000095e:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80000960:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:213
+    ret
+80000964:	8082                	ret
+
+80000966 <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+80000966:	c525                	beqz	a0,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+80000968:	479d                	li	a5,7
+8000096a:	06d7e263          	bltu	a5,a3,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+8000096e:	6789                	lui	a5,0x2
+80000970:	04f67f63          	bgeu	a2,a5,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+80000974:	1101                	addi	sp,sp,-32
+80000976:	cc22                	sw	s0,24(sp)
+80000978:	c84a                	sw	s2,16(sp)
+8000097a:	8432                	mv	s0,a2
+8000097c:	892e                	mv	s2,a1
+8000097e:	ca26                	sw	s1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000980:	0ff67593          	andi	a1,a2,255
+80000984:	84aa                	mv	s1,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000986:	8415                	srai	s0,s0,0x5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000988:	00890513          	addi	a0,s2,8
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+8000098c:	ce06                	sw	ra,28(sp)
+8000098e:	c64e                	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000990:	7f847413          	andi	s0,s0,2040
+80000994:	89b6                	mv	s3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000996:	3f59                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000998:	00c90513          	addi	a0,s2,12
+8000099c:	013465b3          	or	a1,s0,s3
+800009a0:	3771                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009a2:	01090513          	addi	a0,s2,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+        this_uart->base_address = base_addr;
+800009a6:	0124a023          	sw	s2,0(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009aa:	3761                	jal	80000932 <HW_get_8bit_reg>
+800009ac:	8909                	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+800009ae:	e911                	bnez	a0,800009c2 <UART_init+0x5c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+800009b0:	00048223          	sb	zero,4(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+800009b4:	40f2                	lw	ra,28(sp)
+800009b6:	4462                	lw	s0,24(sp)
+800009b8:	44d2                	lw	s1,20(sp)
+800009ba:	4942                	lw	s2,16(sp)
+800009bc:	49b2                	lw	s3,12(sp)
+800009be:	6105                	addi	sp,sp,32
+800009c0:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+800009c2:	4088                	lw	a0,0(s1)
+800009c4:	0511                	addi	a0,a0,4
+800009c6:	37b5                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009c8:	4088                	lw	a0,0(s1)
+800009ca:	0541                	addi	a0,a0,16
+800009cc:	bff9                	j	800009aa <UART_init+0x44>
+800009ce:	8082                	ret
+
+800009d0 <UART_get_rx>:
+UART_get_rx():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:199
+(
+    UART_instance_t * this_uart,
+    uint8_t * rx_buffer,
+    size_t buff_size
+)
+{
+800009d0:	1101                	addi	sp,sp,-32
+800009d2:	ce06                	sw	ra,28(sp)
+800009d4:	cc22                	sw	s0,24(sp)
+800009d6:	ca26                	sw	s1,20(sp)
+800009d8:	c84a                	sw	s2,16(sp)
+800009da:	c64e                	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( rx_buffer != NULL_BUFFER )
+    HAL_ASSERT( buff_size > 0 )
+      
+    if( (this_uart != NULL_INSTANCE) &&
+800009dc:	cd29                	beqz	a0,80000a36 <UART_get_rx+0x66>
+800009de:	89ae                	mv	s3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208 (discriminator 1)
+800009e0:	c9b9                	beqz	a1,80000a36 <UART_get_rx+0x66>
+800009e2:	84b2                	mv	s1,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:209
+        (rx_buffer != NULL_BUFFER)   &&
+800009e4:	ce19                	beqz	a2,80000a02 <UART_get_rx+0x32>
+800009e6:	842a                	mv	s0,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        (buff_size > 0u) )
+    {
+        rx_idx = 0u;
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800009e8:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:212
+        rx_idx = 0u;
+800009ea:	4901                	li	s2,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800009ec:	0541                	addi	a0,a0,16
+800009ee:	3791                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:214
+        this_uart->status |= new_status;
+800009f0:	00444783          	lbu	a5,4(s0)
+800009f4:	8fc9                	or	a5,a5,a0
+800009f6:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:215
+        rx_full = new_status & STATUS_RXFULL_MASK;
+800009fa:	8909                	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216
+        while ( ( rx_full ) && ( rx_idx < buff_size ) )
+800009fc:	cd1d                	beqz	a0,80000a3a <UART_get_rx+0x6a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216 (discriminator 1)
+800009fe:	00991a63          	bne	s2,s1,80000a12 <UART_get_rx+0x42>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:227
+            this_uart->status |= new_status;
+            rx_full = new_status & STATUS_RXFULL_MASK;
+        }
+    }
+    return rx_idx;
+}
+80000a02:	40f2                	lw	ra,28(sp)
+80000a04:	4462                	lw	s0,24(sp)
+80000a06:	8526                	mv	a0,s1
+80000a08:	4942                	lw	s2,16(sp)
+80000a0a:	44d2                	lw	s1,20(sp)
+80000a0c:	49b2                	lw	s3,12(sp)
+80000a0e:	6105                	addi	sp,sp,32
+80000a10:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:218
+            rx_buffer[rx_idx] = HAL_get_8bit_reg( this_uart->base_address,
+80000a12:	4008                	lw	a0,0(s0)
+80000a14:	0511                	addi	a0,a0,4
+80000a16:	3f31                	jal	80000932 <HW_get_8bit_reg>
+80000a18:	012987b3          	add	a5,s3,s2
+80000a1c:	00a78023          	sb	a0,0(a5) # 2000 <STACK_SIZE+0x1c00>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+80000a20:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:220
+            rx_idx++;
+80000a22:	0905                	addi	s2,s2,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+80000a24:	0541                	addi	a0,a0,16
+80000a26:	3731                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:222
+            this_uart->status |= new_status;
+80000a28:	00444783          	lbu	a5,4(s0)
+80000a2c:	8fc9                	or	a5,a5,a0
+80000a2e:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:223
+            rx_full = new_status & STATUS_RXFULL_MASK;
+80000a32:	8909                	andi	a0,a0,2
+80000a34:	b7e1                	j	800009fc <UART_get_rx+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:202
+    size_t rx_idx = 0u;
+80000a36:	4481                	li	s1,0
+80000a38:	b7e9                	j	80000a02 <UART_get_rx+0x32>
+80000a3a:	84ca                	mv	s1,s2
+80000a3c:	b7d9                	j	80000a02 <UART_get_rx+0x32>
+
+80000a3e <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+80000a3e:	c91d                	beqz	a0,80000a74 <UART_polled_tx_string+0x36>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+80000a40:	c995                	beqz	a1,80000a74 <UART_polled_tx_string+0x36>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+{
+80000a42:	1141                	addi	sp,sp,-16
+80000a44:	c422                	sw	s0,8(sp)
+80000a46:	c226                	sw	s1,4(sp)
+80000a48:	c606                	sw	ra,12(sp)
+80000a4a:	84aa                	mv	s1,a0
+80000a4c:	842e                	mv	s0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+    {
+        char_idx = 0U;
+        while( 0U != p_sz_string[char_idx] )
+80000a4e:	00044783          	lbu	a5,0(s0)
+80000a52:	e791                	bnez	a5,80000a5e <UART_polled_tx_string+0x20>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+        }
+    }
+}
+80000a54:	40b2                	lw	ra,12(sp)
+80000a56:	4422                	lw	s0,8(sp)
+80000a58:	4492                	lw	s1,4(sp)
+80000a5a:	0141                	addi	sp,sp,16
+80000a5c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80000a5e:	4088                	lw	a0,0(s1)
+80000a60:	0541                	addi	a0,a0,16
+80000a62:	3dc1                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+            } while ( !tx_ready );
+80000a64:	8905                	andi	a0,a0,1
+80000a66:	dd65                	beqz	a0,80000a5e <UART_polled_tx_string+0x20>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+80000a68:	00044583          	lbu	a1,0(s0)
+80000a6c:	4088                	lw	a0,0(s1)
+80000a6e:	0405                	addi	s0,s0,1
+80000a70:	3d75                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+            char_idx++;
+80000a72:	bff1                	j	80000a4e <UART_polled_tx_string+0x10>
+80000a74:	8082                	ret
+
+80000a76 <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+80000a76:	1141                	addi	sp,sp,-16
+80000a78:	c422                	sw	s0,8(sp)
+80000a7a:	842a                	mv	s0,a0
+80000a7c:	c226                	sw	s1,4(sp)
+80000a7e:	c04a                	sw	s2,0(sp)
+80000a80:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    uint8_t i = 0;
+    addr_t cfg_reg_addr = base_addr;
+    
+    this_gpio->base_addr = base_addr;
+80000a82:	c00c                	sw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+{
+80000a84:	84ae                	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+80000a86:	c150                	sw	a2,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80000a88:	08058913          	addi	s2,a1,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80000a8c:	8526                	mv	a0,s1
+80000a8e:	4581                	li	a1,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+80000a90:	0491                	addi	s1,s1,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80000a92:	3d69                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80000a94:	ff249ce3          	bne	s1,s2,80000a8c <GPIO_init+0x16>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+80000a98:	405c                	lw	a5,4(s0)
+80000a9a:	4705                	li	a4,1
+80000a9c:	02e78063          	beq	a5,a4,80000abc <GPIO_init+0x46>
+80000aa0:	c3a1                	beqz	a5,80000ae0 <GPIO_init+0x6a>
+80000aa2:	4709                	li	a4,2
+80000aa4:	06e79b63          	bne	a5,a4,80000b1a <GPIO_init+0xa4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000aa8:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+80000aaa:	4422                	lw	s0,8(sp)
+80000aac:	40b2                	lw	ra,12(sp)
+80000aae:	4492                	lw	s1,4(sp)
+80000ab0:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000ab2:	55fd                	li	a1,-1
+80000ab4:	08050513          	addi	a0,a0,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000ab8:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000aba:	b511                	j	800008be <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+80000abc:	4008                	lw	a0,0(s0)
+80000abe:	64c1                	lui	s1,0x10
+80000ac0:	fff48593          	addi	a1,s1,-1 # ffff <STACK_SIZE+0xfbff>
+80000ac4:	08050513          	addi	a0,a0,128
+80000ac8:	352d                	jal	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000aca:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000acc:	4422                	lw	s0,8(sp)
+80000ace:	40b2                	lw	ra,12(sp)
+80000ad0:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ad2:	fff48593          	addi	a1,s1,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000ad6:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ad8:	08450513          	addi	a0,a0,132
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000adc:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ade:	bd11                	j	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+80000ae0:	4008                	lw	a0,0(s0)
+80000ae2:	0ff00593          	li	a1,255
+80000ae6:	08050513          	addi	a0,a0,128
+80000aea:	3589                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+80000aec:	4008                	lw	a0,0(s0)
+80000aee:	0ff00593          	li	a1,255
+80000af2:	08450513          	addi	a0,a0,132
+80000af6:	3d1d                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+80000af8:	4008                	lw	a0,0(s0)
+80000afa:	0ff00593          	li	a1,255
+80000afe:	08850513          	addi	a0,a0,136
+80000b02:	352d                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b04:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b06:	4422                	lw	s0,8(sp)
+80000b08:	40b2                	lw	ra,12(sp)
+80000b0a:	4492                	lw	s1,4(sp)
+80000b0c:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b0e:	0ff00593          	li	a1,255
+80000b12:	08c50513          	addi	a0,a0,140
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b16:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b18:	bd11                	j	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b1a:	40b2                	lw	ra,12(sp)
+80000b1c:	4422                	lw	s0,8(sp)
+80000b1e:	4492                	lw	s1,4(sp)
+80000b20:	4902                	lw	s2,0(sp)
+80000b22:	0141                	addi	sp,sp,16
+80000b24:	8082                	ret
+
+80000b26 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+    switch( this_gpio->apb_bus_width )
+80000b26:	415c                	lw	a5,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+80000b28:	1141                	addi	sp,sp,-16
+80000b2a:	c422                	sw	s0,8(sp)
+80000b2c:	c226                	sw	s1,4(sp)
+80000b2e:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+80000b30:	4705                	li	a4,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+80000b32:	842a                	mv	s0,a0
+80000b34:	84ae                	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+80000b36:	00e78e63          	beq	a5,a4,80000b52 <GPIO_set_outputs+0x2c>
+80000b3a:	cf85                	beqz	a5,80000b72 <GPIO_set_outputs+0x4c>
+80000b3c:	4709                	li	a4,2
+80000b3e:	06e79a63          	bne	a5,a4,80000bb2 <GPIO_set_outputs+0x8c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b42:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+}
+80000b44:	4422                	lw	s0,8(sp)
+80000b46:	40b2                	lw	ra,12(sp)
+80000b48:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b4a:	0a050513          	addi	a0,a0,160
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b4e:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b50:	b3bd                	j	800008be <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+80000b52:	4108                	lw	a0,0(a0)
+80000b54:	05c2                	slli	a1,a1,0x10
+80000b56:	81c1                	srli	a1,a1,0x10
+80000b58:	0a050513          	addi	a0,a0,160
+80000b5c:	3b59                	jal	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b5e:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b60:	4422                	lw	s0,8(sp)
+80000b62:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b64:	0104d593          	srli	a1,s1,0x10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b68:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b6a:	0a450513          	addi	a0,a0,164
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b6e:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b70:	b349                	j	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+80000b72:	4108                	lw	a0,0(a0)
+80000b74:	0ff5f593          	andi	a1,a1,255
+80000b78:	0a050513          	addi	a0,a0,160
+80000b7c:	3b45                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+80000b7e:	4008                	lw	a0,0(s0)
+80000b80:	0084d593          	srli	a1,s1,0x8
+80000b84:	0ff5f593          	andi	a1,a1,255
+80000b88:	0a450513          	addi	a0,a0,164
+80000b8c:	3345                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+80000b8e:	4008                	lw	a0,0(s0)
+80000b90:	0104d593          	srli	a1,s1,0x10
+80000b94:	0ff5f593          	andi	a1,a1,255
+80000b98:	0a850513          	addi	a0,a0,168
+80000b9c:	3b41                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000b9e:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000ba0:	4422                	lw	s0,8(sp)
+80000ba2:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000ba4:	0184d593          	srli	a1,s1,0x18
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000ba8:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000baa:	0ac50513          	addi	a0,a0,172
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000bae:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000bb0:	bbb5                	j	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000bb2:	40b2                	lw	ra,12(sp)
+80000bb4:	4422                	lw	s0,8(sp)
+80000bb6:	4492                	lw	s1,4(sp)
+80000bb8:	0141                	addi	sp,sp,16
+80000bba:	8082                	ret
+
+80000bbc <Software_IRQHandler>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000bbc:	6719                	lui	a4,0x6
+80000bbe:	531c                	lw	a5,32(a4)
+80000bc0:	9bf5                	andi	a5,a5,-3
+80000bc2:	d31c                	sw	a5,32(a4)
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:45
+ * in miv_rv32_stubs.c.
+ */
+void Software_IRQHandler()
+{
+    MRV_clear_soft_irq();
+}
+80000bc4:	8082                	ret
+
+80000bc6 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+ * Toggles the LEDs on the board through the GPIO and counts the number of Ticks
+ * that have occured and prints the interrupt count in message on the UART.
+ */
+
+void SysTick_Handler(void)
+{
+80000bc6:	1141                	addi	sp,sp,-16
+80000bc8:	c422                	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    static uint32_t interrupt_counter = 0;
+    interrupt_counter++;
+80000bca:	88418413          	addi	s0,gp,-1916 # 80004084 <interrupt_counter.2878>
+80000bce:	401c                	lw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+{
+80000bd0:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    static volatile uint32_t val = 0u;
+    val ^= 0xFu;
+    GPIO_set_outputs(&g_gpio_out, val);
+80000bd2:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    interrupt_counter++;
+80000bd6:	0785                	addi	a5,a5,1
+80000bd8:	c01c                	sw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:58
+    val ^= 0xFu;
+80000bda:	88818793          	addi	a5,gp,-1912 # 80004088 <val.2879>
+80000bde:	4398                	lw	a4,0(a5)
+80000be0:	00f74713          	xori	a4,a4,15
+80000be4:	c398                	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    GPIO_set_outputs(&g_gpio_out, val);
+80000be6:	438c                	lw	a1,0(a5)
+80000be8:	3f3d                	jal	80000b26 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bea:	400c                	lw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+80000bec:	4422                	lw	s0,8(sp)
+80000bee:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bf0:	00001517          	auipc	a0,0x1
+80000bf4:	20050513          	addi	a0,a0,512 # 80001df0 <local_irq_handler_table+0x40>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+80000bf8:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bfa:	a849                	j	80000c8c <iprintf>
+
+80000bfc <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+
+/*-------------------------------------------------------------------------//**
+  main() function.
+*/
+int main(void)
+{
+80000bfc:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    uint8_t rx_char;
+    uint8_t rx_count;
+    uint32_t switches;
+
+    UART_init(&g_uart,
+80000bfe:	4685                	li	a3,1
+80000c00:	4669                	li	a2,26
+80000c02:	710005b7          	lui	a1,0x71000
+80000c06:	8e818513          	addi	a0,gp,-1816 # 800040e8 <g_uart>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+{
+80000c0a:	c606                	sw	ra,12(sp)
+80000c0c:	c422                	sw	s0,8(sp)
+80000c0e:	c226                	sw	s1,4(sp)
+80000c10:	c04a                	sw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    UART_init(&g_uart,
+80000c12:	3b91                	jal	80000966 <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:77
+              COREUARTAPB0_BASE_ADDR,
+              BAUD_VALUE_115200,
+              (DATA_8_BITS | NO_PARITY));
+
+    printf(g_hello_msg);
+80000c14:	00003797          	auipc	a5,0x3
+80000c18:	3f078793          	addi	a5,a5,1008 # 80004004 <g_hello_msg>
+80000c1c:	4388                	lw	a0,0(a5)
+80000c1e:	20bd                	jal	80000c8c <iprintf>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:80
+
+    /* Initializing GPIOs */
+    GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+80000c20:	4609                	li	a2,2
+80000c22:	750005b7          	lui	a1,0x75000
+80000c26:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+80000c2a:	35b1                	jal	80000a76 <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:98
+	 * GPIO_config(&g_gpio_out, 0, GPIO_OUTPUT_MODE);
+     * GPIO_config(&g_gpio_out, 1, GPIO_OUTPUT_MODE);
+	 */
+
+    /* set the output value */
+    GPIO_set_outputs(&g_gpio_out, 0x0u);
+80000c2c:	4581                	li	a1,0
+80000c2e:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+80000c32:	3dd5                	jal	80000b26 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:101
+
+    /* This must be done for all Mi-V cores to enable interrupts globally. */
+    HAL_enable_interrupts();
+80000c34:	3151                	jal	800008b8 <HAL_enable_interrupts>
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80000c36:	070007b7          	lui	a5,0x7000
+80000c3a:	3047a7f3          	csrrs	a5,mie,a5
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:107
+
+#ifndef MIV_LEGACY_RV32
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn | MRV32_MSYS_EIE1_IRQn | MRV32_MSYS_EIE2_IRQn);
+#endif
+
+    MRV_systick_config(SYS_CLK_FREQ);
+80000c3e:	02faf537          	lui	a0,0x2faf
+80000c42:	08050513          	addi	a0,a0,128 # 2faf080 <STACK_SIZE+0x2faec80>
+80000c46:	4581                	li	a1,0
+80000c48:	348d                	jal	800006aa <MRV_systick_config>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:114
+    /**************************************************************************
+    * Loop
+    *************************************************************************/
+    do
+    {
+        g_rx_size = UART_get_rx(&g_uart, g_rx_buff, sizeof(g_rx_buff));
+80000c4a:	8a018493          	addi	s1,gp,-1888 # 800040a0 <__sbss_end>
+80000c4e:	8e818413          	addi	s0,gp,-1816 # 800040e8 <g_uart>
+80000c52:	88018913          	addi	s2,gp,-1920 # 80004080 <g_rx_size>
+80000c56:	04000613          	li	a2,64
+80000c5a:	8a018593          	addi	a1,gp,-1888 # 800040a0 <__sbss_end>
+80000c5e:	8522                	mv	a0,s0
+80000c60:	3b85                	jal	800009d0 <UART_get_rx>
+80000c62:	88a18023          	sb	a0,-1920(gp) # 80004080 <g_rx_size>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:116
+
+        if (g_rx_size > 0u)
+80000c66:	00094783          	lbu	a5,0(s2)
+80000c6a:	0ff7f793          	andi	a5,a5,255
+80000c6e:	d7e5                	beqz	a5,80000c56 <main+0x5a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:119
+        {
+            /* Echo the characters received from the terminal */
+            UART_polled_tx_string(&g_uart, (const uint8_t *)g_rx_buff);
+80000c70:	85a6                	mv	a1,s1
+80000c72:	8522                	mv	a0,s0
+80000c74:	33e9                	jal	80000a3e <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:120
+            g_rx_size = 0u;
+80000c76:	88018023          	sb	zero,-1920(gp) # 80004080 <g_rx_size>
+80000c7a:	bff1                	j	80000c56 <main+0x5a>
+
+80000c7c <memset>:
+memset():
+80000c7c:	832a                	mv	t1,a0
+80000c7e:	c611                	beqz	a2,80000c8a <memset+0xe>
+80000c80:	00b30023          	sb	a1,0(t1)
+80000c84:	167d                	addi	a2,a2,-1
+80000c86:	0305                	addi	t1,t1,1
+80000c88:	fe65                	bnez	a2,80000c80 <memset+0x4>
+80000c8a:	8082                	ret
+
+80000c8c <iprintf>:
+printf():
+80000c8c:	7139                	addi	sp,sp,-64
+80000c8e:	da3e                	sw	a5,52(sp)
+80000c90:	d22e                	sw	a1,36(sp)
+80000c92:	d432                	sw	a2,40(sp)
+80000c94:	d636                	sw	a3,44(sp)
+80000c96:	d83a                	sw	a4,48(sp)
+80000c98:	dc42                	sw	a6,56(sp)
+80000c9a:	de46                	sw	a7,60(sp)
+80000c9c:	00003797          	auipc	a5,0x3
+80000ca0:	36c78793          	addi	a5,a5,876 # 80004008 <_impure_ptr>
+80000ca4:	cc22                	sw	s0,24(sp)
+80000ca6:	4380                	lw	s0,0(a5)
+80000ca8:	ca26                	sw	s1,20(sp)
+80000caa:	ce06                	sw	ra,28(sp)
+80000cac:	84aa                	mv	s1,a0
+80000cae:	c409                	beqz	s0,80000cb8 <iprintf+0x2c>
+80000cb0:	4c1c                	lw	a5,24(s0)
+80000cb2:	e399                	bnez	a5,80000cb8 <iprintf+0x2c>
+80000cb4:	8522                	mv	a0,s0
+80000cb6:	28f5                	jal	80000db2 <__sinit>
+80000cb8:	440c                	lw	a1,8(s0)
+80000cba:	1054                	addi	a3,sp,36
+80000cbc:	8626                	mv	a2,s1
+80000cbe:	8522                	mv	a0,s0
+80000cc0:	c636                	sw	a3,12(sp)
+80000cc2:	264d                	jal	80001064 <_vfiprintf_r>
+80000cc4:	40f2                	lw	ra,28(sp)
+80000cc6:	4462                	lw	s0,24(sp)
+80000cc8:	44d2                	lw	s1,20(sp)
+80000cca:	6121                	addi	sp,sp,64
+80000ccc:	8082                	ret
+
+80000cce <isatty>:
+isatty():
+80000cce:	be55                	j	80000882 <_isatty>
+
+80000cd0 <_write_r>:
+_write_r():
+80000cd0:	1141                	addi	sp,sp,-16
+80000cd2:	c422                	sw	s0,8(sp)
+80000cd4:	842a                	mv	s0,a0
+80000cd6:	852e                	mv	a0,a1
+80000cd8:	85b2                	mv	a1,a2
+80000cda:	8636                	mv	a2,a3
+80000cdc:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80000ce0:	c606                	sw	ra,12(sp)
+80000ce2:	3ec9                	jal	800008b4 <_write>
+80000ce4:	57fd                	li	a5,-1
+80000ce6:	00f51763          	bne	a0,a5,80000cf4 <_write_r+0x24>
+80000cea:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80000cee:	439c                	lw	a5,0(a5)
+80000cf0:	c391                	beqz	a5,80000cf4 <_write_r+0x24>
+80000cf2:	c01c                	sw	a5,0(s0)
+80000cf4:	40b2                	lw	ra,12(sp)
+80000cf6:	4422                	lw	s0,8(sp)
+80000cf8:	0141                	addi	sp,sp,16
+80000cfa:	8082                	ret
+
+80000cfc <std>:
+std():
+80000cfc:	1141                	addi	sp,sp,-16
+80000cfe:	c422                	sw	s0,8(sp)
+80000d00:	c606                	sw	ra,12(sp)
+80000d02:	842a                	mv	s0,a0
+80000d04:	00b51623          	sh	a1,12(a0)
+80000d08:	00c51723          	sh	a2,14(a0)
+80000d0c:	00052023          	sw	zero,0(a0)
+80000d10:	00052223          	sw	zero,4(a0)
+80000d14:	00052423          	sw	zero,8(a0)
+80000d18:	06052223          	sw	zero,100(a0)
+80000d1c:	00052823          	sw	zero,16(a0)
+80000d20:	00052a23          	sw	zero,20(a0)
+80000d24:	00052c23          	sw	zero,24(a0)
+80000d28:	4621                	li	a2,8
+80000d2a:	4581                	li	a1,0
+80000d2c:	05c50513          	addi	a0,a0,92
+80000d30:	37b1                	jal	80000c7c <memset>
+80000d32:	00001797          	auipc	a5,0x1
+80000d36:	9a678793          	addi	a5,a5,-1626 # 800016d8 <__sread>
+80000d3a:	d05c                	sw	a5,36(s0)
+80000d3c:	00001797          	auipc	a5,0x1
+80000d40:	9cc78793          	addi	a5,a5,-1588 # 80001708 <__swrite>
+80000d44:	d41c                	sw	a5,40(s0)
+80000d46:	00001797          	auipc	a5,0x1
+80000d4a:	a1278793          	addi	a5,a5,-1518 # 80001758 <__sseek>
+80000d4e:	d45c                	sw	a5,44(s0)
+80000d50:	00001797          	auipc	a5,0x1
+80000d54:	a3e78793          	addi	a5,a5,-1474 # 8000178e <__sclose>
+80000d58:	d000                	sw	s0,32(s0)
+80000d5a:	d81c                	sw	a5,48(s0)
+80000d5c:	40b2                	lw	ra,12(sp)
+80000d5e:	4422                	lw	s0,8(sp)
+80000d60:	0141                	addi	sp,sp,16
+80000d62:	8082                	ret
+
+80000d64 <_cleanup_r>:
+_cleanup_r():
+80000d64:	00001597          	auipc	a1,0x1
+80000d68:	d7858593          	addi	a1,a1,-648 # 80001adc <_fflush_r>
+80000d6c:	a2b9                	j	80000eba <_fwalk_reent>
+
+80000d6e <__sfmoreglue>:
+__sfmoreglue():
+80000d6e:	1141                	addi	sp,sp,-16
+80000d70:	c226                	sw	s1,4(sp)
+80000d72:	06800613          	li	a2,104
+80000d76:	fff58493          	addi	s1,a1,-1
+80000d7a:	02c484b3          	mul	s1,s1,a2
+80000d7e:	c04a                	sw	s2,0(sp)
+80000d80:	892e                	mv	s2,a1
+80000d82:	c422                	sw	s0,8(sp)
+80000d84:	c606                	sw	ra,12(sp)
+80000d86:	07448593          	addi	a1,s1,116
+80000d8a:	2a71                	jal	80000f26 <_malloc_r>
+80000d8c:	842a                	mv	s0,a0
+80000d8e:	c919                	beqz	a0,80000da4 <__sfmoreglue+0x36>
+80000d90:	00052023          	sw	zero,0(a0)
+80000d94:	01252223          	sw	s2,4(a0)
+80000d98:	0531                	addi	a0,a0,12
+80000d9a:	c408                	sw	a0,8(s0)
+80000d9c:	06848613          	addi	a2,s1,104
+80000da0:	4581                	li	a1,0
+80000da2:	3de9                	jal	80000c7c <memset>
+80000da4:	8522                	mv	a0,s0
+80000da6:	40b2                	lw	ra,12(sp)
+80000da8:	4422                	lw	s0,8(sp)
+80000daa:	4492                	lw	s1,4(sp)
+80000dac:	4902                	lw	s2,0(sp)
+80000dae:	0141                	addi	sp,sp,16
+80000db0:	8082                	ret
+
+80000db2 <__sinit>:
+__sinit():
+80000db2:	4d1c                	lw	a5,24(a0)
+80000db4:	e3bd                	bnez	a5,80000e1a <__sinit+0x68>
+80000db6:	1141                	addi	sp,sp,-16
+80000db8:	c606                	sw	ra,12(sp)
+80000dba:	c422                	sw	s0,8(sp)
+80000dbc:	00000797          	auipc	a5,0x0
+80000dc0:	fa878793          	addi	a5,a5,-88 # 80000d64 <_cleanup_r>
+80000dc4:	d51c                	sw	a5,40(a0)
+80000dc6:	00001797          	auipc	a5,0x1
+80000dca:	26a78793          	addi	a5,a5,618 # 80002030 <_global_impure_ptr>
+80000dce:	439c                	lw	a5,0(a5)
+80000dd0:	04052423          	sw	zero,72(a0)
+80000dd4:	04052623          	sw	zero,76(a0)
+80000dd8:	04052823          	sw	zero,80(a0)
+80000ddc:	00f51463          	bne	a0,a5,80000de4 <__sinit+0x32>
+80000de0:	4785                	li	a5,1
+80000de2:	cd1c                	sw	a5,24(a0)
+80000de4:	842a                	mv	s0,a0
+80000de6:	281d                	jal	80000e1c <__sfp>
+80000de8:	c048                	sw	a0,4(s0)
+80000dea:	8522                	mv	a0,s0
+80000dec:	2805                	jal	80000e1c <__sfp>
+80000dee:	c408                	sw	a0,8(s0)
+80000df0:	8522                	mv	a0,s0
+80000df2:	202d                	jal	80000e1c <__sfp>
+80000df4:	c448                	sw	a0,12(s0)
+80000df6:	4048                	lw	a0,4(s0)
+80000df8:	4601                	li	a2,0
+80000dfa:	4591                	li	a1,4
+80000dfc:	3701                	jal	80000cfc <std>
+80000dfe:	4408                	lw	a0,8(s0)
+80000e00:	4605                	li	a2,1
+80000e02:	45a5                	li	a1,9
+80000e04:	3de5                	jal	80000cfc <std>
+80000e06:	4448                	lw	a0,12(s0)
+80000e08:	4609                	li	a2,2
+80000e0a:	45c9                	li	a1,18
+80000e0c:	3dc5                	jal	80000cfc <std>
+80000e0e:	4785                	li	a5,1
+80000e10:	cc1c                	sw	a5,24(s0)
+80000e12:	40b2                	lw	ra,12(sp)
+80000e14:	4422                	lw	s0,8(sp)
+80000e16:	0141                	addi	sp,sp,16
+80000e18:	8082                	ret
+80000e1a:	8082                	ret
+
+80000e1c <__sfp>:
+__sfp():
+80000e1c:	1141                	addi	sp,sp,-16
+80000e1e:	00001797          	auipc	a5,0x1
+80000e22:	21278793          	addi	a5,a5,530 # 80002030 <_global_impure_ptr>
+80000e26:	c226                	sw	s1,4(sp)
+80000e28:	4384                	lw	s1,0(a5)
+80000e2a:	c04a                	sw	s2,0(sp)
+80000e2c:	c606                	sw	ra,12(sp)
+80000e2e:	4c9c                	lw	a5,24(s1)
+80000e30:	c422                	sw	s0,8(sp)
+80000e32:	892a                	mv	s2,a0
+80000e34:	e399                	bnez	a5,80000e3a <__sfp+0x1e>
+80000e36:	8526                	mv	a0,s1
+80000e38:	3fad                	jal	80000db2 <__sinit>
+80000e3a:	04848493          	addi	s1,s1,72
+80000e3e:	4480                	lw	s0,8(s1)
+80000e40:	40dc                	lw	a5,4(s1)
+80000e42:	17fd                	addi	a5,a5,-1
+80000e44:	0007d663          	bgez	a5,80000e50 <__sfp+0x34>
+80000e48:	409c                	lw	a5,0(s1)
+80000e4a:	cfb1                	beqz	a5,80000ea6 <__sfp+0x8a>
+80000e4c:	4084                	lw	s1,0(s1)
+80000e4e:	bfc5                	j	80000e3e <__sfp+0x22>
+80000e50:	00c41703          	lh	a4,12(s0)
+80000e54:	e731                	bnez	a4,80000ea0 <__sfp+0x84>
+80000e56:	77c1                	lui	a5,0xffff0
+80000e58:	0785                	addi	a5,a5,1
+80000e5a:	06042223          	sw	zero,100(s0)
+80000e5e:	00042023          	sw	zero,0(s0)
+80000e62:	00042223          	sw	zero,4(s0)
+80000e66:	00042423          	sw	zero,8(s0)
+80000e6a:	c45c                	sw	a5,12(s0)
+80000e6c:	00042823          	sw	zero,16(s0)
+80000e70:	00042a23          	sw	zero,20(s0)
+80000e74:	00042c23          	sw	zero,24(s0)
+80000e78:	4621                	li	a2,8
+80000e7a:	4581                	li	a1,0
+80000e7c:	05c40513          	addi	a0,s0,92
+80000e80:	3bf5                	jal	80000c7c <memset>
+80000e82:	02042a23          	sw	zero,52(s0)
+80000e86:	02042c23          	sw	zero,56(s0)
+80000e8a:	04042423          	sw	zero,72(s0)
+80000e8e:	04042623          	sw	zero,76(s0)
+80000e92:	8522                	mv	a0,s0
+80000e94:	40b2                	lw	ra,12(sp)
+80000e96:	4422                	lw	s0,8(sp)
+80000e98:	4492                	lw	s1,4(sp)
+80000e9a:	4902                	lw	s2,0(sp)
+80000e9c:	0141                	addi	sp,sp,16
+80000e9e:	8082                	ret
+80000ea0:	06840413          	addi	s0,s0,104
+80000ea4:	bf79                	j	80000e42 <__sfp+0x26>
+80000ea6:	4591                	li	a1,4
+80000ea8:	854a                	mv	a0,s2
+80000eaa:	35d1                	jal	80000d6e <__sfmoreglue>
+80000eac:	c088                	sw	a0,0(s1)
+80000eae:	842a                	mv	s0,a0
+80000eb0:	fd51                	bnez	a0,80000e4c <__sfp+0x30>
+80000eb2:	47b1                	li	a5,12
+80000eb4:	00f92023          	sw	a5,0(s2)
+80000eb8:	bfe9                	j	80000e92 <__sfp+0x76>
+
+80000eba <_fwalk_reent>:
+_fwalk_reent():
+80000eba:	7179                	addi	sp,sp,-48
+80000ebc:	d422                	sw	s0,40(sp)
+80000ebe:	d04a                	sw	s2,32(sp)
+80000ec0:	cc52                	sw	s4,24(sp)
+80000ec2:	ca56                	sw	s5,20(sp)
+80000ec4:	c85a                	sw	s6,16(sp)
+80000ec6:	c65e                	sw	s7,12(sp)
+80000ec8:	d606                	sw	ra,44(sp)
+80000eca:	d226                	sw	s1,36(sp)
+80000ecc:	ce4e                	sw	s3,28(sp)
+80000ece:	8a2a                	mv	s4,a0
+80000ed0:	8aae                	mv	s5,a1
+80000ed2:	04850413          	addi	s0,a0,72
+80000ed6:	4901                	li	s2,0
+80000ed8:	4b05                	li	s6,1
+80000eda:	5bfd                	li	s7,-1
+80000edc:	ec09                	bnez	s0,80000ef6 <_fwalk_reent+0x3c>
+80000ede:	50b2                	lw	ra,44(sp)
+80000ee0:	5422                	lw	s0,40(sp)
+80000ee2:	854a                	mv	a0,s2
+80000ee4:	5492                	lw	s1,36(sp)
+80000ee6:	5902                	lw	s2,32(sp)
+80000ee8:	49f2                	lw	s3,28(sp)
+80000eea:	4a62                	lw	s4,24(sp)
+80000eec:	4ad2                	lw	s5,20(sp)
+80000eee:	4b42                	lw	s6,16(sp)
+80000ef0:	4bb2                	lw	s7,12(sp)
+80000ef2:	6145                	addi	sp,sp,48
+80000ef4:	8082                	ret
+80000ef6:	4404                	lw	s1,8(s0)
+80000ef8:	00442983          	lw	s3,4(s0)
+80000efc:	19fd                	addi	s3,s3,-1
+80000efe:	0009d463          	bgez	s3,80000f06 <_fwalk_reent+0x4c>
+80000f02:	4000                	lw	s0,0(s0)
+80000f04:	bfe1                	j	80000edc <_fwalk_reent+0x22>
+80000f06:	00c4d783          	lhu	a5,12(s1)
+80000f0a:	00fb7b63          	bgeu	s6,a5,80000f20 <_fwalk_reent+0x66>
+80000f0e:	00e49783          	lh	a5,14(s1)
+80000f12:	01778763          	beq	a5,s7,80000f20 <_fwalk_reent+0x66>
+80000f16:	85a6                	mv	a1,s1
+80000f18:	8552                	mv	a0,s4
+80000f1a:	9a82                	jalr	s5
+80000f1c:	00a96933          	or	s2,s2,a0
+80000f20:	06848493          	addi	s1,s1,104
+80000f24:	bfe1                	j	80000efc <_fwalk_reent+0x42>
+
+80000f26 <_malloc_r>:
+_malloc_r():
+80000f26:	1101                	addi	sp,sp,-32
+80000f28:	ca26                	sw	s1,20(sp)
+80000f2a:	00358493          	addi	s1,a1,3
+80000f2e:	98f1                	andi	s1,s1,-4
+80000f30:	ce06                	sw	ra,28(sp)
+80000f32:	cc22                	sw	s0,24(sp)
+80000f34:	c84a                	sw	s2,16(sp)
+80000f36:	c64e                	sw	s3,12(sp)
+80000f38:	04a1                	addi	s1,s1,8
+80000f3a:	47b1                	li	a5,12
+80000f3c:	04f4f363          	bgeu	s1,a5,80000f82 <_malloc_r+0x5c>
+80000f40:	44b1                	li	s1,12
+80000f42:	04b4e263          	bltu	s1,a1,80000f86 <_malloc_r+0x60>
+80000f46:	892a                	mv	s2,a0
+80000f48:	539000ef          	jal	ra,80001c80 <__malloc_lock>
+80000f4c:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+80000f50:	4398                	lw	a4,0(a5)
+80000f52:	843a                	mv	s0,a4
+80000f54:	e039                	bnez	s0,80000f9a <_malloc_r+0x74>
+80000f56:	89018793          	addi	a5,gp,-1904 # 80004090 <__malloc_sbrk_start>
+80000f5a:	439c                	lw	a5,0(a5)
+80000f5c:	e791                	bnez	a5,80000f68 <_malloc_r+0x42>
+80000f5e:	4581                	li	a1,0
+80000f60:	854a                	mv	a0,s2
+80000f62:	27b1                	jal	800016ae <_sbrk_r>
+80000f64:	88a1a823          	sw	a0,-1904(gp) # 80004090 <__malloc_sbrk_start>
+80000f68:	85a6                	mv	a1,s1
+80000f6a:	854a                	mv	a0,s2
+80000f6c:	2789                	jal	800016ae <_sbrk_r>
+80000f6e:	59fd                	li	s3,-1
+80000f70:	07351963          	bne	a0,s3,80000fe2 <_malloc_r+0xbc>
+80000f74:	47b1                	li	a5,12
+80000f76:	00f92023          	sw	a5,0(s2)
+80000f7a:	854a                	mv	a0,s2
+80000f7c:	507000ef          	jal	ra,80001c82 <__malloc_unlock>
+80000f80:	a029                	j	80000f8a <_malloc_r+0x64>
+80000f82:	fc04d0e3          	bgez	s1,80000f42 <_malloc_r+0x1c>
+80000f86:	47b1                	li	a5,12
+80000f88:	c11c                	sw	a5,0(a0)
+80000f8a:	4501                	li	a0,0
+80000f8c:	40f2                	lw	ra,28(sp)
+80000f8e:	4462                	lw	s0,24(sp)
+80000f90:	44d2                	lw	s1,20(sp)
+80000f92:	4942                	lw	s2,16(sp)
+80000f94:	49b2                	lw	s3,12(sp)
+80000f96:	6105                	addi	sp,sp,32
+80000f98:	8082                	ret
+80000f9a:	401c                	lw	a5,0(s0)
+80000f9c:	8f85                	sub	a5,a5,s1
+80000f9e:	0207cf63          	bltz	a5,80000fdc <_malloc_r+0xb6>
+80000fa2:	46ad                	li	a3,11
+80000fa4:	00f6f663          	bgeu	a3,a5,80000fb0 <_malloc_r+0x8a>
+80000fa8:	c01c                	sw	a5,0(s0)
+80000faa:	943e                	add	s0,s0,a5
+80000fac:	c004                	sw	s1,0(s0)
+80000fae:	a031                	j	80000fba <_malloc_r+0x94>
+80000fb0:	405c                	lw	a5,4(s0)
+80000fb2:	02871363          	bne	a4,s0,80000fd8 <_malloc_r+0xb2>
+80000fb6:	88f1a623          	sw	a5,-1908(gp) # 8000408c <__malloc_free_list>
+80000fba:	854a                	mv	a0,s2
+80000fbc:	4c7000ef          	jal	ra,80001c82 <__malloc_unlock>
+80000fc0:	00b40513          	addi	a0,s0,11
+80000fc4:	00440793          	addi	a5,s0,4
+80000fc8:	9961                	andi	a0,a0,-8
+80000fca:	40f50733          	sub	a4,a0,a5
+80000fce:	df5d                	beqz	a4,80000f8c <_malloc_r+0x66>
+80000fd0:	943a                	add	s0,s0,a4
+80000fd2:	8f89                	sub	a5,a5,a0
+80000fd4:	c01c                	sw	a5,0(s0)
+80000fd6:	bf5d                	j	80000f8c <_malloc_r+0x66>
+80000fd8:	c35c                	sw	a5,4(a4)
+80000fda:	b7c5                	j	80000fba <_malloc_r+0x94>
+80000fdc:	8722                	mv	a4,s0
+80000fde:	4040                	lw	s0,4(s0)
+80000fe0:	bf95                	j	80000f54 <_malloc_r+0x2e>
+80000fe2:	00350413          	addi	s0,a0,3
+80000fe6:	9871                	andi	s0,s0,-4
+80000fe8:	fc8502e3          	beq	a0,s0,80000fac <_malloc_r+0x86>
+80000fec:	40a405b3          	sub	a1,s0,a0
+80000ff0:	854a                	mv	a0,s2
+80000ff2:	2d75                	jal	800016ae <_sbrk_r>
+80000ff4:	fb351ce3          	bne	a0,s3,80000fac <_malloc_r+0x86>
+80000ff8:	bfb5                	j	80000f74 <_malloc_r+0x4e>
+
+80000ffa <__sfputc_r>:
+__sfputc_r():
+80000ffa:	461c                	lw	a5,8(a2)
+80000ffc:	17fd                	addi	a5,a5,-1
+80000ffe:	c61c                	sw	a5,8(a2)
+80001000:	0007d963          	bgez	a5,80001012 <__sfputc_r+0x18>
+80001004:	4e18                	lw	a4,24(a2)
+80001006:	00e7c563          	blt	a5,a4,80001010 <__sfputc_r+0x16>
+8000100a:	47a9                	li	a5,10
+8000100c:	00f59363          	bne	a1,a5,80001012 <__sfputc_r+0x18>
+80001010:	a751                	j	80001794 <__swbuf_r>
+80001012:	421c                	lw	a5,0(a2)
+80001014:	852e                	mv	a0,a1
+80001016:	00178713          	addi	a4,a5,1 # ffff0001 <__global_pointer$+0x7ffeb801>
+8000101a:	c218                	sw	a4,0(a2)
+8000101c:	00b78023          	sb	a1,0(a5)
+80001020:	8082                	ret
+
+80001022 <__sfputs_r>:
+__sfputs_r():
+80001022:	1101                	addi	sp,sp,-32
+80001024:	cc22                	sw	s0,24(sp)
+80001026:	ca26                	sw	s1,20(sp)
+80001028:	c84a                	sw	s2,16(sp)
+8000102a:	c64e                	sw	s3,12(sp)
+8000102c:	c452                	sw	s4,8(sp)
+8000102e:	ce06                	sw	ra,28(sp)
+80001030:	892a                	mv	s2,a0
+80001032:	89ae                	mv	s3,a1
+80001034:	8432                	mv	s0,a2
+80001036:	00d604b3          	add	s1,a2,a3
+8000103a:	5a7d                	li	s4,-1
+8000103c:	00941463          	bne	s0,s1,80001044 <__sfputs_r+0x22>
+80001040:	4501                	li	a0,0
+80001042:	a809                	j	80001054 <__sfputs_r+0x32>
+80001044:	00044583          	lbu	a1,0(s0)
+80001048:	864e                	mv	a2,s3
+8000104a:	854a                	mv	a0,s2
+8000104c:	377d                	jal	80000ffa <__sfputc_r>
+8000104e:	0405                	addi	s0,s0,1
+80001050:	ff4516e3          	bne	a0,s4,8000103c <__sfputs_r+0x1a>
+80001054:	40f2                	lw	ra,28(sp)
+80001056:	4462                	lw	s0,24(sp)
+80001058:	44d2                	lw	s1,20(sp)
+8000105a:	4942                	lw	s2,16(sp)
+8000105c:	49b2                	lw	s3,12(sp)
+8000105e:	4a22                	lw	s4,8(sp)
+80001060:	6105                	addi	sp,sp,32
+80001062:	8082                	ret
+
+80001064 <_vfiprintf_r>:
+_vfiprintf_r():
+80001064:	7135                	addi	sp,sp,-160
+80001066:	cd22                	sw	s0,152(sp)
+80001068:	cb26                	sw	s1,148(sp)
+8000106a:	c94a                	sw	s2,144(sp)
+8000106c:	c74e                	sw	s3,140(sp)
+8000106e:	cf06                	sw	ra,156(sp)
+80001070:	c552                	sw	s4,136(sp)
+80001072:	c356                	sw	s5,132(sp)
+80001074:	c15a                	sw	s6,128(sp)
+80001076:	dede                	sw	s7,124(sp)
+80001078:	dce2                	sw	s8,120(sp)
+8000107a:	dae6                	sw	s9,116(sp)
+8000107c:	89aa                	mv	s3,a0
+8000107e:	84ae                	mv	s1,a1
+80001080:	8932                	mv	s2,a2
+80001082:	8436                	mv	s0,a3
+80001084:	c501                	beqz	a0,8000108c <_vfiprintf_r+0x28>
+80001086:	4d1c                	lw	a5,24(a0)
+80001088:	e391                	bnez	a5,8000108c <_vfiprintf_r+0x28>
+8000108a:	3325                	jal	80000db2 <__sinit>
+8000108c:	00001797          	auipc	a5,0x1
+80001090:	f2078793          	addi	a5,a5,-224 # 80001fac <__sf_fake_stdin>
+80001094:	0cf49c63          	bne	s1,a5,8000116c <_vfiprintf_r+0x108>
+80001098:	0049a483          	lw	s1,4(s3)
+8000109c:	00c4d783          	lhu	a5,12(s1)
+800010a0:	8ba1                	andi	a5,a5,8
+800010a2:	c7fd                	beqz	a5,80001190 <_vfiprintf_r+0x12c>
+800010a4:	489c                	lw	a5,16(s1)
+800010a6:	c7ed                	beqz	a5,80001190 <_vfiprintf_r+0x12c>
+800010a8:	02000793          	li	a5,32
+800010ac:	02f104a3          	sb	a5,41(sp)
+800010b0:	03000793          	li	a5,48
+800010b4:	d202                	sw	zero,36(sp)
+800010b6:	02f10523          	sb	a5,42(sp)
+800010ba:	c622                	sw	s0,12(sp)
+800010bc:	02500b93          	li	s7,37
+800010c0:	00001a97          	auipc	s5,0x1
+800010c4:	f2ca8a93          	addi	s5,s5,-212 # 80001fec <__sf_fake_stdout+0x20>
+800010c8:	4c05                	li	s8,1
+800010ca:	4b29                	li	s6,10
+800010cc:	844a                	mv	s0,s2
+800010ce:	00044783          	lbu	a5,0(s0)
+800010d2:	c399                	beqz	a5,800010d8 <_vfiprintf_r+0x74>
+800010d4:	0f779063          	bne	a5,s7,800011b4 <_vfiprintf_r+0x150>
+800010d8:	41240cb3          	sub	s9,s0,s2
+800010dc:	000c8d63          	beqz	s9,800010f6 <_vfiprintf_r+0x92>
+800010e0:	86e6                	mv	a3,s9
+800010e2:	864a                	mv	a2,s2
+800010e4:	85a6                	mv	a1,s1
+800010e6:	854e                	mv	a0,s3
+800010e8:	3f2d                	jal	80001022 <__sfputs_r>
+800010ea:	57fd                	li	a5,-1
+800010ec:	1ef50863          	beq	a0,a5,800012dc <_vfiprintf_r+0x278>
+800010f0:	5692                	lw	a3,36(sp)
+800010f2:	96e6                	add	a3,a3,s9
+800010f4:	d236                	sw	a3,36(sp)
+800010f6:	00044783          	lbu	a5,0(s0)
+800010fa:	1e078163          	beqz	a5,800012dc <_vfiprintf_r+0x278>
+800010fe:	57fd                	li	a5,-1
+80001100:	00140913          	addi	s2,s0,1
+80001104:	c802                	sw	zero,16(sp)
+80001106:	ce02                	sw	zero,28(sp)
+80001108:	ca3e                	sw	a5,20(sp)
+8000110a:	cc02                	sw	zero,24(sp)
+8000110c:	040109a3          	sb	zero,83(sp)
+80001110:	d482                	sw	zero,104(sp)
+80001112:	00094583          	lbu	a1,0(s2)
+80001116:	4615                	li	a2,5
+80001118:	8556                	mv	a0,s5
+8000111a:	34d000ef          	jal	ra,80001c66 <memchr>
+8000111e:	00190413          	addi	s0,s2,1
+80001122:	47c2                	lw	a5,16(sp)
+80001124:	e951                	bnez	a0,800011b8 <_vfiprintf_r+0x154>
+80001126:	0107f713          	andi	a4,a5,16
+8000112a:	c709                	beqz	a4,80001134 <_vfiprintf_r+0xd0>
+8000112c:	02000713          	li	a4,32
+80001130:	04e109a3          	sb	a4,83(sp)
+80001134:	0087f713          	andi	a4,a5,8
+80001138:	c709                	beqz	a4,80001142 <_vfiprintf_r+0xde>
+8000113a:	02b00713          	li	a4,43
+8000113e:	04e109a3          	sb	a4,83(sp)
+80001142:	00094683          	lbu	a3,0(s2)
+80001146:	02a00713          	li	a4,42
+8000114a:	06e68f63          	beq	a3,a4,800011c8 <_vfiprintf_r+0x164>
+8000114e:	47f2                	lw	a5,28(sp)
+80001150:	844a                	mv	s0,s2
+80001152:	4681                	li	a3,0
+80001154:	4625                	li	a2,9
+80001156:	00044703          	lbu	a4,0(s0)
+8000115a:	00140593          	addi	a1,s0,1
+8000115e:	fd070713          	addi	a4,a4,-48 # 5fd0 <STACK_SIZE+0x5bd0>
+80001162:	0ae67863          	bgeu	a2,a4,80001212 <_vfiprintf_r+0x1ae>
+80001166:	caad                	beqz	a3,800011d8 <_vfiprintf_r+0x174>
+80001168:	ce3e                	sw	a5,28(sp)
+8000116a:	a0bd                	j	800011d8 <_vfiprintf_r+0x174>
+8000116c:	00001797          	auipc	a5,0x1
+80001170:	e6078793          	addi	a5,a5,-416 # 80001fcc <__sf_fake_stdout>
+80001174:	00f49563          	bne	s1,a5,8000117e <_vfiprintf_r+0x11a>
+80001178:	0089a483          	lw	s1,8(s3)
+8000117c:	b705                	j	8000109c <_vfiprintf_r+0x38>
+8000117e:	00001797          	auipc	a5,0x1
+80001182:	e0e78793          	addi	a5,a5,-498 # 80001f8c <__sf_fake_stderr>
+80001186:	f0f49be3          	bne	s1,a5,8000109c <_vfiprintf_r+0x38>
+8000118a:	00c9a483          	lw	s1,12(s3)
+8000118e:	b739                	j	8000109c <_vfiprintf_r+0x38>
+80001190:	85a6                	mv	a1,s1
+80001192:	854e                	mv	a0,s3
+80001194:	25c9                	jal	80001856 <__swsetup_r>
+80001196:	d909                	beqz	a0,800010a8 <_vfiprintf_r+0x44>
+80001198:	557d                	li	a0,-1
+8000119a:	40fa                	lw	ra,156(sp)
+8000119c:	446a                	lw	s0,152(sp)
+8000119e:	44da                	lw	s1,148(sp)
+800011a0:	494a                	lw	s2,144(sp)
+800011a2:	49ba                	lw	s3,140(sp)
+800011a4:	4a2a                	lw	s4,136(sp)
+800011a6:	4a9a                	lw	s5,132(sp)
+800011a8:	4b0a                	lw	s6,128(sp)
+800011aa:	5bf6                	lw	s7,124(sp)
+800011ac:	5c66                	lw	s8,120(sp)
+800011ae:	5cd6                	lw	s9,116(sp)
+800011b0:	610d                	addi	sp,sp,160
+800011b2:	8082                	ret
+800011b4:	0405                	addi	s0,s0,1
+800011b6:	bf21                	j	800010ce <_vfiprintf_r+0x6a>
+800011b8:	41550533          	sub	a0,a0,s5
+800011bc:	00ac1533          	sll	a0,s8,a0
+800011c0:	8fc9                	or	a5,a5,a0
+800011c2:	c83e                	sw	a5,16(sp)
+800011c4:	8922                	mv	s2,s0
+800011c6:	b7b1                	j	80001112 <_vfiprintf_r+0xae>
+800011c8:	4732                	lw	a4,12(sp)
+800011ca:	00470693          	addi	a3,a4,4
+800011ce:	4318                	lw	a4,0(a4)
+800011d0:	c636                	sw	a3,12(sp)
+800011d2:	02074963          	bltz	a4,80001204 <_vfiprintf_r+0x1a0>
+800011d6:	ce3a                	sw	a4,28(sp)
+800011d8:	00044703          	lbu	a4,0(s0)
+800011dc:	02e00793          	li	a5,46
+800011e0:	04f71f63          	bne	a4,a5,8000123e <_vfiprintf_r+0x1da>
+800011e4:	00144703          	lbu	a4,1(s0)
+800011e8:	02a00793          	li	a5,42
+800011ec:	02f71b63          	bne	a4,a5,80001222 <_vfiprintf_r+0x1be>
+800011f0:	47b2                	lw	a5,12(sp)
+800011f2:	0409                	addi	s0,s0,2
+800011f4:	00478713          	addi	a4,a5,4
+800011f8:	439c                	lw	a5,0(a5)
+800011fa:	c63a                	sw	a4,12(sp)
+800011fc:	0207c163          	bltz	a5,8000121e <_vfiprintf_r+0x1ba>
+80001200:	ca3e                	sw	a5,20(sp)
+80001202:	a835                	j	8000123e <_vfiprintf_r+0x1da>
+80001204:	40e00733          	neg	a4,a4
+80001208:	0027e793          	ori	a5,a5,2
+8000120c:	ce3a                	sw	a4,28(sp)
+8000120e:	c83e                	sw	a5,16(sp)
+80001210:	b7e1                	j	800011d8 <_vfiprintf_r+0x174>
+80001212:	036787b3          	mul	a5,a5,s6
+80001216:	4685                	li	a3,1
+80001218:	842e                	mv	s0,a1
+8000121a:	97ba                	add	a5,a5,a4
+8000121c:	bf2d                	j	80001156 <_vfiprintf_r+0xf2>
+8000121e:	57fd                	li	a5,-1
+80001220:	b7c5                	j	80001200 <_vfiprintf_r+0x19c>
+80001222:	0405                	addi	s0,s0,1
+80001224:	ca02                	sw	zero,20(sp)
+80001226:	4681                	li	a3,0
+80001228:	4781                	li	a5,0
+8000122a:	4625                	li	a2,9
+8000122c:	00044703          	lbu	a4,0(s0)
+80001230:	00140593          	addi	a1,s0,1
+80001234:	fd070713          	addi	a4,a4,-48
+80001238:	06e67863          	bgeu	a2,a4,800012a8 <_vfiprintf_r+0x244>
+8000123c:	f2f1                	bnez	a3,80001200 <_vfiprintf_r+0x19c>
+8000123e:	00044583          	lbu	a1,0(s0)
+80001242:	460d                	li	a2,3
+80001244:	00001517          	auipc	a0,0x1
+80001248:	db050513          	addi	a0,a0,-592 # 80001ff4 <__sf_fake_stdout+0x28>
+8000124c:	21b000ef          	jal	ra,80001c66 <memchr>
+80001250:	cd11                	beqz	a0,8000126c <_vfiprintf_r+0x208>
+80001252:	00001797          	auipc	a5,0x1
+80001256:	da278793          	addi	a5,a5,-606 # 80001ff4 <__sf_fake_stdout+0x28>
+8000125a:	8d1d                	sub	a0,a0,a5
+8000125c:	04000793          	li	a5,64
+80001260:	00a797b3          	sll	a5,a5,a0
+80001264:	4542                	lw	a0,16(sp)
+80001266:	0405                	addi	s0,s0,1
+80001268:	8d5d                	or	a0,a0,a5
+8000126a:	c82a                	sw	a0,16(sp)
+8000126c:	00044583          	lbu	a1,0(s0)
+80001270:	4619                	li	a2,6
+80001272:	00001517          	auipc	a0,0x1
+80001276:	d8650513          	addi	a0,a0,-634 # 80001ff8 <__sf_fake_stdout+0x2c>
+8000127a:	00140913          	addi	s2,s0,1
+8000127e:	02b10423          	sb	a1,40(sp)
+80001282:	1e5000ef          	jal	ra,80001c66 <memchr>
+80001286:	c13d                	beqz	a0,800012ec <_vfiprintf_r+0x288>
+80001288:	7ffff797          	auipc	a5,0x7ffff
+8000128c:	d7878793          	addi	a5,a5,-648 # 0 <__global_pointer$+0x7fffb800>
+80001290:	e795                	bnez	a5,800012bc <_vfiprintf_r+0x258>
+80001292:	4742                	lw	a4,16(sp)
+80001294:	47b2                	lw	a5,12(sp)
+80001296:	10077713          	andi	a4,a4,256
+8000129a:	cf09                	beqz	a4,800012b4 <_vfiprintf_r+0x250>
+8000129c:	0791                	addi	a5,a5,4
+8000129e:	c63e                	sw	a5,12(sp)
+800012a0:	5792                	lw	a5,36(sp)
+800012a2:	97d2                	add	a5,a5,s4
+800012a4:	d23e                	sw	a5,36(sp)
+800012a6:	b51d                	j	800010cc <_vfiprintf_r+0x68>
+800012a8:	036787b3          	mul	a5,a5,s6
+800012ac:	4685                	li	a3,1
+800012ae:	842e                	mv	s0,a1
+800012b0:	97ba                	add	a5,a5,a4
+800012b2:	bfad                	j	8000122c <_vfiprintf_r+0x1c8>
+800012b4:	079d                	addi	a5,a5,7
+800012b6:	9be1                	andi	a5,a5,-8
+800012b8:	07a1                	addi	a5,a5,8
+800012ba:	b7d5                	j	8000129e <_vfiprintf_r+0x23a>
+800012bc:	0078                	addi	a4,sp,12
+800012be:	00000697          	auipc	a3,0x0
+800012c2:	d6468693          	addi	a3,a3,-668 # 80001022 <__sfputs_r>
+800012c6:	8626                	mv	a2,s1
+800012c8:	080c                	addi	a1,sp,16
+800012ca:	854e                	mv	a0,s3
+800012cc:	00000097          	auipc	ra,0x0
+800012d0:	000000e7          	jalr	zero # 0 <HEAP_SIZE>
+800012d4:	57fd                	li	a5,-1
+800012d6:	8a2a                	mv	s4,a0
+800012d8:	fcf514e3          	bne	a0,a5,800012a0 <_vfiprintf_r+0x23c>
+800012dc:	00c4d783          	lhu	a5,12(s1)
+800012e0:	0407f793          	andi	a5,a5,64
+800012e4:	ea079ae3          	bnez	a5,80001198 <_vfiprintf_r+0x134>
+800012e8:	5512                	lw	a0,36(sp)
+800012ea:	bd45                	j	8000119a <_vfiprintf_r+0x136>
+800012ec:	0078                	addi	a4,sp,12
+800012ee:	00000697          	auipc	a3,0x0
+800012f2:	d3468693          	addi	a3,a3,-716 # 80001022 <__sfputs_r>
+800012f6:	8626                	mv	a2,s1
+800012f8:	080c                	addi	a1,sp,16
+800012fa:	854e                	mv	a0,s3
+800012fc:	2a01                	jal	8000140c <_printf_i>
+800012fe:	bfd9                	j	800012d4 <_vfiprintf_r+0x270>
+
+80001300 <_printf_common>:
+_printf_common():
+80001300:	7179                	addi	sp,sp,-48
+80001302:	ca56                	sw	s5,20(sp)
+80001304:	499c                	lw	a5,16(a1)
+80001306:	8aba                	mv	s5,a4
+80001308:	4598                	lw	a4,8(a1)
+8000130a:	d422                	sw	s0,40(sp)
+8000130c:	d226                	sw	s1,36(sp)
+8000130e:	ce4e                	sw	s3,28(sp)
+80001310:	cc52                	sw	s4,24(sp)
+80001312:	d606                	sw	ra,44(sp)
+80001314:	d04a                	sw	s2,32(sp)
+80001316:	c85a                	sw	s6,16(sp)
+80001318:	c65e                	sw	s7,12(sp)
+8000131a:	89aa                	mv	s3,a0
+8000131c:	842e                	mv	s0,a1
+8000131e:	84b2                	mv	s1,a2
+80001320:	8a36                	mv	s4,a3
+80001322:	00e7d363          	bge	a5,a4,80001328 <_printf_common+0x28>
+80001326:	87ba                	mv	a5,a4
+80001328:	c09c                	sw	a5,0(s1)
+8000132a:	04344703          	lbu	a4,67(s0)
+8000132e:	c319                	beqz	a4,80001334 <_printf_common+0x34>
+80001330:	0785                	addi	a5,a5,1
+80001332:	c09c                	sw	a5,0(s1)
+80001334:	401c                	lw	a5,0(s0)
+80001336:	0207f793          	andi	a5,a5,32
+8000133a:	c781                	beqz	a5,80001342 <_printf_common+0x42>
+8000133c:	409c                	lw	a5,0(s1)
+8000133e:	0789                	addi	a5,a5,2
+80001340:	c09c                	sw	a5,0(s1)
+80001342:	00042903          	lw	s2,0(s0)
+80001346:	00697913          	andi	s2,s2,6
+8000134a:	00091a63          	bnez	s2,8000135e <_printf_common+0x5e>
+8000134e:	01940b13          	addi	s6,s0,25
+80001352:	5bfd                	li	s7,-1
+80001354:	445c                	lw	a5,12(s0)
+80001356:	4098                	lw	a4,0(s1)
+80001358:	8f99                	sub	a5,a5,a4
+8000135a:	04f94c63          	blt	s2,a5,800013b2 <_printf_common+0xb2>
+8000135e:	401c                	lw	a5,0(s0)
+80001360:	04344683          	lbu	a3,67(s0)
+80001364:	0207f793          	andi	a5,a5,32
+80001368:	00d036b3          	snez	a3,a3
+8000136c:	eba5                	bnez	a5,800013dc <_printf_common+0xdc>
+8000136e:	04340613          	addi	a2,s0,67
+80001372:	85d2                	mv	a1,s4
+80001374:	854e                	mv	a0,s3
+80001376:	9a82                	jalr	s5
+80001378:	57fd                	li	a5,-1
+8000137a:	04f50363          	beq	a0,a5,800013c0 <_printf_common+0xc0>
+8000137e:	401c                	lw	a5,0(s0)
+80001380:	4611                	li	a2,4
+80001382:	4098                	lw	a4,0(s1)
+80001384:	8b99                	andi	a5,a5,6
+80001386:	4454                	lw	a3,12(s0)
+80001388:	4481                	li	s1,0
+8000138a:	00c79763          	bne	a5,a2,80001398 <_printf_common+0x98>
+8000138e:	40e684b3          	sub	s1,a3,a4
+80001392:	0004d363          	bgez	s1,80001398 <_printf_common+0x98>
+80001396:	4481                	li	s1,0
+80001398:	441c                	lw	a5,8(s0)
+8000139a:	4818                	lw	a4,16(s0)
+8000139c:	00f75463          	bge	a4,a5,800013a4 <_printf_common+0xa4>
+800013a0:	8f99                	sub	a5,a5,a4
+800013a2:	94be                	add	s1,s1,a5
+800013a4:	4901                	li	s2,0
+800013a6:	0469                	addi	s0,s0,26
+800013a8:	5b7d                	li	s6,-1
+800013aa:	05249863          	bne	s1,s2,800013fa <_printf_common+0xfa>
+800013ae:	4501                	li	a0,0
+800013b0:	a809                	j	800013c2 <_printf_common+0xc2>
+800013b2:	4685                	li	a3,1
+800013b4:	865a                	mv	a2,s6
+800013b6:	85d2                	mv	a1,s4
+800013b8:	854e                	mv	a0,s3
+800013ba:	9a82                	jalr	s5
+800013bc:	01751e63          	bne	a0,s7,800013d8 <_printf_common+0xd8>
+800013c0:	557d                	li	a0,-1
+800013c2:	50b2                	lw	ra,44(sp)
+800013c4:	5422                	lw	s0,40(sp)
+800013c6:	5492                	lw	s1,36(sp)
+800013c8:	5902                	lw	s2,32(sp)
+800013ca:	49f2                	lw	s3,28(sp)
+800013cc:	4a62                	lw	s4,24(sp)
+800013ce:	4ad2                	lw	s5,20(sp)
+800013d0:	4b42                	lw	s6,16(sp)
+800013d2:	4bb2                	lw	s7,12(sp)
+800013d4:	6145                	addi	sp,sp,48
+800013d6:	8082                	ret
+800013d8:	0905                	addi	s2,s2,1
+800013da:	bfad                	j	80001354 <_printf_common+0x54>
+800013dc:	00d40733          	add	a4,s0,a3
+800013e0:	03000613          	li	a2,48
+800013e4:	04c701a3          	sb	a2,67(a4)
+800013e8:	04544703          	lbu	a4,69(s0)
+800013ec:	00168793          	addi	a5,a3,1
+800013f0:	97a2                	add	a5,a5,s0
+800013f2:	0689                	addi	a3,a3,2
+800013f4:	04e781a3          	sb	a4,67(a5)
+800013f8:	bf9d                	j	8000136e <_printf_common+0x6e>
+800013fa:	4685                	li	a3,1
+800013fc:	8622                	mv	a2,s0
+800013fe:	85d2                	mv	a1,s4
+80001400:	854e                	mv	a0,s3
+80001402:	9a82                	jalr	s5
+80001404:	fb650ee3          	beq	a0,s6,800013c0 <_printf_common+0xc0>
+80001408:	0905                	addi	s2,s2,1
+8000140a:	b745                	j	800013aa <_printf_common+0xaa>
+
+8000140c <_printf_i>:
+_printf_i():
+8000140c:	7179                	addi	sp,sp,-48
+8000140e:	d422                	sw	s0,40(sp)
+80001410:	d226                	sw	s1,36(sp)
+80001412:	d04a                	sw	s2,32(sp)
+80001414:	ce4e                	sw	s3,28(sp)
+80001416:	d606                	sw	ra,44(sp)
+80001418:	cc52                	sw	s4,24(sp)
+8000141a:	ca56                	sw	s5,20(sp)
+8000141c:	c85a                	sw	s6,16(sp)
+8000141e:	89b6                	mv	s3,a3
+80001420:	0185c683          	lbu	a3,24(a1)
+80001424:	06e00793          	li	a5,110
+80001428:	8932                	mv	s2,a2
+8000142a:	84aa                	mv	s1,a0
+8000142c:	842e                	mv	s0,a1
+8000142e:	04358613          	addi	a2,a1,67
+80001432:	1ef68063          	beq	a3,a5,80001612 <_printf_i+0x206>
+80001436:	06d7e263          	bltu	a5,a3,8000149a <_printf_i+0x8e>
+8000143a:	06300793          	li	a5,99
+8000143e:	0af68263          	beq	a3,a5,800014e2 <_printf_i+0xd6>
+80001442:	00d7ed63          	bltu	a5,a3,8000145c <_printf_i+0x50>
+80001446:	1e068a63          	beqz	a3,8000163a <_printf_i+0x22e>
+8000144a:	05800793          	li	a5,88
+8000144e:	16f68663          	beq	a3,a5,800015ba <_printf_i+0x1ae>
+80001452:	04240a93          	addi	s5,s0,66
+80001456:	04d40123          	sb	a3,66(s0)
+8000145a:	a869                	j	800014f4 <_printf_i+0xe8>
+8000145c:	06400793          	li	a5,100
+80001460:	00f68663          	beq	a3,a5,8000146c <_printf_i+0x60>
+80001464:	06900793          	li	a5,105
+80001468:	fef695e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+8000146c:	401c                	lw	a5,0(s0)
+8000146e:	4308                	lw	a0,0(a4)
+80001470:	0807f693          	andi	a3,a5,128
+80001474:	00450593          	addi	a1,a0,4
+80001478:	c2c1                	beqz	a3,800014f8 <_printf_i+0xec>
+8000147a:	411c                	lw	a5,0(a0)
+8000147c:	c30c                	sw	a1,0(a4)
+8000147e:	0007d863          	bgez	a5,8000148e <_printf_i+0x82>
+80001482:	02d00713          	li	a4,45
+80001486:	40f007b3          	neg	a5,a5
+8000148a:	04e401a3          	sb	a4,67(s0)
+8000148e:	00001697          	auipc	a3,0x1
+80001492:	b7268693          	addi	a3,a3,-1166 # 80002000 <__sf_fake_stdout+0x34>
+80001496:	4729                	li	a4,10
+80001498:	a065                	j	80001540 <_printf_i+0x134>
+8000149a:	07300793          	li	a5,115
+8000149e:	1af68263          	beq	a3,a5,80001642 <_printf_i+0x236>
+800014a2:	00d7ef63          	bltu	a5,a3,800014c0 <_printf_i+0xb4>
+800014a6:	06f00793          	li	a5,111
+800014aa:	04f68f63          	beq	a3,a5,80001508 <_printf_i+0xfc>
+800014ae:	07000793          	li	a5,112
+800014b2:	faf690e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+800014b6:	419c                	lw	a5,0(a1)
+800014b8:	0207e793          	ori	a5,a5,32
+800014bc:	c19c                	sw	a5,0(a1)
+800014be:	a809                	j	800014d0 <_printf_i+0xc4>
+800014c0:	07500793          	li	a5,117
+800014c4:	04f68263          	beq	a3,a5,80001508 <_printf_i+0xfc>
+800014c8:	07800793          	li	a5,120
+800014cc:	f8f693e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+800014d0:	07800793          	li	a5,120
+800014d4:	04f402a3          	sb	a5,69(s0)
+800014d8:	00001697          	auipc	a3,0x1
+800014dc:	b3c68693          	addi	a3,a3,-1220 # 80002014 <__sf_fake_stdout+0x48>
+800014e0:	a0dd                	j	800015c6 <_printf_i+0x1ba>
+800014e2:	431c                	lw	a5,0(a4)
+800014e4:	04258a93          	addi	s5,a1,66
+800014e8:	00478693          	addi	a3,a5,4
+800014ec:	439c                	lw	a5,0(a5)
+800014ee:	c314                	sw	a3,0(a4)
+800014f0:	04f58123          	sb	a5,66(a1)
+800014f4:	4785                	li	a5,1
+800014f6:	a2ad                	j	80001660 <_printf_i+0x254>
+800014f8:	0407f693          	andi	a3,a5,64
+800014fc:	411c                	lw	a5,0(a0)
+800014fe:	c30c                	sw	a1,0(a4)
+80001500:	debd                	beqz	a3,8000147e <_printf_i+0x72>
+80001502:	07c2                	slli	a5,a5,0x10
+80001504:	87c1                	srai	a5,a5,0x10
+80001506:	bfa5                	j	8000147e <_printf_i+0x72>
+80001508:	400c                	lw	a1,0(s0)
+8000150a:	431c                	lw	a5,0(a4)
+8000150c:	0805f813          	andi	a6,a1,128
+80001510:	00478513          	addi	a0,a5,4
+80001514:	00080563          	beqz	a6,8000151e <_printf_i+0x112>
+80001518:	c308                	sw	a0,0(a4)
+8000151a:	439c                	lw	a5,0(a5)
+8000151c:	a039                	j	8000152a <_printf_i+0x11e>
+8000151e:	0405f593          	andi	a1,a1,64
+80001522:	c308                	sw	a0,0(a4)
+80001524:	d9fd                	beqz	a1,8000151a <_printf_i+0x10e>
+80001526:	0007d783          	lhu	a5,0(a5)
+8000152a:	06f00713          	li	a4,111
+8000152e:	0ce68a63          	beq	a3,a4,80001602 <_printf_i+0x1f6>
+80001532:	00001697          	auipc	a3,0x1
+80001536:	ace68693          	addi	a3,a3,-1330 # 80002000 <__sf_fake_stdout+0x34>
+8000153a:	4729                	li	a4,10
+8000153c:	040401a3          	sb	zero,67(s0)
+80001540:	404c                	lw	a1,4(s0)
+80001542:	c40c                	sw	a1,8(s0)
+80001544:	0005c563          	bltz	a1,8000154e <_printf_i+0x142>
+80001548:	4008                	lw	a0,0(s0)
+8000154a:	996d                	andi	a0,a0,-5
+8000154c:	c008                	sw	a0,0(s0)
+8000154e:	e399                	bnez	a5,80001554 <_printf_i+0x148>
+80001550:	8ab2                	mv	s5,a2
+80001552:	cd91                	beqz	a1,8000156e <_printf_i+0x162>
+80001554:	8ab2                	mv	s5,a2
+80001556:	02e7f5b3          	remu	a1,a5,a4
+8000155a:	1afd                	addi	s5,s5,-1
+8000155c:	95b6                	add	a1,a1,a3
+8000155e:	0005c583          	lbu	a1,0(a1)
+80001562:	00ba8023          	sb	a1,0(s5)
+80001566:	02e7d5b3          	divu	a1,a5,a4
+8000156a:	0ae7f263          	bgeu	a5,a4,8000160e <_printf_i+0x202>
+8000156e:	47a1                	li	a5,8
+80001570:	00f71e63          	bne	a4,a5,8000158c <_printf_i+0x180>
+80001574:	401c                	lw	a5,0(s0)
+80001576:	8b85                	andi	a5,a5,1
+80001578:	cb91                	beqz	a5,8000158c <_printf_i+0x180>
+8000157a:	4058                	lw	a4,4(s0)
+8000157c:	481c                	lw	a5,16(s0)
+8000157e:	00e7c763          	blt	a5,a4,8000158c <_printf_i+0x180>
+80001582:	03000793          	li	a5,48
+80001586:	fefa8fa3          	sb	a5,-1(s5)
+8000158a:	1afd                	addi	s5,s5,-1
+8000158c:	41560633          	sub	a2,a2,s5
+80001590:	c810                	sw	a2,16(s0)
+80001592:	874e                	mv	a4,s3
+80001594:	86ca                	mv	a3,s2
+80001596:	0070                	addi	a2,sp,12
+80001598:	85a2                	mv	a1,s0
+8000159a:	8526                	mv	a0,s1
+8000159c:	3395                	jal	80001300 <_printf_common>
+8000159e:	5a7d                	li	s4,-1
+800015a0:	0d451463          	bne	a0,s4,80001668 <_printf_i+0x25c>
+800015a4:	557d                	li	a0,-1
+800015a6:	50b2                	lw	ra,44(sp)
+800015a8:	5422                	lw	s0,40(sp)
+800015aa:	5492                	lw	s1,36(sp)
+800015ac:	5902                	lw	s2,32(sp)
+800015ae:	49f2                	lw	s3,28(sp)
+800015b0:	4a62                	lw	s4,24(sp)
+800015b2:	4ad2                	lw	s5,20(sp)
+800015b4:	4b42                	lw	s6,16(sp)
+800015b6:	6145                	addi	sp,sp,48
+800015b8:	8082                	ret
+800015ba:	04d582a3          	sb	a3,69(a1)
+800015be:	00001697          	auipc	a3,0x1
+800015c2:	a4268693          	addi	a3,a3,-1470 # 80002000 <__sf_fake_stdout+0x34>
+800015c6:	400c                	lw	a1,0(s0)
+800015c8:	4308                	lw	a0,0(a4)
+800015ca:	0805f813          	andi	a6,a1,128
+800015ce:	411c                	lw	a5,0(a0)
+800015d0:	0511                	addi	a0,a0,4
+800015d2:	02080063          	beqz	a6,800015f2 <_printf_i+0x1e6>
+800015d6:	c308                	sw	a0,0(a4)
+800015d8:	0015f713          	andi	a4,a1,1
+800015dc:	c701                	beqz	a4,800015e4 <_printf_i+0x1d8>
+800015de:	0205e593          	ori	a1,a1,32
+800015e2:	c00c                	sw	a1,0(s0)
+800015e4:	4741                	li	a4,16
+800015e6:	fbb9                	bnez	a5,8000153c <_printf_i+0x130>
+800015e8:	400c                	lw	a1,0(s0)
+800015ea:	fdf5f593          	andi	a1,a1,-33
+800015ee:	c00c                	sw	a1,0(s0)
+800015f0:	b7b1                	j	8000153c <_printf_i+0x130>
+800015f2:	0405f813          	andi	a6,a1,64
+800015f6:	c308                	sw	a0,0(a4)
+800015f8:	fe0800e3          	beqz	a6,800015d8 <_printf_i+0x1cc>
+800015fc:	07c2                	slli	a5,a5,0x10
+800015fe:	83c1                	srli	a5,a5,0x10
+80001600:	bfe1                	j	800015d8 <_printf_i+0x1cc>
+80001602:	00001697          	auipc	a3,0x1
+80001606:	9fe68693          	addi	a3,a3,-1538 # 80002000 <__sf_fake_stdout+0x34>
+8000160a:	4721                	li	a4,8
+8000160c:	bf05                	j	8000153c <_printf_i+0x130>
+8000160e:	87ae                	mv	a5,a1
+80001610:	b799                	j	80001556 <_printf_i+0x14a>
+80001612:	4194                	lw	a3,0(a1)
+80001614:	431c                	lw	a5,0(a4)
+80001616:	49cc                	lw	a1,20(a1)
+80001618:	0806f813          	andi	a6,a3,128
+8000161c:	00478513          	addi	a0,a5,4
+80001620:	00080663          	beqz	a6,8000162c <_printf_i+0x220>
+80001624:	c308                	sw	a0,0(a4)
+80001626:	439c                	lw	a5,0(a5)
+80001628:	c38c                	sw	a1,0(a5)
+8000162a:	a801                	j	8000163a <_printf_i+0x22e>
+8000162c:	c308                	sw	a0,0(a4)
+8000162e:	0406f693          	andi	a3,a3,64
+80001632:	439c                	lw	a5,0(a5)
+80001634:	daf5                	beqz	a3,80001628 <_printf_i+0x21c>
+80001636:	00b79023          	sh	a1,0(a5)
+8000163a:	00042823          	sw	zero,16(s0)
+8000163e:	8ab2                	mv	s5,a2
+80001640:	bf89                	j	80001592 <_printf_i+0x186>
+80001642:	431c                	lw	a5,0(a4)
+80001644:	41d0                	lw	a2,4(a1)
+80001646:	4581                	li	a1,0
+80001648:	00478693          	addi	a3,a5,4
+8000164c:	c314                	sw	a3,0(a4)
+8000164e:	0007aa83          	lw	s5,0(a5)
+80001652:	8556                	mv	a0,s5
+80001654:	2d09                	jal	80001c66 <memchr>
+80001656:	c501                	beqz	a0,8000165e <_printf_i+0x252>
+80001658:	41550533          	sub	a0,a0,s5
+8000165c:	c048                	sw	a0,4(s0)
+8000165e:	405c                	lw	a5,4(s0)
+80001660:	c81c                	sw	a5,16(s0)
+80001662:	040401a3          	sb	zero,67(s0)
+80001666:	b735                	j	80001592 <_printf_i+0x186>
+80001668:	4814                	lw	a3,16(s0)
+8000166a:	8656                	mv	a2,s5
+8000166c:	85ca                	mv	a1,s2
+8000166e:	8526                	mv	a0,s1
+80001670:	9982                	jalr	s3
+80001672:	f34509e3          	beq	a0,s4,800015a4 <_printf_i+0x198>
+80001676:	401c                	lw	a5,0(s0)
+80001678:	8b89                	andi	a5,a5,2
+8000167a:	e78d                	bnez	a5,800016a4 <_printf_i+0x298>
+8000167c:	47b2                	lw	a5,12(sp)
+8000167e:	4448                	lw	a0,12(s0)
+80001680:	f2f553e3          	bge	a0,a5,800015a6 <_printf_i+0x19a>
+80001684:	853e                	mv	a0,a5
+80001686:	b705                	j	800015a6 <_printf_i+0x19a>
+80001688:	4685                	li	a3,1
+8000168a:	8656                	mv	a2,s5
+8000168c:	85ca                	mv	a1,s2
+8000168e:	8526                	mv	a0,s1
+80001690:	9982                	jalr	s3
+80001692:	f16509e3          	beq	a0,s6,800015a4 <_printf_i+0x198>
+80001696:	0a05                	addi	s4,s4,1
+80001698:	445c                	lw	a5,12(s0)
+8000169a:	4732                	lw	a4,12(sp)
+8000169c:	8f99                	sub	a5,a5,a4
+8000169e:	fefa45e3          	blt	s4,a5,80001688 <_printf_i+0x27c>
+800016a2:	bfe9                	j	8000167c <_printf_i+0x270>
+800016a4:	4a01                	li	s4,0
+800016a6:	01940a93          	addi	s5,s0,25
+800016aa:	5b7d                	li	s6,-1
+800016ac:	b7f5                	j	80001698 <_printf_i+0x28c>
+
+800016ae <_sbrk_r>:
+_sbrk_r():
+800016ae:	1141                	addi	sp,sp,-16
+800016b0:	c422                	sw	s0,8(sp)
+800016b2:	842a                	mv	s0,a0
+800016b4:	852e                	mv	a0,a1
+800016b6:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+800016ba:	c606                	sw	ra,12(sp)
+800016bc:	99aff0ef          	jal	ra,80000856 <_sbrk>
+800016c0:	57fd                	li	a5,-1
+800016c2:	00f51763          	bne	a0,a5,800016d0 <_sbrk_r+0x22>
+800016c6:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+800016ca:	439c                	lw	a5,0(a5)
+800016cc:	c391                	beqz	a5,800016d0 <_sbrk_r+0x22>
+800016ce:	c01c                	sw	a5,0(s0)
+800016d0:	40b2                	lw	ra,12(sp)
+800016d2:	4422                	lw	s0,8(sp)
+800016d4:	0141                	addi	sp,sp,16
+800016d6:	8082                	ret
+
+800016d8 <__sread>:
+__sread():
+800016d8:	1141                	addi	sp,sp,-16
+800016da:	c422                	sw	s0,8(sp)
+800016dc:	842e                	mv	s0,a1
+800016de:	00e59583          	lh	a1,14(a1)
+800016e2:	c606                	sw	ra,12(sp)
+800016e4:	2591                	jal	80001d28 <_read_r>
+800016e6:	00054963          	bltz	a0,800016f8 <__sread+0x20>
+800016ea:	487c                	lw	a5,84(s0)
+800016ec:	97aa                	add	a5,a5,a0
+800016ee:	c87c                	sw	a5,84(s0)
+800016f0:	40b2                	lw	ra,12(sp)
+800016f2:	4422                	lw	s0,8(sp)
+800016f4:	0141                	addi	sp,sp,16
+800016f6:	8082                	ret
+800016f8:	00c45783          	lhu	a5,12(s0)
+800016fc:	777d                	lui	a4,0xfffff
+800016fe:	177d                	addi	a4,a4,-1
+80001700:	8ff9                	and	a5,a5,a4
+80001702:	00f41623          	sh	a5,12(s0)
+80001706:	b7ed                	j	800016f0 <__sread+0x18>
+
+80001708 <__swrite>:
+__swrite():
+80001708:	00c5d783          	lhu	a5,12(a1)
+8000170c:	1101                	addi	sp,sp,-32
+8000170e:	cc22                	sw	s0,24(sp)
+80001710:	ca26                	sw	s1,20(sp)
+80001712:	c84a                	sw	s2,16(sp)
+80001714:	c64e                	sw	s3,12(sp)
+80001716:	ce06                	sw	ra,28(sp)
+80001718:	1007f793          	andi	a5,a5,256
+8000171c:	84aa                	mv	s1,a0
+8000171e:	842e                	mv	s0,a1
+80001720:	8932                	mv	s2,a2
+80001722:	89b6                	mv	s3,a3
+80001724:	c791                	beqz	a5,80001730 <__swrite+0x28>
+80001726:	00e59583          	lh	a1,14(a1)
+8000172a:	4689                	li	a3,2
+8000172c:	4601                	li	a2,0
+8000172e:	2911                	jal	80001b42 <_lseek_r>
+80001730:	00c45783          	lhu	a5,12(s0)
+80001734:	777d                	lui	a4,0xfffff
+80001736:	177d                	addi	a4,a4,-1
+80001738:	8ff9                	and	a5,a5,a4
+8000173a:	00f41623          	sh	a5,12(s0)
+8000173e:	00e41583          	lh	a1,14(s0)
+80001742:	4462                	lw	s0,24(sp)
+80001744:	40f2                	lw	ra,28(sp)
+80001746:	86ce                	mv	a3,s3
+80001748:	864a                	mv	a2,s2
+8000174a:	49b2                	lw	s3,12(sp)
+8000174c:	4942                	lw	s2,16(sp)
+8000174e:	8526                	mv	a0,s1
+80001750:	44d2                	lw	s1,20(sp)
+80001752:	6105                	addi	sp,sp,32
+80001754:	d7cff06f          	j	80000cd0 <_write_r>
+
+80001758 <__sseek>:
+__sseek():
+80001758:	1141                	addi	sp,sp,-16
+8000175a:	c422                	sw	s0,8(sp)
+8000175c:	842e                	mv	s0,a1
+8000175e:	00e59583          	lh	a1,14(a1)
+80001762:	c606                	sw	ra,12(sp)
+80001764:	2ef9                	jal	80001b42 <_lseek_r>
+80001766:	57fd                	li	a5,-1
+80001768:	00c45703          	lhu	a4,12(s0)
+8000176c:	00f51b63          	bne	a0,a5,80001782 <__sseek+0x2a>
+80001770:	77fd                	lui	a5,0xfffff
+80001772:	17fd                	addi	a5,a5,-1
+80001774:	8ff9                	and	a5,a5,a4
+80001776:	00f41623          	sh	a5,12(s0)
+8000177a:	40b2                	lw	ra,12(sp)
+8000177c:	4422                	lw	s0,8(sp)
+8000177e:	0141                	addi	sp,sp,16
+80001780:	8082                	ret
+80001782:	6785                	lui	a5,0x1
+80001784:	8fd9                	or	a5,a5,a4
+80001786:	00f41623          	sh	a5,12(s0)
+8000178a:	c868                	sw	a0,84(s0)
+8000178c:	b7fd                	j	8000177a <__sseek+0x22>
+
+8000178e <__sclose>:
+__sclose():
+8000178e:	00e59583          	lh	a1,14(a1)
+80001792:	aad9                	j	80001968 <_close_r>
+
+80001794 <__swbuf_r>:
+__swbuf_r():
+80001794:	1101                	addi	sp,sp,-32
+80001796:	cc22                	sw	s0,24(sp)
+80001798:	ca26                	sw	s1,20(sp)
+8000179a:	c84a                	sw	s2,16(sp)
+8000179c:	ce06                	sw	ra,28(sp)
+8000179e:	c64e                	sw	s3,12(sp)
+800017a0:	84aa                	mv	s1,a0
+800017a2:	892e                	mv	s2,a1
+800017a4:	8432                	mv	s0,a2
+800017a6:	c509                	beqz	a0,800017b0 <__swbuf_r+0x1c>
+800017a8:	4d1c                	lw	a5,24(a0)
+800017aa:	e399                	bnez	a5,800017b0 <__swbuf_r+0x1c>
+800017ac:	e06ff0ef          	jal	ra,80000db2 <__sinit>
+800017b0:	00000797          	auipc	a5,0x0
+800017b4:	7fc78793          	addi	a5,a5,2044 # 80001fac <__sf_fake_stdin>
+800017b8:	06f41963          	bne	s0,a5,8000182a <__swbuf_r+0x96>
+800017bc:	40c0                	lw	s0,4(s1)
+800017be:	4c1c                	lw	a5,24(s0)
+800017c0:	c41c                	sw	a5,8(s0)
+800017c2:	00c45783          	lhu	a5,12(s0)
+800017c6:	8ba1                	andi	a5,a5,8
+800017c8:	c3c9                	beqz	a5,8000184a <__swbuf_r+0xb6>
+800017ca:	481c                	lw	a5,16(s0)
+800017cc:	cfbd                	beqz	a5,8000184a <__swbuf_r+0xb6>
+800017ce:	481c                	lw	a5,16(s0)
+800017d0:	4008                	lw	a0,0(s0)
+800017d2:	0ff97993          	andi	s3,s2,255
+800017d6:	0ff97913          	andi	s2,s2,255
+800017da:	8d1d                	sub	a0,a0,a5
+800017dc:	485c                	lw	a5,20(s0)
+800017de:	00f54663          	blt	a0,a5,800017ea <__swbuf_r+0x56>
+800017e2:	85a2                	mv	a1,s0
+800017e4:	8526                	mv	a0,s1
+800017e6:	2cdd                	jal	80001adc <_fflush_r>
+800017e8:	e52d                	bnez	a0,80001852 <__swbuf_r+0xbe>
+800017ea:	441c                	lw	a5,8(s0)
+800017ec:	0505                	addi	a0,a0,1
+800017ee:	17fd                	addi	a5,a5,-1
+800017f0:	c41c                	sw	a5,8(s0)
+800017f2:	401c                	lw	a5,0(s0)
+800017f4:	00178713          	addi	a4,a5,1
+800017f8:	c018                	sw	a4,0(s0)
+800017fa:	01378023          	sb	s3,0(a5)
+800017fe:	485c                	lw	a5,20(s0)
+80001800:	00a78963          	beq	a5,a0,80001812 <__swbuf_r+0x7e>
+80001804:	00c45783          	lhu	a5,12(s0)
+80001808:	8b85                	andi	a5,a5,1
+8000180a:	cb81                	beqz	a5,8000181a <__swbuf_r+0x86>
+8000180c:	47a9                	li	a5,10
+8000180e:	00f91663          	bne	s2,a5,8000181a <__swbuf_r+0x86>
+80001812:	85a2                	mv	a1,s0
+80001814:	8526                	mv	a0,s1
+80001816:	24d9                	jal	80001adc <_fflush_r>
+80001818:	ed0d                	bnez	a0,80001852 <__swbuf_r+0xbe>
+8000181a:	40f2                	lw	ra,28(sp)
+8000181c:	4462                	lw	s0,24(sp)
+8000181e:	854a                	mv	a0,s2
+80001820:	44d2                	lw	s1,20(sp)
+80001822:	4942                	lw	s2,16(sp)
+80001824:	49b2                	lw	s3,12(sp)
+80001826:	6105                	addi	sp,sp,32
+80001828:	8082                	ret
+8000182a:	00000797          	auipc	a5,0x0
+8000182e:	7a278793          	addi	a5,a5,1954 # 80001fcc <__sf_fake_stdout>
+80001832:	00f41463          	bne	s0,a5,8000183a <__swbuf_r+0xa6>
+80001836:	4480                	lw	s0,8(s1)
+80001838:	b759                	j	800017be <__swbuf_r+0x2a>
+8000183a:	00000797          	auipc	a5,0x0
+8000183e:	75278793          	addi	a5,a5,1874 # 80001f8c <__sf_fake_stderr>
+80001842:	f6f41ee3          	bne	s0,a5,800017be <__swbuf_r+0x2a>
+80001846:	44c0                	lw	s0,12(s1)
+80001848:	bf9d                	j	800017be <__swbuf_r+0x2a>
+8000184a:	85a2                	mv	a1,s0
+8000184c:	8526                	mv	a0,s1
+8000184e:	2021                	jal	80001856 <__swsetup_r>
+80001850:	dd3d                	beqz	a0,800017ce <__swbuf_r+0x3a>
+80001852:	597d                	li	s2,-1
+80001854:	b7d9                	j	8000181a <__swbuf_r+0x86>
+
+80001856 <__swsetup_r>:
+__swsetup_r():
+80001856:	1141                	addi	sp,sp,-16
+80001858:	00002797          	auipc	a5,0x2
+8000185c:	7b078793          	addi	a5,a5,1968 # 80004008 <_impure_ptr>
+80001860:	c226                	sw	s1,4(sp)
+80001862:	4384                	lw	s1,0(a5)
+80001864:	c422                	sw	s0,8(sp)
+80001866:	c04a                	sw	s2,0(sp)
+80001868:	c606                	sw	ra,12(sp)
+8000186a:	892a                	mv	s2,a0
+8000186c:	842e                	mv	s0,a1
+8000186e:	c491                	beqz	s1,8000187a <__swsetup_r+0x24>
+80001870:	4c9c                	lw	a5,24(s1)
+80001872:	e781                	bnez	a5,8000187a <__swsetup_r+0x24>
+80001874:	8526                	mv	a0,s1
+80001876:	d3cff0ef          	jal	ra,80000db2 <__sinit>
+8000187a:	00000797          	auipc	a5,0x0
+8000187e:	73278793          	addi	a5,a5,1842 # 80001fac <__sf_fake_stdin>
+80001882:	02f41c63          	bne	s0,a5,800018ba <__swsetup_r+0x64>
+80001886:	40c0                	lw	s0,4(s1)
+80001888:	00c41703          	lh	a4,12(s0)
+8000188c:	01071793          	slli	a5,a4,0x10
+80001890:	83c1                	srli	a5,a5,0x10
+80001892:	0087f693          	andi	a3,a5,8
+80001896:	eeb5                	bnez	a3,80001912 <__swsetup_r+0xbc>
+80001898:	0107f693          	andi	a3,a5,16
+8000189c:	ee9d                	bnez	a3,800018da <__swsetup_r+0x84>
+8000189e:	47a5                	li	a5,9
+800018a0:	00f92023          	sw	a5,0(s2)
+800018a4:	04076713          	ori	a4,a4,64
+800018a8:	00e41623          	sh	a4,12(s0)
+800018ac:	557d                	li	a0,-1
+800018ae:	40b2                	lw	ra,12(sp)
+800018b0:	4422                	lw	s0,8(sp)
+800018b2:	4492                	lw	s1,4(sp)
+800018b4:	4902                	lw	s2,0(sp)
+800018b6:	0141                	addi	sp,sp,16
+800018b8:	8082                	ret
+800018ba:	00000797          	auipc	a5,0x0
+800018be:	71278793          	addi	a5,a5,1810 # 80001fcc <__sf_fake_stdout>
+800018c2:	00f41463          	bne	s0,a5,800018ca <__swsetup_r+0x74>
+800018c6:	4480                	lw	s0,8(s1)
+800018c8:	b7c1                	j	80001888 <__swsetup_r+0x32>
+800018ca:	00000797          	auipc	a5,0x0
+800018ce:	6c278793          	addi	a5,a5,1730 # 80001f8c <__sf_fake_stderr>
+800018d2:	faf41be3          	bne	s0,a5,80001888 <__swsetup_r+0x32>
+800018d6:	44c0                	lw	s0,12(s1)
+800018d8:	bf45                	j	80001888 <__swsetup_r+0x32>
+800018da:	8b91                	andi	a5,a5,4
+800018dc:	c78d                	beqz	a5,80001906 <__swsetup_r+0xb0>
+800018de:	584c                	lw	a1,52(s0)
+800018e0:	c989                	beqz	a1,800018f2 <__swsetup_r+0x9c>
+800018e2:	04440793          	addi	a5,s0,68
+800018e6:	00f58463          	beq	a1,a5,800018ee <__swsetup_r+0x98>
+800018ea:	854a                	mv	a0,s2
+800018ec:	2e61                	jal	80001c84 <_free_r>
+800018ee:	02042a23          	sw	zero,52(s0)
+800018f2:	00c45783          	lhu	a5,12(s0)
+800018f6:	00042223          	sw	zero,4(s0)
+800018fa:	fdb7f793          	andi	a5,a5,-37
+800018fe:	00f41623          	sh	a5,12(s0)
+80001902:	481c                	lw	a5,16(s0)
+80001904:	c01c                	sw	a5,0(s0)
+80001906:	00c45783          	lhu	a5,12(s0)
+8000190a:	0087e793          	ori	a5,a5,8
+8000190e:	00f41623          	sh	a5,12(s0)
+80001912:	481c                	lw	a5,16(s0)
+80001914:	ef81                	bnez	a5,8000192c <__swsetup_r+0xd6>
+80001916:	00c45783          	lhu	a5,12(s0)
+8000191a:	20000713          	li	a4,512
+8000191e:	2807f793          	andi	a5,a5,640
+80001922:	00e78563          	beq	a5,a4,8000192c <__swsetup_r+0xd6>
+80001926:	85a2                	mv	a1,s0
+80001928:	854a                	mv	a0,s2
+8000192a:	2c79                	jal	80001bc8 <__smakebuf_r>
+8000192c:	00c45783          	lhu	a5,12(s0)
+80001930:	0017f713          	andi	a4,a5,1
+80001934:	c705                	beqz	a4,8000195c <__swsetup_r+0x106>
+80001936:	485c                	lw	a5,20(s0)
+80001938:	00042423          	sw	zero,8(s0)
+8000193c:	40f007b3          	neg	a5,a5
+80001940:	cc1c                	sw	a5,24(s0)
+80001942:	481c                	lw	a5,16(s0)
+80001944:	4501                	li	a0,0
+80001946:	f7a5                	bnez	a5,800018ae <__swsetup_r+0x58>
+80001948:	00c41783          	lh	a5,12(s0)
+8000194c:	0807f713          	andi	a4,a5,128
+80001950:	df39                	beqz	a4,800018ae <__swsetup_r+0x58>
+80001952:	0407e793          	ori	a5,a5,64
+80001956:	00f41623          	sh	a5,12(s0)
+8000195a:	bf89                	j	800018ac <__swsetup_r+0x56>
+8000195c:	8b89                	andi	a5,a5,2
+8000195e:	4701                	li	a4,0
+80001960:	e391                	bnez	a5,80001964 <__swsetup_r+0x10e>
+80001962:	4858                	lw	a4,20(s0)
+80001964:	c418                	sw	a4,8(s0)
+80001966:	bff1                	j	80001942 <__swsetup_r+0xec>
+
+80001968 <_close_r>:
+_close_r():
+80001968:	1141                	addi	sp,sp,-16
+8000196a:	c422                	sw	s0,8(sp)
+8000196c:	842a                	mv	s0,a0
+8000196e:	852e                	mv	a0,a1
+80001970:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001974:	c606                	sw	ra,12(sp)
+80001976:	f13fe0ef          	jal	ra,80000888 <_close>
+8000197a:	57fd                	li	a5,-1
+8000197c:	00f51763          	bne	a0,a5,8000198a <_close_r+0x22>
+80001980:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001984:	439c                	lw	a5,0(a5)
+80001986:	c391                	beqz	a5,8000198a <_close_r+0x22>
+80001988:	c01c                	sw	a5,0(s0)
+8000198a:	40b2                	lw	ra,12(sp)
+8000198c:	4422                	lw	s0,8(sp)
+8000198e:	0141                	addi	sp,sp,16
+80001990:	8082                	ret
+
+80001992 <__sflush_r>:
+__sflush_r():
+80001992:	00c5d783          	lhu	a5,12(a1)
+80001996:	1101                	addi	sp,sp,-32
+80001998:	cc22                	sw	s0,24(sp)
+8000199a:	ca26                	sw	s1,20(sp)
+8000199c:	ce06                	sw	ra,28(sp)
+8000199e:	c84a                	sw	s2,16(sp)
+800019a0:	c64e                	sw	s3,12(sp)
+800019a2:	0087f713          	andi	a4,a5,8
+800019a6:	84aa                	mv	s1,a0
+800019a8:	842e                	mv	s0,a1
+800019aa:	e765                	bnez	a4,80001a92 <__sflush_r+0x100>
+800019ac:	41d8                	lw	a4,4(a1)
+800019ae:	00e04763          	bgtz	a4,800019bc <__sflush_r+0x2a>
+800019b2:	41b8                	lw	a4,64(a1)
+800019b4:	00e04463          	bgtz	a4,800019bc <__sflush_r+0x2a>
+800019b8:	4501                	li	a0,0
+800019ba:	a0c1                	j	80001a7a <__sflush_r+0xe8>
+800019bc:	5458                	lw	a4,44(s0)
+800019be:	df6d                	beqz	a4,800019b8 <__sflush_r+0x26>
+800019c0:	0004a903          	lw	s2,0(s1)
+800019c4:	01379693          	slli	a3,a5,0x13
+800019c8:	0004a023          	sw	zero,0(s1)
+800019cc:	0606de63          	bgez	a3,80001a48 <__sflush_r+0xb6>
+800019d0:	4868                	lw	a0,84(s0)
+800019d2:	00c45783          	lhu	a5,12(s0)
+800019d6:	8b91                	andi	a5,a5,4
+800019d8:	c799                	beqz	a5,800019e6 <__sflush_r+0x54>
+800019da:	405c                	lw	a5,4(s0)
+800019dc:	8d1d                	sub	a0,a0,a5
+800019de:	585c                	lw	a5,52(s0)
+800019e0:	c399                	beqz	a5,800019e6 <__sflush_r+0x54>
+800019e2:	403c                	lw	a5,64(s0)
+800019e4:	8d1d                	sub	a0,a0,a5
+800019e6:	545c                	lw	a5,44(s0)
+800019e8:	500c                	lw	a1,32(s0)
+800019ea:	862a                	mv	a2,a0
+800019ec:	4681                	li	a3,0
+800019ee:	8526                	mv	a0,s1
+800019f0:	9782                	jalr	a5
+800019f2:	57fd                	li	a5,-1
+800019f4:	00c45703          	lhu	a4,12(s0)
+800019f8:	00f51d63          	bne	a0,a5,80001a12 <__sflush_r+0x80>
+800019fc:	4094                	lw	a3,0(s1)
+800019fe:	47f5                	li	a5,29
+80001a00:	08d7e463          	bltu	a5,a3,80001a88 <__sflush_r+0xf6>
+80001a04:	204007b7          	lui	a5,0x20400
+80001a08:	0785                	addi	a5,a5,1
+80001a0a:	00d7d7b3          	srl	a5,a5,a3
+80001a0e:	8b85                	andi	a5,a5,1
+80001a10:	cfa5                	beqz	a5,80001a88 <__sflush_r+0xf6>
+80001a12:	481c                	lw	a5,16(s0)
+80001a14:	00042223          	sw	zero,4(s0)
+80001a18:	c01c                	sw	a5,0(s0)
+80001a1a:	01371793          	slli	a5,a4,0x13
+80001a1e:	0007d863          	bgez	a5,80001a2e <__sflush_r+0x9c>
+80001a22:	57fd                	li	a5,-1
+80001a24:	00f51463          	bne	a0,a5,80001a2c <__sflush_r+0x9a>
+80001a28:	409c                	lw	a5,0(s1)
+80001a2a:	e391                	bnez	a5,80001a2e <__sflush_r+0x9c>
+80001a2c:	c868                	sw	a0,84(s0)
+80001a2e:	584c                	lw	a1,52(s0)
+80001a30:	0124a023          	sw	s2,0(s1)
+80001a34:	d1d1                	beqz	a1,800019b8 <__sflush_r+0x26>
+80001a36:	04440793          	addi	a5,s0,68
+80001a3a:	00f58463          	beq	a1,a5,80001a42 <__sflush_r+0xb0>
+80001a3e:	8526                	mv	a0,s1
+80001a40:	2491                	jal	80001c84 <_free_r>
+80001a42:	02042a23          	sw	zero,52(s0)
+80001a46:	bf8d                	j	800019b8 <__sflush_r+0x26>
+80001a48:	500c                	lw	a1,32(s0)
+80001a4a:	4685                	li	a3,1
+80001a4c:	4601                	li	a2,0
+80001a4e:	8526                	mv	a0,s1
+80001a50:	9702                	jalr	a4
+80001a52:	57fd                	li	a5,-1
+80001a54:	f6f51fe3          	bne	a0,a5,800019d2 <__sflush_r+0x40>
+80001a58:	409c                	lw	a5,0(s1)
+80001a5a:	dfa5                	beqz	a5,800019d2 <__sflush_r+0x40>
+80001a5c:	4775                	li	a4,29
+80001a5e:	00e78563          	beq	a5,a4,80001a68 <__sflush_r+0xd6>
+80001a62:	4759                	li	a4,22
+80001a64:	00e79563          	bne	a5,a4,80001a6e <__sflush_r+0xdc>
+80001a68:	0124a023          	sw	s2,0(s1)
+80001a6c:	b7b1                	j	800019b8 <__sflush_r+0x26>
+80001a6e:	00c45783          	lhu	a5,12(s0)
+80001a72:	0407e793          	ori	a5,a5,64
+80001a76:	00f41623          	sh	a5,12(s0)
+80001a7a:	40f2                	lw	ra,28(sp)
+80001a7c:	4462                	lw	s0,24(sp)
+80001a7e:	44d2                	lw	s1,20(sp)
+80001a80:	4942                	lw	s2,16(sp)
+80001a82:	49b2                	lw	s3,12(sp)
+80001a84:	6105                	addi	sp,sp,32
+80001a86:	8082                	ret
+80001a88:	04076713          	ori	a4,a4,64
+80001a8c:	00e41623          	sh	a4,12(s0)
+80001a90:	b7ed                	j	80001a7a <__sflush_r+0xe8>
+80001a92:	0105a983          	lw	s3,16(a1)
+80001a96:	f20981e3          	beqz	s3,800019b8 <__sflush_r+0x26>
+80001a9a:	0005a903          	lw	s2,0(a1)
+80001a9e:	8b8d                	andi	a5,a5,3
+80001aa0:	0135a023          	sw	s3,0(a1)
+80001aa4:	41390933          	sub	s2,s2,s3
+80001aa8:	4701                	li	a4,0
+80001aaa:	e391                	bnez	a5,80001aae <__sflush_r+0x11c>
+80001aac:	49d8                	lw	a4,20(a1)
+80001aae:	c418                	sw	a4,8(s0)
+80001ab0:	f12054e3          	blez	s2,800019b8 <__sflush_r+0x26>
+80001ab4:	541c                	lw	a5,40(s0)
+80001ab6:	500c                	lw	a1,32(s0)
+80001ab8:	86ca                	mv	a3,s2
+80001aba:	864e                	mv	a2,s3
+80001abc:	8526                	mv	a0,s1
+80001abe:	9782                	jalr	a5
+80001ac0:	00a04a63          	bgtz	a0,80001ad4 <__sflush_r+0x142>
+80001ac4:	00c45783          	lhu	a5,12(s0)
+80001ac8:	557d                	li	a0,-1
+80001aca:	0407e793          	ori	a5,a5,64
+80001ace:	00f41623          	sh	a5,12(s0)
+80001ad2:	b765                	j	80001a7a <__sflush_r+0xe8>
+80001ad4:	99aa                	add	s3,s3,a0
+80001ad6:	40a90933          	sub	s2,s2,a0
+80001ada:	bfd9                	j	80001ab0 <__sflush_r+0x11e>
+
+80001adc <_fflush_r>:
+_fflush_r():
+80001adc:	499c                	lw	a5,16(a1)
+80001ade:	c3a5                	beqz	a5,80001b3e <_fflush_r+0x62>
+80001ae0:	1101                	addi	sp,sp,-32
+80001ae2:	cc22                	sw	s0,24(sp)
+80001ae4:	ce06                	sw	ra,28(sp)
+80001ae6:	842a                	mv	s0,a0
+80001ae8:	c519                	beqz	a0,80001af6 <_fflush_r+0x1a>
+80001aea:	4d1c                	lw	a5,24(a0)
+80001aec:	e789                	bnez	a5,80001af6 <_fflush_r+0x1a>
+80001aee:	c62e                	sw	a1,12(sp)
+80001af0:	ac2ff0ef          	jal	ra,80000db2 <__sinit>
+80001af4:	45b2                	lw	a1,12(sp)
+80001af6:	00000797          	auipc	a5,0x0
+80001afa:	4b678793          	addi	a5,a5,1206 # 80001fac <__sf_fake_stdin>
+80001afe:	00f59b63          	bne	a1,a5,80001b14 <_fflush_r+0x38>
+80001b02:	404c                	lw	a1,4(s0)
+80001b04:	00c59783          	lh	a5,12(a1)
+80001b08:	c795                	beqz	a5,80001b34 <_fflush_r+0x58>
+80001b0a:	8522                	mv	a0,s0
+80001b0c:	4462                	lw	s0,24(sp)
+80001b0e:	40f2                	lw	ra,28(sp)
+80001b10:	6105                	addi	sp,sp,32
+80001b12:	b541                	j	80001992 <__sflush_r>
+80001b14:	00000797          	auipc	a5,0x0
+80001b18:	4b878793          	addi	a5,a5,1208 # 80001fcc <__sf_fake_stdout>
+80001b1c:	00f59463          	bne	a1,a5,80001b24 <_fflush_r+0x48>
+80001b20:	440c                	lw	a1,8(s0)
+80001b22:	b7cd                	j	80001b04 <_fflush_r+0x28>
+80001b24:	00000797          	auipc	a5,0x0
+80001b28:	46878793          	addi	a5,a5,1128 # 80001f8c <__sf_fake_stderr>
+80001b2c:	fcf59ce3          	bne	a1,a5,80001b04 <_fflush_r+0x28>
+80001b30:	444c                	lw	a1,12(s0)
+80001b32:	bfc9                	j	80001b04 <_fflush_r+0x28>
+80001b34:	40f2                	lw	ra,28(sp)
+80001b36:	4462                	lw	s0,24(sp)
+80001b38:	4501                	li	a0,0
+80001b3a:	6105                	addi	sp,sp,32
+80001b3c:	8082                	ret
+80001b3e:	4501                	li	a0,0
+80001b40:	8082                	ret
+
+80001b42 <_lseek_r>:
+_lseek_r():
+80001b42:	1141                	addi	sp,sp,-16
+80001b44:	c422                	sw	s0,8(sp)
+80001b46:	842a                	mv	s0,a0
+80001b48:	852e                	mv	a0,a1
+80001b4a:	85b2                	mv	a1,a2
+80001b4c:	8636                	mv	a2,a3
+80001b4e:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001b52:	c606                	sw	ra,12(sp)
+80001b54:	d55fe0ef          	jal	ra,800008a8 <_lseek>
+80001b58:	57fd                	li	a5,-1
+80001b5a:	00f51763          	bne	a0,a5,80001b68 <_lseek_r+0x26>
+80001b5e:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001b62:	439c                	lw	a5,0(a5)
+80001b64:	c391                	beqz	a5,80001b68 <_lseek_r+0x26>
+80001b66:	c01c                	sw	a5,0(s0)
+80001b68:	40b2                	lw	ra,12(sp)
+80001b6a:	4422                	lw	s0,8(sp)
+80001b6c:	0141                	addi	sp,sp,16
+80001b6e:	8082                	ret
+
+80001b70 <__swhatbuf_r>:
+__swhatbuf_r():
+80001b70:	7119                	addi	sp,sp,-128
+80001b72:	daa6                	sw	s1,116(sp)
+80001b74:	84ae                	mv	s1,a1
+80001b76:	00e59583          	lh	a1,14(a1)
+80001b7a:	dca2                	sw	s0,120(sp)
+80001b7c:	de86                	sw	ra,124(sp)
+80001b7e:	8432                	mv	s0,a2
+80001b80:	0005dc63          	bgez	a1,80001b98 <__swhatbuf_r+0x28>
+80001b84:	00c4d783          	lhu	a5,12(s1)
+80001b88:	0006a023          	sw	zero,0(a3)
+80001b8c:	0807f793          	andi	a5,a5,128
+80001b90:	e39d                	bnez	a5,80001bb6 <__swhatbuf_r+0x46>
+80001b92:	40000793          	li	a5,1024
+80001b96:	a015                	j	80001bba <__swhatbuf_r+0x4a>
+80001b98:	0830                	addi	a2,sp,24
+80001b9a:	c636                	sw	a3,12(sp)
+80001b9c:	2a6d                	jal	80001d56 <_fstat_r>
+80001b9e:	46b2                	lw	a3,12(sp)
+80001ba0:	fe0542e3          	bltz	a0,80001b84 <__swhatbuf_r+0x14>
+80001ba4:	4772                	lw	a4,28(sp)
+80001ba6:	67bd                	lui	a5,0xf
+80001ba8:	8ff9                	and	a5,a5,a4
+80001baa:	7779                	lui	a4,0xffffe
+80001bac:	97ba                	add	a5,a5,a4
+80001bae:	0017b793          	seqz	a5,a5
+80001bb2:	c29c                	sw	a5,0(a3)
+80001bb4:	bff9                	j	80001b92 <__swhatbuf_r+0x22>
+80001bb6:	04000793          	li	a5,64
+80001bba:	c01c                	sw	a5,0(s0)
+80001bbc:	50f6                	lw	ra,124(sp)
+80001bbe:	5466                	lw	s0,120(sp)
+80001bc0:	54d6                	lw	s1,116(sp)
+80001bc2:	4501                	li	a0,0
+80001bc4:	6109                	addi	sp,sp,128
+80001bc6:	8082                	ret
+
+80001bc8 <__smakebuf_r>:
+__smakebuf_r():
+80001bc8:	00c5d783          	lhu	a5,12(a1)
+80001bcc:	1101                	addi	sp,sp,-32
+80001bce:	cc22                	sw	s0,24(sp)
+80001bd0:	ce06                	sw	ra,28(sp)
+80001bd2:	ca26                	sw	s1,20(sp)
+80001bd4:	c84a                	sw	s2,16(sp)
+80001bd6:	8b89                	andi	a5,a5,2
+80001bd8:	842e                	mv	s0,a1
+80001bda:	cf89                	beqz	a5,80001bf4 <__smakebuf_r+0x2c>
+80001bdc:	04740793          	addi	a5,s0,71
+80001be0:	c01c                	sw	a5,0(s0)
+80001be2:	c81c                	sw	a5,16(s0)
+80001be4:	4785                	li	a5,1
+80001be6:	c85c                	sw	a5,20(s0)
+80001be8:	40f2                	lw	ra,28(sp)
+80001bea:	4462                	lw	s0,24(sp)
+80001bec:	44d2                	lw	s1,20(sp)
+80001bee:	4942                	lw	s2,16(sp)
+80001bf0:	6105                	addi	sp,sp,32
+80001bf2:	8082                	ret
+80001bf4:	0074                	addi	a3,sp,12
+80001bf6:	0030                	addi	a2,sp,8
+80001bf8:	84aa                	mv	s1,a0
+80001bfa:	3f9d                	jal	80001b70 <__swhatbuf_r>
+80001bfc:	45a2                	lw	a1,8(sp)
+80001bfe:	892a                	mv	s2,a0
+80001c00:	8526                	mv	a0,s1
+80001c02:	b24ff0ef          	jal	ra,80000f26 <_malloc_r>
+80001c06:	ed01                	bnez	a0,80001c1e <__smakebuf_r+0x56>
+80001c08:	00c41783          	lh	a5,12(s0)
+80001c0c:	2007f713          	andi	a4,a5,512
+80001c10:	ff61                	bnez	a4,80001be8 <__smakebuf_r+0x20>
+80001c12:	9bf1                	andi	a5,a5,-4
+80001c14:	0027e793          	ori	a5,a5,2
+80001c18:	00f41623          	sh	a5,12(s0)
+80001c1c:	b7c1                	j	80001bdc <__smakebuf_r+0x14>
+80001c1e:	fffff797          	auipc	a5,0xfffff
+80001c22:	14678793          	addi	a5,a5,326 # 80000d64 <_cleanup_r>
+80001c26:	d49c                	sw	a5,40(s1)
+80001c28:	00c45783          	lhu	a5,12(s0)
+80001c2c:	c008                	sw	a0,0(s0)
+80001c2e:	c808                	sw	a0,16(s0)
+80001c30:	0807e793          	ori	a5,a5,128
+80001c34:	00f41623          	sh	a5,12(s0)
+80001c38:	47a2                	lw	a5,8(sp)
+80001c3a:	c85c                	sw	a5,20(s0)
+80001c3c:	47b2                	lw	a5,12(sp)
+80001c3e:	cf89                	beqz	a5,80001c58 <__smakebuf_r+0x90>
+80001c40:	00e41583          	lh	a1,14(s0)
+80001c44:	8526                	mv	a0,s1
+80001c46:	2a35                	jal	80001d82 <_isatty_r>
+80001c48:	c901                	beqz	a0,80001c58 <__smakebuf_r+0x90>
+80001c4a:	00c45783          	lhu	a5,12(s0)
+80001c4e:	9bf1                	andi	a5,a5,-4
+80001c50:	0017e793          	ori	a5,a5,1
+80001c54:	00f41623          	sh	a5,12(s0)
+80001c58:	00c45783          	lhu	a5,12(s0)
+80001c5c:	00f96933          	or	s2,s2,a5
+80001c60:	01241623          	sh	s2,12(s0)
+80001c64:	b751                	j	80001be8 <__smakebuf_r+0x20>
+
+80001c66 <memchr>:
+memchr():
+80001c66:	0ff5f593          	andi	a1,a1,255
+80001c6a:	962a                	add	a2,a2,a0
+80001c6c:	00c51463          	bne	a0,a2,80001c74 <memchr+0xe>
+80001c70:	4501                	li	a0,0
+80001c72:	8082                	ret
+80001c74:	00054783          	lbu	a5,0(a0)
+80001c78:	feb78de3          	beq	a5,a1,80001c72 <memchr+0xc>
+80001c7c:	0505                	addi	a0,a0,1
+80001c7e:	b7fd                	j	80001c6c <memchr+0x6>
+
+80001c80 <__malloc_lock>:
+__malloc_lock():
+80001c80:	8082                	ret
+
+80001c82 <__malloc_unlock>:
+__malloc_unlock():
+80001c82:	8082                	ret
+
+80001c84 <_free_r>:
+_free_r():
+80001c84:	c1cd                	beqz	a1,80001d26 <_free_r+0xa2>
+80001c86:	ffc5a783          	lw	a5,-4(a1)
+80001c8a:	1141                	addi	sp,sp,-16
+80001c8c:	c422                	sw	s0,8(sp)
+80001c8e:	c606                	sw	ra,12(sp)
+80001c90:	c226                	sw	s1,4(sp)
+80001c92:	ffc58413          	addi	s0,a1,-4
+80001c96:	0007d363          	bgez	a5,80001c9c <_free_r+0x18>
+80001c9a:	943e                	add	s0,s0,a5
+80001c9c:	84aa                	mv	s1,a0
+80001c9e:	37cd                	jal	80001c80 <__malloc_lock>
+80001ca0:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+80001ca4:	439c                	lw	a5,0(a5)
+80001ca6:	eb99                	bnez	a5,80001cbc <_free_r+0x38>
+80001ca8:	00042223          	sw	zero,4(s0)
+80001cac:	8881a623          	sw	s0,-1908(gp) # 8000408c <__malloc_free_list>
+80001cb0:	4422                	lw	s0,8(sp)
+80001cb2:	40b2                	lw	ra,12(sp)
+80001cb4:	8526                	mv	a0,s1
+80001cb6:	4492                	lw	s1,4(sp)
+80001cb8:	0141                	addi	sp,sp,16
+80001cba:	b7e1                	j	80001c82 <__malloc_unlock>
+80001cbc:	00f47e63          	bgeu	s0,a5,80001cd8 <_free_r+0x54>
+80001cc0:	4014                	lw	a3,0(s0)
+80001cc2:	00d40733          	add	a4,s0,a3
+80001cc6:	00e79663          	bne	a5,a4,80001cd2 <_free_r+0x4e>
+80001cca:	4398                	lw	a4,0(a5)
+80001ccc:	43dc                	lw	a5,4(a5)
+80001cce:	9736                	add	a4,a4,a3
+80001cd0:	c018                	sw	a4,0(s0)
+80001cd2:	c05c                	sw	a5,4(s0)
+80001cd4:	bfe1                	j	80001cac <_free_r+0x28>
+80001cd6:	87ba                	mv	a5,a4
+80001cd8:	43d8                	lw	a4,4(a5)
+80001cda:	c319                	beqz	a4,80001ce0 <_free_r+0x5c>
+80001cdc:	fee47de3          	bgeu	s0,a4,80001cd6 <_free_r+0x52>
+80001ce0:	4394                	lw	a3,0(a5)
+80001ce2:	00d78633          	add	a2,a5,a3
+80001ce6:	00861f63          	bne	a2,s0,80001d04 <_free_r+0x80>
+80001cea:	4010                	lw	a2,0(s0)
+80001cec:	96b2                	add	a3,a3,a2
+80001cee:	c394                	sw	a3,0(a5)
+80001cf0:	00d78633          	add	a2,a5,a3
+80001cf4:	fac71ee3          	bne	a4,a2,80001cb0 <_free_r+0x2c>
+80001cf8:	4310                	lw	a2,0(a4)
+80001cfa:	4358                	lw	a4,4(a4)
+80001cfc:	96b2                	add	a3,a3,a2
+80001cfe:	c394                	sw	a3,0(a5)
+80001d00:	c3d8                	sw	a4,4(a5)
+80001d02:	b77d                	j	80001cb0 <_free_r+0x2c>
+80001d04:	00c47563          	bgeu	s0,a2,80001d0e <_free_r+0x8a>
+80001d08:	47b1                	li	a5,12
+80001d0a:	c09c                	sw	a5,0(s1)
+80001d0c:	b755                	j	80001cb0 <_free_r+0x2c>
+80001d0e:	4010                	lw	a2,0(s0)
+80001d10:	00c406b3          	add	a3,s0,a2
+80001d14:	00d71663          	bne	a4,a3,80001d20 <_free_r+0x9c>
+80001d18:	4314                	lw	a3,0(a4)
+80001d1a:	4358                	lw	a4,4(a4)
+80001d1c:	96b2                	add	a3,a3,a2
+80001d1e:	c014                	sw	a3,0(s0)
+80001d20:	c058                	sw	a4,4(s0)
+80001d22:	c3c0                	sw	s0,4(a5)
+80001d24:	b771                	j	80001cb0 <_free_r+0x2c>
+80001d26:	8082                	ret
+
+80001d28 <_read_r>:
+_read_r():
+80001d28:	1141                	addi	sp,sp,-16
+80001d2a:	c422                	sw	s0,8(sp)
+80001d2c:	842a                	mv	s0,a0
+80001d2e:	852e                	mv	a0,a1
+80001d30:	85b2                	mv	a1,a2
+80001d32:	8636                	mv	a2,a3
+80001d34:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d38:	c606                	sw	ra,12(sp)
+80001d3a:	b77fe0ef          	jal	ra,800008b0 <_read>
+80001d3e:	57fd                	li	a5,-1
+80001d40:	00f51763          	bne	a0,a5,80001d4e <_read_r+0x26>
+80001d44:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d48:	439c                	lw	a5,0(a5)
+80001d4a:	c391                	beqz	a5,80001d4e <_read_r+0x26>
+80001d4c:	c01c                	sw	a5,0(s0)
+80001d4e:	40b2                	lw	ra,12(sp)
+80001d50:	4422                	lw	s0,8(sp)
+80001d52:	0141                	addi	sp,sp,16
+80001d54:	8082                	ret
+
+80001d56 <_fstat_r>:
+_fstat_r():
+80001d56:	1141                	addi	sp,sp,-16
+80001d58:	c422                	sw	s0,8(sp)
+80001d5a:	842a                	mv	s0,a0
+80001d5c:	852e                	mv	a0,a1
+80001d5e:	85b2                	mv	a1,a2
+80001d60:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d64:	c606                	sw	ra,12(sp)
+80001d66:	b27fe0ef          	jal	ra,8000088c <_fstat>
+80001d6a:	57fd                	li	a5,-1
+80001d6c:	00f51763          	bne	a0,a5,80001d7a <_fstat_r+0x24>
+80001d70:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d74:	439c                	lw	a5,0(a5)
+80001d76:	c391                	beqz	a5,80001d7a <_fstat_r+0x24>
+80001d78:	c01c                	sw	a5,0(s0)
+80001d7a:	40b2                	lw	ra,12(sp)
+80001d7c:	4422                	lw	s0,8(sp)
+80001d7e:	0141                	addi	sp,sp,16
+80001d80:	8082                	ret
+
+80001d82 <_isatty_r>:
+_isatty_r():
+80001d82:	1141                	addi	sp,sp,-16
+80001d84:	c422                	sw	s0,8(sp)
+80001d86:	842a                	mv	s0,a0
+80001d88:	852e                	mv	a0,a1
+80001d8a:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d8e:	c606                	sw	ra,12(sp)
+80001d90:	af3fe0ef          	jal	ra,80000882 <_isatty>
+80001d94:	57fd                	li	a5,-1
+80001d96:	00f51763          	bne	a0,a5,80001da4 <_isatty_r+0x22>
+80001d9a:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d9e:	439c                	lw	a5,0(a5)
+80001da0:	c391                	beqz	a5,80001da4 <_isatty_r+0x22>
+80001da2:	c01c                	sw	a5,0(s0)
+80001da4:	40b2                	lw	ra,12(sp)
+80001da6:	4422                	lw	s0,8(sp)
+80001da8:	0141                	addi	sp,sp,16
+80001daa:	8082                	ret
+80001dac:	0000                	unimp
+	...
+
+80001db0 <local_irq_handler_table>:
+80001db0:	083c 8000 083a 8000 083e 8000 0852 8000     <...:...>...R...
+80001dc0:	084c 8000 084c 8000 084c 8000 084c 8000     L...L...L...L...
+80001dd0:	0840 8000 0842 8000 0844 8000 0846 8000     @...B...D...F...
+80001de0:	0848 8000 084a 8000 084e 8000 0850 8000     H...J...N...P...
+80001df0:	0a0d 6e49 6574 6e72 6c61 5320 7379 6574     ..Internal Syste
+80001e00:	206d 6954 656d 2072 6e49 6574 7272 7075     m Timer Interrup
+80001e10:	2074 6f43 6e75 6574 2072 203d 6425 0000     t Counter = %d..
+80001e20:	0a0d 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ..**************
+80001e30:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e40:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e50:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e60:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e70:	0a0d 2a0a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ...*************
+80001e80:	2a2a 2a2a 2a2a 202a 2020 4d20 2d69 2056     *******    Mi-V 
+80001e90:	7953 7473 6d65 5420 6d69 7265 4220 696c     System Timer Bli
+80001ea0:	6b6e 2079 7845 6d61 6c70 2065 2020 2a20     nky Example    *
+80001eb0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ec0:	2a2a 2a2a 2a2a 0a0d 2a0a 2a2a 2a2a 2a2a     ******...*******
+80001ed0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ee0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ef0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001f00:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001f10:	2a2a 2a2a 2a2a 0d2a 0d0a 4f0a 7362 7265     *******....Obser
+80001f20:	6576 7420 6568 4c20 4445 2073 6c62 6e69     ve the LEDs blin
+80001f30:	696b 676e 6f20 206e 6874 2065 6f62 7261     king on the boar
+80001f40:	2e64 5420 6568 4c20 4445 7020 7461 6574     d. The LED patte
+80001f50:	6e72 6320 6168 676e 7365 6520 6576 7972     rn changes every
+80001f60:	7420 6d69 2065 2061 7973 7473 6d65 7420      time a system t
+80001f70:	6d69 7265 6920 746e 7265 7572 7470 6f20     imer interrupt o
+80001f80:	6363 7275 2e73 0a0d 0000 0000               ccurs.......
+
+80001f8c <__sf_fake_stderr>:
+	...
+
+80001fac <__sf_fake_stdin>:
+	...
+
+80001fcc <__sf_fake_stdout>:
+	...
+80001fec:	2d23 2b30 0020 0000 6c68 004c 6665 4567     #-0+ ...hlL.efgE
+80001ffc:	4746 0000 3130 3332 3534 3736 3938 4241     FG..0123456789AB
+8000200c:	4443 4645 0000 0000 3130 3332 3534 3736     CDEF....01234567
+8000201c:	3938 6261 6463 6665 0000 0000 0000 0000     89abcdef........
+8000202c:	0000 0000                                   ....
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.hex
new file mode 100644
index 0000000..2ce9d61
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.hex
@@ -0,0 +1,462 @@
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.lst
new file mode 100644
index 0000000..e8507be
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32-coretimer-timer_interrupt.lst
@@ -0,0 +1,3747 @@
+
+miv-rv32-coretimer-timer_interrupt.elf:     file format elf32-littleriscv
+miv-rv32-coretimer-timer_interrupt.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00001cc0 memsz 0x00002500 flags rwx
+
+Sections:
+Idx Name              Size      VMA       LMA       File off  Algn  Flags
+  0 .entry            000009a0  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text             00001260  800009a0  800009a0  000019a0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata            00000000  80001c00  80001c00  00002cc0  2**4  CONTENTS
+  3 .data             000000c0  80001c00  80001c00  00002c00  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .sbss             00000020  80001cc0  80001cc0  00002cc0  2**4  ALLOC
+  5 .bss              00000020  80001ce0  80001ce0  00002cc0  2**4  ALLOC
+  6 .heap             00000000  80001d00  80001d00  00002cc0  2**4  CONTENTS
+  7 .stack            00000800  80001d00  80001d00  00002cc0  2**4  ALLOC
+  8 .riscv.attributes 0000001c  00000000  00000000  00002cc0  2**0  CONTENTS, READONLY
+  9 .comment          00000051  00000000  00000000  00002cdc  2**0  CONTENTS, READONLY
+ 10 .debug_line       00004687  00000000  00000000  00002d2d  2**0  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_info       00002e5a  00000000  00000000  000073b4  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_abbrev     00000cc2  00000000  00000000  0000a20e  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_aranges    00000398  00000000  00000000  0000aed0  2**3  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_str        0000c434  00000000  00000000  0000b268  2**0  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges     000002e0  00000000  00000000  000176a0  2**3  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro      00003488  00000000  00000000  00017980  2**0  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_frame      00000ce8  00000000  00000000  0001ae08  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+800009a0 l    d  .text	00000000 .text
+80001c00 l    d  .sdata	00000000 .sdata
+80001c00 l    d  .data	00000000 .data
+80001cc0 l    d  .sbss	00000000 .sbss
+80001ce0 l    d  .bss	00000000 .bss
+80001d00 l    d  .heap	00000000 .heap
+80001d00 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_macro	00000000 .debug_macro
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+800009a0 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+80000120 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+800001a8 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+80000230 l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800002b8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000340 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+80000890 l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+800006f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+800003c8 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+80000450 l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800004d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000560 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+800005e8 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+80000670 l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+80000780 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000808 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000918 l       .entry	00000000 generic_restore
+800009f0 l       .text	00000000 ima_cores_setup
+80000a38 l       .text	00000000 vector_address_not_matching
+800009fc l       .text	00000000 generic_reset_handling
+80000ab8 l       .text	00000000 block_copy
+80000a3c l       .text	00000000 initializations
+80000a98 l       .text	00000000 zeroize_block
+80000ae0 l       .text	00000000 block_copy_error
+80000aa8 l       .text	00000000 zeroize_loop
+80000ac8 l       .text	00000000 block_copy_loop
+80000ae4 l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000ae8 l     F .text	00000030 MRV_clear_soft_irq
+80001cc0 l     O .sbss	00000008 g_systick_increment
+80001cc8 l     O .sbss	00000008 g_systick_cmp_value
+80001cd0 l     O .sbss	00000004 d_tick.2196
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+00000000 l    df *ABS*	00000000 hal_irq.c
+80001068 l     F .text	00000024 MRV_enable_interrupts
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_timer.c
+80001cd4 l     O .sbss	00000004 NULL_timer_instance
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80001ab0 l     F .text	0000002c MRV_enable_local_irq
+80001cd8 l     O .sbss	00000004 gpio_pins_state
+80001ce0 g     O .bss	00000008 g_gpio
+00000800 g       *ABS*	00000000 STACK_SIZE
+80002400 g       .sdata	00000000 __global_pointer$
+80001c00 g       *ABS*	00000000 __data_load
+80000ed0  w    F .text	0000001c SysTick_Handler
+8000117c g       .text	00000000 HW_get_8bit_reg_field
+80001cc0 g       .sbss	00000000 __sbss_start
+80000c90 g     F .text	00000088 handle_local_ei_interrupts
+800010b4 g       .text	00000000 HW_set_32bit_reg
+80001c00 g       .sdata	00000000 __sdata_start
+80000fb0  w    F .text	0000001c MSYS_EI4_IRQHandler
+80001154 g       .text	00000000 HW_set_8bit_reg_field
+80000f40  w    F .text	0000001c SUBSYS_IRQHandler
+80000d18 g     F .text	0000015c handle_trap
+00008000 g       *ABS*	00000000 RAM_SIZE
+80001ce8 g     O .bss	00000004 g_core_timer_0
+80001000  w    F .text	0000001c MSYS_EI6_IRQHandler
+800015b0 g     F .text	0000005c TMR_enable_int
+80001038  w    F .text	0000001c SUBSYSR_IRQHandler
+80000f08  w    F .text	0000001c MGECI_IRQHandler
+80001d00 g       .heap	00000000 _heap_end
+80001bc0 g     O .text	00000040 local_irq_handler_table
+8000101c  w    F .text	0000001c MSYS_EI7_IRQHandler
+80001d00 g       .bss	00000000 __bss_end
+80000e74 g     F .text	00000028 _init
+80001144 g       .text	00000000 HW_set_8bit_reg
+8000114c g       .text	00000000 HW_get_8bit_reg
+80000f5c  w    F .text	0000001c MSYS_EI1_IRQHandler
+80001ce0 g       .sbss	00000000 __sbss_end
+800010c4 g       .text	00000000 HW_set_32bit_reg_field
+80002500 g       .stack	00000000 __stack_top
+8000142c g     F .text	00000128 TMR_init
+80001cec g     O .bss	00000008 g_core_uart_0
+80001364 g     F .text	000000c8 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001c00 g     O .data	000000c0 g_message
+800017d4 g     F .text	00000164 GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+80000b18 g     F .text	0000014c handle_m_timer_interrupt
+80001c00 g       *ABS*	00000000 __sdata_load
+80001cc0 g       .data	00000000 __data_end
+800010ec g       .text	00000000 HW_get_32bit_reg_field
+80001660 g     F .text	00000174 GPIO_init
+80000000 g       *ABS*	00000000 RAM_START_ADDRESS
+80001938 g     F .text	00000178 GPIO_get_outputs
+80001ce0 g       .bss	00000000 __bss_start
+8000108c g     F .text	00000028 HAL_enable_interrupts
+80001b34 g     F .text	0000008c main
+80000fcc  w    F .text	0000001c MSYS_EI5_IRQHandler
+80000f24  w    F .text	0000001c MGEUI_IRQHandler
+80001104 g       .text	00000000 HW_get_16bit_reg
+80001c00 g       .sdata	00000000 __sdata_end
+80001d00 g       .heap	00000000 __heap_end
+80000e9c g     F .text	0000001c _fini
+8000110c g       .text	00000000 HW_set_16bit_reg_field
+80000f78  w    F .text	0000001c MSYS_EI2_IRQHandler
+80001d00 g       .stack	00000000 __stack_bottom
+80000eb8  w    F .text	00000018 Software_IRQHandler
+80001554 g     F .text	0000005c TMR_start
+80001d00 g       .heap	00000000 __heap_start
+80001d00 g       .bss	00000000 _end
+80000fe8  w    F .text	00000018 Reserved_IRQHandler
+8000118c g     F .text	000001d8 UART_init
+800010bc g       .text	00000000 HW_get_32bit_reg
+80001054 g     F .text	00000014 _exit
+800010fc g       .text	00000000 HW_set_16bit_reg
+80000f94  w    F .text	0000001c MSYS_EI3_IRQHandler
+80000eec  w    F .text	0000001c External_IRQHandler
+80001c00 g       .data	00000000 __data_start
+80000c64 g     F .text	0000002c handle_m_soft_interrupt
+80001134 g       .text	00000000 HW_get_16bit_reg_field
+80001adc g     F .text	00000058 MSYS_EI0_IRQHandler
+8000160c g     F .text	00000054 TMR_clear_int
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:113
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	1a10006f          	j	800009a0 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:124
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:130
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	1100006f          	j	80000120 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:139
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	1880006f          	j	800001a8 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:148
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	2000006f          	j	80000230 <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:159
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	2740006f          	j	800002b8 <vector_MGEUI_trap_handler>
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:165
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	2f80006f          	j	80000340 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:177
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	0350006f          	j	80000890 <vector_SUBSYSR_IRQHandler>
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:184
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	6980006f          	j	800006f8 <vector_SUBSYS_IRQHandler>
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:191
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	3640006f          	j	800003c8 <vector_MSYS_EI0_trap_handler>
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:197
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	3e80006f          	j	80000450 <vector_MSYS_EI1_trap_handler>
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:203
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	46c0006f          	j	800004d8 <vector_MSYS_EI2_trap_handler>
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:209
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	4f00006f          	j	80000560 <vector_MSYS_EI3_trap_handler>
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:215
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	5740006f          	j	800005e8 <vector_MSYS_EI4_trap_handler>
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:221
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	5f80006f          	j	80000670 <vector_MSYS_EI5_trap_handler>
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:228
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	7040006f          	j	80000780 <vector_MSYS_EI6_trap_handler>
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:238
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	7880006f          	j	80000808 <vector_MSYS_EI7_trap_handler>
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:247
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	f8010113          	addi	sp,sp,-128
+80000094:	00112023          	sw	ra,0(sp)
+80000098:	00212223          	sw	sp,4(sp)
+8000009c:	00312423          	sw	gp,8(sp)
+800000a0:	00412623          	sw	tp,12(sp)
+800000a4:	00512823          	sw	t0,16(sp)
+800000a8:	00612a23          	sw	t1,20(sp)
+800000ac:	00712c23          	sw	t2,24(sp)
+800000b0:	00812e23          	sw	s0,28(sp)
+800000b4:	02912023          	sw	s1,32(sp)
+800000b8:	02a12223          	sw	a0,36(sp)
+800000bc:	02b12423          	sw	a1,40(sp)
+800000c0:	02c12623          	sw	a2,44(sp)
+800000c4:	02d12823          	sw	a3,48(sp)
+800000c8:	02e12a23          	sw	a4,52(sp)
+800000cc:	02f12c23          	sw	a5,56(sp)
+800000d0:	03012e23          	sw	a6,60(sp)
+800000d4:	05112023          	sw	a7,64(sp)
+800000d8:	05212223          	sw	s2,68(sp)
+800000dc:	05312423          	sw	s3,72(sp)
+800000e0:	05412623          	sw	s4,76(sp)
+800000e4:	05512823          	sw	s5,80(sp)
+800000e8:	05612a23          	sw	s6,84(sp)
+800000ec:	05712c23          	sw	s7,88(sp)
+800000f0:	05812e23          	sw	s8,92(sp)
+800000f4:	07912023          	sw	s9,96(sp)
+800000f8:	07a12223          	sw	s10,100(sp)
+800000fc:	07b12423          	sw	s11,104(sp)
+80000100:	07c12623          	sw	t3,108(sp)
+80000104:	07d12823          	sw	t4,112(sp)
+80000108:	07e12a23          	sw	t5,116(sp)
+8000010c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+  csrr a0, mcause
+80000110:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a1, mepc
+80000114:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  jal handle_trap
+80000118:	401000ef          	jal	ra,80000d18 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  j generic_restore
+8000011c:	7fc0006f          	j	80000918 <generic_restore>
+
+80000120 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:254
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+80000120:	f8010113          	addi	sp,sp,-128
+80000124:	00112023          	sw	ra,0(sp)
+80000128:	00212223          	sw	sp,4(sp)
+8000012c:	00312423          	sw	gp,8(sp)
+80000130:	00412623          	sw	tp,12(sp)
+80000134:	00512823          	sw	t0,16(sp)
+80000138:	00612a23          	sw	t1,20(sp)
+8000013c:	00712c23          	sw	t2,24(sp)
+80000140:	00812e23          	sw	s0,28(sp)
+80000144:	02912023          	sw	s1,32(sp)
+80000148:	02a12223          	sw	a0,36(sp)
+8000014c:	02b12423          	sw	a1,40(sp)
+80000150:	02c12623          	sw	a2,44(sp)
+80000154:	02d12823          	sw	a3,48(sp)
+80000158:	02e12a23          	sw	a4,52(sp)
+8000015c:	02f12c23          	sw	a5,56(sp)
+80000160:	03012e23          	sw	a6,60(sp)
+80000164:	05112023          	sw	a7,64(sp)
+80000168:	05212223          	sw	s2,68(sp)
+8000016c:	05312423          	sw	s3,72(sp)
+80000170:	05412623          	sw	s4,76(sp)
+80000174:	05512823          	sw	s5,80(sp)
+80000178:	05612a23          	sw	s6,84(sp)
+8000017c:	05712c23          	sw	s7,88(sp)
+80000180:	05812e23          	sw	s8,92(sp)
+80000184:	07912023          	sw	s9,96(sp)
+80000188:	07a12223          	sw	s10,100(sp)
+8000018c:	07b12423          	sw	s11,104(sp)
+80000190:	07c12623          	sw	t3,108(sp)
+80000194:	07d12823          	sw	t4,112(sp)
+80000198:	07e12a23          	sw	t5,116(sp)
+8000019c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+  jal handle_m_soft_interrupt
+800001a0:	2c5000ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  j generic_restore
+800001a4:	7740006f          	j	80000918 <generic_restore>
+
+800001a8 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:259
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+800001a8:	f8010113          	addi	sp,sp,-128
+800001ac:	00112023          	sw	ra,0(sp)
+800001b0:	00212223          	sw	sp,4(sp)
+800001b4:	00312423          	sw	gp,8(sp)
+800001b8:	00412623          	sw	tp,12(sp)
+800001bc:	00512823          	sw	t0,16(sp)
+800001c0:	00612a23          	sw	t1,20(sp)
+800001c4:	00712c23          	sw	t2,24(sp)
+800001c8:	00812e23          	sw	s0,28(sp)
+800001cc:	02912023          	sw	s1,32(sp)
+800001d0:	02a12223          	sw	a0,36(sp)
+800001d4:	02b12423          	sw	a1,40(sp)
+800001d8:	02c12623          	sw	a2,44(sp)
+800001dc:	02d12823          	sw	a3,48(sp)
+800001e0:	02e12a23          	sw	a4,52(sp)
+800001e4:	02f12c23          	sw	a5,56(sp)
+800001e8:	03012e23          	sw	a6,60(sp)
+800001ec:	05112023          	sw	a7,64(sp)
+800001f0:	05212223          	sw	s2,68(sp)
+800001f4:	05312423          	sw	s3,72(sp)
+800001f8:	05412623          	sw	s4,76(sp)
+800001fc:	05512823          	sw	s5,80(sp)
+80000200:	05612a23          	sw	s6,84(sp)
+80000204:	05712c23          	sw	s7,88(sp)
+80000208:	05812e23          	sw	s8,92(sp)
+8000020c:	07912023          	sw	s9,96(sp)
+80000210:	07a12223          	sw	s10,100(sp)
+80000214:	07b12423          	sw	s11,104(sp)
+80000218:	07c12623          	sw	t3,108(sp)
+8000021c:	07d12823          	sw	t4,112(sp)
+80000220:	07e12a23          	sw	t5,116(sp)
+80000224:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+  jal handle_m_timer_interrupt
+80000228:	0f1000ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  j generic_restore
+8000022c:	6ec0006f          	j	80000918 <generic_restore>
+
+80000230 <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:264
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+80000230:	f8010113          	addi	sp,sp,-128
+80000234:	00112023          	sw	ra,0(sp)
+80000238:	00212223          	sw	sp,4(sp)
+8000023c:	00312423          	sw	gp,8(sp)
+80000240:	00412623          	sw	tp,12(sp)
+80000244:	00512823          	sw	t0,16(sp)
+80000248:	00612a23          	sw	t1,20(sp)
+8000024c:	00712c23          	sw	t2,24(sp)
+80000250:	00812e23          	sw	s0,28(sp)
+80000254:	02912023          	sw	s1,32(sp)
+80000258:	02a12223          	sw	a0,36(sp)
+8000025c:	02b12423          	sw	a1,40(sp)
+80000260:	02c12623          	sw	a2,44(sp)
+80000264:	02d12823          	sw	a3,48(sp)
+80000268:	02e12a23          	sw	a4,52(sp)
+8000026c:	02f12c23          	sw	a5,56(sp)
+80000270:	03012e23          	sw	a6,60(sp)
+80000274:	05112023          	sw	a7,64(sp)
+80000278:	05212223          	sw	s2,68(sp)
+8000027c:	05312423          	sw	s3,72(sp)
+80000280:	05412623          	sw	s4,76(sp)
+80000284:	05512823          	sw	s5,80(sp)
+80000288:	05612a23          	sw	s6,84(sp)
+8000028c:	05712c23          	sw	s7,88(sp)
+80000290:	05812e23          	sw	s8,92(sp)
+80000294:	07912023          	sw	s9,96(sp)
+80000298:	07a12223          	sw	s10,100(sp)
+8000029c:	07b12423          	sw	s11,104(sp)
+800002a0:	07c12623          	sw	t3,108(sp)
+800002a4:	07d12823          	sw	t4,112(sp)
+800002a8:	07e12a23          	sw	t5,116(sp)
+800002ac:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:268
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800002b0:	43d000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:270
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800002b4:	6640006f          	j	80000918 <generic_restore>
+
+800002b8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:274
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800002b8:	f8010113          	addi	sp,sp,-128
+800002bc:	00112023          	sw	ra,0(sp)
+800002c0:	00212223          	sw	sp,4(sp)
+800002c4:	00312423          	sw	gp,8(sp)
+800002c8:	00412623          	sw	tp,12(sp)
+800002cc:	00512823          	sw	t0,16(sp)
+800002d0:	00612a23          	sw	t1,20(sp)
+800002d4:	00712c23          	sw	t2,24(sp)
+800002d8:	00812e23          	sw	s0,28(sp)
+800002dc:	02912023          	sw	s1,32(sp)
+800002e0:	02a12223          	sw	a0,36(sp)
+800002e4:	02b12423          	sw	a1,40(sp)
+800002e8:	02c12623          	sw	a2,44(sp)
+800002ec:	02d12823          	sw	a3,48(sp)
+800002f0:	02e12a23          	sw	a4,52(sp)
+800002f4:	02f12c23          	sw	a5,56(sp)
+800002f8:	03012e23          	sw	a6,60(sp)
+800002fc:	05112023          	sw	a7,64(sp)
+80000300:	05212223          	sw	s2,68(sp)
+80000304:	05312423          	sw	s3,72(sp)
+80000308:	05412623          	sw	s4,76(sp)
+8000030c:	05512823          	sw	s5,80(sp)
+80000310:	05612a23          	sw	s6,84(sp)
+80000314:	05712c23          	sw	s7,88(sp)
+80000318:	05812e23          	sw	s8,92(sp)
+8000031c:	07912023          	sw	s9,96(sp)
+80000320:	07a12223          	sw	s10,100(sp)
+80000324:	07b12423          	sw	s11,104(sp)
+80000328:	07c12623          	sw	t3,108(sp)
+8000032c:	07d12823          	sw	t4,112(sp)
+80000330:	07e12a23          	sw	t5,116(sp)
+80000334:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+  jal MGEUI_IRQHandler
+80000338:	3ed000ef          	jal	ra,80000f24 <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  j generic_restore
+8000033c:	5dc0006f          	j	80000918 <generic_restore>
+
+80000340 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:279
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000340:	f8010113          	addi	sp,sp,-128
+80000344:	00112023          	sw	ra,0(sp)
+80000348:	00212223          	sw	sp,4(sp)
+8000034c:	00312423          	sw	gp,8(sp)
+80000350:	00412623          	sw	tp,12(sp)
+80000354:	00512823          	sw	t0,16(sp)
+80000358:	00612a23          	sw	t1,20(sp)
+8000035c:	00712c23          	sw	t2,24(sp)
+80000360:	00812e23          	sw	s0,28(sp)
+80000364:	02912023          	sw	s1,32(sp)
+80000368:	02a12223          	sw	a0,36(sp)
+8000036c:	02b12423          	sw	a1,40(sp)
+80000370:	02c12623          	sw	a2,44(sp)
+80000374:	02d12823          	sw	a3,48(sp)
+80000378:	02e12a23          	sw	a4,52(sp)
+8000037c:	02f12c23          	sw	a5,56(sp)
+80000380:	03012e23          	sw	a6,60(sp)
+80000384:	05112023          	sw	a7,64(sp)
+80000388:	05212223          	sw	s2,68(sp)
+8000038c:	05312423          	sw	s3,72(sp)
+80000390:	05412623          	sw	s4,76(sp)
+80000394:	05512823          	sw	s5,80(sp)
+80000398:	05612a23          	sw	s6,84(sp)
+8000039c:	05712c23          	sw	s7,88(sp)
+800003a0:	05812e23          	sw	s8,92(sp)
+800003a4:	07912023          	sw	s9,96(sp)
+800003a8:	07a12223          	sw	s10,100(sp)
+800003ac:	07b12423          	sw	s11,104(sp)
+800003b0:	07c12623          	sw	t3,108(sp)
+800003b4:	07d12823          	sw	t4,112(sp)
+800003b8:	07e12a23          	sw	t5,116(sp)
+800003bc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+  jal MGECI_IRQHandler
+800003c0:	349000ef          	jal	ra,80000f08 <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  j generic_restore
+800003c4:	5540006f          	j	80000918 <generic_restore>
+
+800003c8 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:284
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+800003c8:	f8010113          	addi	sp,sp,-128
+800003cc:	00112023          	sw	ra,0(sp)
+800003d0:	00212223          	sw	sp,4(sp)
+800003d4:	00312423          	sw	gp,8(sp)
+800003d8:	00412623          	sw	tp,12(sp)
+800003dc:	00512823          	sw	t0,16(sp)
+800003e0:	00612a23          	sw	t1,20(sp)
+800003e4:	00712c23          	sw	t2,24(sp)
+800003e8:	00812e23          	sw	s0,28(sp)
+800003ec:	02912023          	sw	s1,32(sp)
+800003f0:	02a12223          	sw	a0,36(sp)
+800003f4:	02b12423          	sw	a1,40(sp)
+800003f8:	02c12623          	sw	a2,44(sp)
+800003fc:	02d12823          	sw	a3,48(sp)
+80000400:	02e12a23          	sw	a4,52(sp)
+80000404:	02f12c23          	sw	a5,56(sp)
+80000408:	03012e23          	sw	a6,60(sp)
+8000040c:	05112023          	sw	a7,64(sp)
+80000410:	05212223          	sw	s2,68(sp)
+80000414:	05312423          	sw	s3,72(sp)
+80000418:	05412623          	sw	s4,76(sp)
+8000041c:	05512823          	sw	s5,80(sp)
+80000420:	05612a23          	sw	s6,84(sp)
+80000424:	05712c23          	sw	s7,88(sp)
+80000428:	05812e23          	sw	s8,92(sp)
+8000042c:	07912023          	sw	s9,96(sp)
+80000430:	07a12223          	sw	s10,100(sp)
+80000434:	07b12423          	sw	s11,104(sp)
+80000438:	07c12623          	sw	t3,108(sp)
+8000043c:	07d12823          	sw	t4,112(sp)
+80000440:	07e12a23          	sw	t5,116(sp)
+80000444:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+  jal MSYS_EI0_IRQHandler
+80000448:	694010ef          	jal	ra,80001adc <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  j generic_restore
+8000044c:	4cc0006f          	j	80000918 <generic_restore>
+
+80000450 <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:289
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+80000450:	f8010113          	addi	sp,sp,-128
+80000454:	00112023          	sw	ra,0(sp)
+80000458:	00212223          	sw	sp,4(sp)
+8000045c:	00312423          	sw	gp,8(sp)
+80000460:	00412623          	sw	tp,12(sp)
+80000464:	00512823          	sw	t0,16(sp)
+80000468:	00612a23          	sw	t1,20(sp)
+8000046c:	00712c23          	sw	t2,24(sp)
+80000470:	00812e23          	sw	s0,28(sp)
+80000474:	02912023          	sw	s1,32(sp)
+80000478:	02a12223          	sw	a0,36(sp)
+8000047c:	02b12423          	sw	a1,40(sp)
+80000480:	02c12623          	sw	a2,44(sp)
+80000484:	02d12823          	sw	a3,48(sp)
+80000488:	02e12a23          	sw	a4,52(sp)
+8000048c:	02f12c23          	sw	a5,56(sp)
+80000490:	03012e23          	sw	a6,60(sp)
+80000494:	05112023          	sw	a7,64(sp)
+80000498:	05212223          	sw	s2,68(sp)
+8000049c:	05312423          	sw	s3,72(sp)
+800004a0:	05412623          	sw	s4,76(sp)
+800004a4:	05512823          	sw	s5,80(sp)
+800004a8:	05612a23          	sw	s6,84(sp)
+800004ac:	05712c23          	sw	s7,88(sp)
+800004b0:	05812e23          	sw	s8,92(sp)
+800004b4:	07912023          	sw	s9,96(sp)
+800004b8:	07a12223          	sw	s10,100(sp)
+800004bc:	07b12423          	sw	s11,104(sp)
+800004c0:	07c12623          	sw	t3,108(sp)
+800004c4:	07d12823          	sw	t4,112(sp)
+800004c8:	07e12a23          	sw	t5,116(sp)
+800004cc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+  jal MSYS_EI1_IRQHandler
+800004d0:	28d000ef          	jal	ra,80000f5c <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  j generic_restore
+800004d4:	4440006f          	j	80000918 <generic_restore>
+
+800004d8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:294
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800004d8:	f8010113          	addi	sp,sp,-128
+800004dc:	00112023          	sw	ra,0(sp)
+800004e0:	00212223          	sw	sp,4(sp)
+800004e4:	00312423          	sw	gp,8(sp)
+800004e8:	00412623          	sw	tp,12(sp)
+800004ec:	00512823          	sw	t0,16(sp)
+800004f0:	00612a23          	sw	t1,20(sp)
+800004f4:	00712c23          	sw	t2,24(sp)
+800004f8:	00812e23          	sw	s0,28(sp)
+800004fc:	02912023          	sw	s1,32(sp)
+80000500:	02a12223          	sw	a0,36(sp)
+80000504:	02b12423          	sw	a1,40(sp)
+80000508:	02c12623          	sw	a2,44(sp)
+8000050c:	02d12823          	sw	a3,48(sp)
+80000510:	02e12a23          	sw	a4,52(sp)
+80000514:	02f12c23          	sw	a5,56(sp)
+80000518:	03012e23          	sw	a6,60(sp)
+8000051c:	05112023          	sw	a7,64(sp)
+80000520:	05212223          	sw	s2,68(sp)
+80000524:	05312423          	sw	s3,72(sp)
+80000528:	05412623          	sw	s4,76(sp)
+8000052c:	05512823          	sw	s5,80(sp)
+80000530:	05612a23          	sw	s6,84(sp)
+80000534:	05712c23          	sw	s7,88(sp)
+80000538:	05812e23          	sw	s8,92(sp)
+8000053c:	07912023          	sw	s9,96(sp)
+80000540:	07a12223          	sw	s10,100(sp)
+80000544:	07b12423          	sw	s11,104(sp)
+80000548:	07c12623          	sw	t3,108(sp)
+8000054c:	07d12823          	sw	t4,112(sp)
+80000550:	07e12a23          	sw	t5,116(sp)
+80000554:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+  jal MSYS_EI2_IRQHandler
+80000558:	221000ef          	jal	ra,80000f78 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  j generic_restore
+8000055c:	3bc0006f          	j	80000918 <generic_restore>
+
+80000560 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:299
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000560:	f8010113          	addi	sp,sp,-128
+80000564:	00112023          	sw	ra,0(sp)
+80000568:	00212223          	sw	sp,4(sp)
+8000056c:	00312423          	sw	gp,8(sp)
+80000570:	00412623          	sw	tp,12(sp)
+80000574:	00512823          	sw	t0,16(sp)
+80000578:	00612a23          	sw	t1,20(sp)
+8000057c:	00712c23          	sw	t2,24(sp)
+80000580:	00812e23          	sw	s0,28(sp)
+80000584:	02912023          	sw	s1,32(sp)
+80000588:	02a12223          	sw	a0,36(sp)
+8000058c:	02b12423          	sw	a1,40(sp)
+80000590:	02c12623          	sw	a2,44(sp)
+80000594:	02d12823          	sw	a3,48(sp)
+80000598:	02e12a23          	sw	a4,52(sp)
+8000059c:	02f12c23          	sw	a5,56(sp)
+800005a0:	03012e23          	sw	a6,60(sp)
+800005a4:	05112023          	sw	a7,64(sp)
+800005a8:	05212223          	sw	s2,68(sp)
+800005ac:	05312423          	sw	s3,72(sp)
+800005b0:	05412623          	sw	s4,76(sp)
+800005b4:	05512823          	sw	s5,80(sp)
+800005b8:	05612a23          	sw	s6,84(sp)
+800005bc:	05712c23          	sw	s7,88(sp)
+800005c0:	05812e23          	sw	s8,92(sp)
+800005c4:	07912023          	sw	s9,96(sp)
+800005c8:	07a12223          	sw	s10,100(sp)
+800005cc:	07b12423          	sw	s11,104(sp)
+800005d0:	07c12623          	sw	t3,108(sp)
+800005d4:	07d12823          	sw	t4,112(sp)
+800005d8:	07e12a23          	sw	t5,116(sp)
+800005dc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+  jal MSYS_EI3_IRQHandler
+800005e0:	1b5000ef          	jal	ra,80000f94 <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  j generic_restore
+800005e4:	3340006f          	j	80000918 <generic_restore>
+
+800005e8 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:304
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+800005e8:	f8010113          	addi	sp,sp,-128
+800005ec:	00112023          	sw	ra,0(sp)
+800005f0:	00212223          	sw	sp,4(sp)
+800005f4:	00312423          	sw	gp,8(sp)
+800005f8:	00412623          	sw	tp,12(sp)
+800005fc:	00512823          	sw	t0,16(sp)
+80000600:	00612a23          	sw	t1,20(sp)
+80000604:	00712c23          	sw	t2,24(sp)
+80000608:	00812e23          	sw	s0,28(sp)
+8000060c:	02912023          	sw	s1,32(sp)
+80000610:	02a12223          	sw	a0,36(sp)
+80000614:	02b12423          	sw	a1,40(sp)
+80000618:	02c12623          	sw	a2,44(sp)
+8000061c:	02d12823          	sw	a3,48(sp)
+80000620:	02e12a23          	sw	a4,52(sp)
+80000624:	02f12c23          	sw	a5,56(sp)
+80000628:	03012e23          	sw	a6,60(sp)
+8000062c:	05112023          	sw	a7,64(sp)
+80000630:	05212223          	sw	s2,68(sp)
+80000634:	05312423          	sw	s3,72(sp)
+80000638:	05412623          	sw	s4,76(sp)
+8000063c:	05512823          	sw	s5,80(sp)
+80000640:	05612a23          	sw	s6,84(sp)
+80000644:	05712c23          	sw	s7,88(sp)
+80000648:	05812e23          	sw	s8,92(sp)
+8000064c:	07912023          	sw	s9,96(sp)
+80000650:	07a12223          	sw	s10,100(sp)
+80000654:	07b12423          	sw	s11,104(sp)
+80000658:	07c12623          	sw	t3,108(sp)
+8000065c:	07d12823          	sw	t4,112(sp)
+80000660:	07e12a23          	sw	t5,116(sp)
+80000664:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+  jal MSYS_EI4_IRQHandler
+80000668:	149000ef          	jal	ra,80000fb0 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  j generic_restore
+8000066c:	2ac0006f          	j	80000918 <generic_restore>
+
+80000670 <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:309
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+80000670:	f8010113          	addi	sp,sp,-128
+80000674:	00112023          	sw	ra,0(sp)
+80000678:	00212223          	sw	sp,4(sp)
+8000067c:	00312423          	sw	gp,8(sp)
+80000680:	00412623          	sw	tp,12(sp)
+80000684:	00512823          	sw	t0,16(sp)
+80000688:	00612a23          	sw	t1,20(sp)
+8000068c:	00712c23          	sw	t2,24(sp)
+80000690:	00812e23          	sw	s0,28(sp)
+80000694:	02912023          	sw	s1,32(sp)
+80000698:	02a12223          	sw	a0,36(sp)
+8000069c:	02b12423          	sw	a1,40(sp)
+800006a0:	02c12623          	sw	a2,44(sp)
+800006a4:	02d12823          	sw	a3,48(sp)
+800006a8:	02e12a23          	sw	a4,52(sp)
+800006ac:	02f12c23          	sw	a5,56(sp)
+800006b0:	03012e23          	sw	a6,60(sp)
+800006b4:	05112023          	sw	a7,64(sp)
+800006b8:	05212223          	sw	s2,68(sp)
+800006bc:	05312423          	sw	s3,72(sp)
+800006c0:	05412623          	sw	s4,76(sp)
+800006c4:	05512823          	sw	s5,80(sp)
+800006c8:	05612a23          	sw	s6,84(sp)
+800006cc:	05712c23          	sw	s7,88(sp)
+800006d0:	05812e23          	sw	s8,92(sp)
+800006d4:	07912023          	sw	s9,96(sp)
+800006d8:	07a12223          	sw	s10,100(sp)
+800006dc:	07b12423          	sw	s11,104(sp)
+800006e0:	07c12623          	sw	t3,108(sp)
+800006e4:	07d12823          	sw	t4,112(sp)
+800006e8:	07e12a23          	sw	t5,116(sp)
+800006ec:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+  jal MSYS_EI5_IRQHandler
+800006f0:	0dd000ef          	jal	ra,80000fcc <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  j generic_restore
+800006f4:	2240006f          	j	80000918 <generic_restore>
+
+800006f8 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:314
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+800006f8:	f8010113          	addi	sp,sp,-128
+800006fc:	00112023          	sw	ra,0(sp)
+80000700:	00212223          	sw	sp,4(sp)
+80000704:	00312423          	sw	gp,8(sp)
+80000708:	00412623          	sw	tp,12(sp)
+8000070c:	00512823          	sw	t0,16(sp)
+80000710:	00612a23          	sw	t1,20(sp)
+80000714:	00712c23          	sw	t2,24(sp)
+80000718:	00812e23          	sw	s0,28(sp)
+8000071c:	02912023          	sw	s1,32(sp)
+80000720:	02a12223          	sw	a0,36(sp)
+80000724:	02b12423          	sw	a1,40(sp)
+80000728:	02c12623          	sw	a2,44(sp)
+8000072c:	02d12823          	sw	a3,48(sp)
+80000730:	02e12a23          	sw	a4,52(sp)
+80000734:	02f12c23          	sw	a5,56(sp)
+80000738:	03012e23          	sw	a6,60(sp)
+8000073c:	05112023          	sw	a7,64(sp)
+80000740:	05212223          	sw	s2,68(sp)
+80000744:	05312423          	sw	s3,72(sp)
+80000748:	05412623          	sw	s4,76(sp)
+8000074c:	05512823          	sw	s5,80(sp)
+80000750:	05612a23          	sw	s6,84(sp)
+80000754:	05712c23          	sw	s7,88(sp)
+80000758:	05812e23          	sw	s8,92(sp)
+8000075c:	07912023          	sw	s9,96(sp)
+80000760:	07a12223          	sw	s10,100(sp)
+80000764:	07b12423          	sw	s11,104(sp)
+80000768:	07c12623          	sw	t3,108(sp)
+8000076c:	07d12823          	sw	t4,112(sp)
+80000770:	07e12a23          	sw	t5,116(sp)
+80000774:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+  jal SUBSYS_IRQHandler
+80000778:	7c8000ef          	jal	ra,80000f40 <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  j generic_restore
+8000077c:	19c0006f          	j	80000918 <generic_restore>
+
+80000780 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:320
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+80000780:	f8010113          	addi	sp,sp,-128
+80000784:	00112023          	sw	ra,0(sp)
+80000788:	00212223          	sw	sp,4(sp)
+8000078c:	00312423          	sw	gp,8(sp)
+80000790:	00412623          	sw	tp,12(sp)
+80000794:	00512823          	sw	t0,16(sp)
+80000798:	00612a23          	sw	t1,20(sp)
+8000079c:	00712c23          	sw	t2,24(sp)
+800007a0:	00812e23          	sw	s0,28(sp)
+800007a4:	02912023          	sw	s1,32(sp)
+800007a8:	02a12223          	sw	a0,36(sp)
+800007ac:	02b12423          	sw	a1,40(sp)
+800007b0:	02c12623          	sw	a2,44(sp)
+800007b4:	02d12823          	sw	a3,48(sp)
+800007b8:	02e12a23          	sw	a4,52(sp)
+800007bc:	02f12c23          	sw	a5,56(sp)
+800007c0:	03012e23          	sw	a6,60(sp)
+800007c4:	05112023          	sw	a7,64(sp)
+800007c8:	05212223          	sw	s2,68(sp)
+800007cc:	05312423          	sw	s3,72(sp)
+800007d0:	05412623          	sw	s4,76(sp)
+800007d4:	05512823          	sw	s5,80(sp)
+800007d8:	05612a23          	sw	s6,84(sp)
+800007dc:	05712c23          	sw	s7,88(sp)
+800007e0:	05812e23          	sw	s8,92(sp)
+800007e4:	07912023          	sw	s9,96(sp)
+800007e8:	07a12223          	sw	s10,100(sp)
+800007ec:	07b12423          	sw	s11,104(sp)
+800007f0:	07c12623          	sw	t3,108(sp)
+800007f4:	07d12823          	sw	t4,112(sp)
+800007f8:	07e12a23          	sw	t5,116(sp)
+800007fc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+  jal MSYS_EI6_IRQHandler
+80000800:	001000ef          	jal	ra,80001000 <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  j generic_restore
+80000804:	1140006f          	j	80000918 <generic_restore>
+
+80000808 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:325
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000808:	f8010113          	addi	sp,sp,-128
+8000080c:	00112023          	sw	ra,0(sp)
+80000810:	00212223          	sw	sp,4(sp)
+80000814:	00312423          	sw	gp,8(sp)
+80000818:	00412623          	sw	tp,12(sp)
+8000081c:	00512823          	sw	t0,16(sp)
+80000820:	00612a23          	sw	t1,20(sp)
+80000824:	00712c23          	sw	t2,24(sp)
+80000828:	00812e23          	sw	s0,28(sp)
+8000082c:	02912023          	sw	s1,32(sp)
+80000830:	02a12223          	sw	a0,36(sp)
+80000834:	02b12423          	sw	a1,40(sp)
+80000838:	02c12623          	sw	a2,44(sp)
+8000083c:	02d12823          	sw	a3,48(sp)
+80000840:	02e12a23          	sw	a4,52(sp)
+80000844:	02f12c23          	sw	a5,56(sp)
+80000848:	03012e23          	sw	a6,60(sp)
+8000084c:	05112023          	sw	a7,64(sp)
+80000850:	05212223          	sw	s2,68(sp)
+80000854:	05312423          	sw	s3,72(sp)
+80000858:	05412623          	sw	s4,76(sp)
+8000085c:	05512823          	sw	s5,80(sp)
+80000860:	05612a23          	sw	s6,84(sp)
+80000864:	05712c23          	sw	s7,88(sp)
+80000868:	05812e23          	sw	s8,92(sp)
+8000086c:	07912023          	sw	s9,96(sp)
+80000870:	07a12223          	sw	s10,100(sp)
+80000874:	07b12423          	sw	s11,104(sp)
+80000878:	07c12623          	sw	t3,108(sp)
+8000087c:	07d12823          	sw	t4,112(sp)
+80000880:	07e12a23          	sw	t5,116(sp)
+80000884:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+  jal MSYS_EI7_IRQHandler
+80000888:	794000ef          	jal	ra,8000101c <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  j generic_restore
+8000088c:	08c0006f          	j	80000918 <generic_restore>
+
+80000890 <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:331
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+80000890:	f8010113          	addi	sp,sp,-128
+80000894:	00112023          	sw	ra,0(sp)
+80000898:	00212223          	sw	sp,4(sp)
+8000089c:	00312423          	sw	gp,8(sp)
+800008a0:	00412623          	sw	tp,12(sp)
+800008a4:	00512823          	sw	t0,16(sp)
+800008a8:	00612a23          	sw	t1,20(sp)
+800008ac:	00712c23          	sw	t2,24(sp)
+800008b0:	00812e23          	sw	s0,28(sp)
+800008b4:	02912023          	sw	s1,32(sp)
+800008b8:	02a12223          	sw	a0,36(sp)
+800008bc:	02b12423          	sw	a1,40(sp)
+800008c0:	02c12623          	sw	a2,44(sp)
+800008c4:	02d12823          	sw	a3,48(sp)
+800008c8:	02e12a23          	sw	a4,52(sp)
+800008cc:	02f12c23          	sw	a5,56(sp)
+800008d0:	03012e23          	sw	a6,60(sp)
+800008d4:	05112023          	sw	a7,64(sp)
+800008d8:	05212223          	sw	s2,68(sp)
+800008dc:	05312423          	sw	s3,72(sp)
+800008e0:	05412623          	sw	s4,76(sp)
+800008e4:	05512823          	sw	s5,80(sp)
+800008e8:	05612a23          	sw	s6,84(sp)
+800008ec:	05712c23          	sw	s7,88(sp)
+800008f0:	05812e23          	sw	s8,92(sp)
+800008f4:	07912023          	sw	s9,96(sp)
+800008f8:	07a12223          	sw	s10,100(sp)
+800008fc:	07b12423          	sw	s11,104(sp)
+80000900:	07c12623          	sw	t3,108(sp)
+80000904:	07d12823          	sw	t4,112(sp)
+80000908:	07e12a23          	sw	t5,116(sp)
+8000090c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+  jal SUBSYSR_IRQHandler
+80000910:	728000ef          	jal	ra,80001038 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  j generic_restore
+80000914:	0040006f          	j	80000918 <generic_restore>
+
+80000918 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:339
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000918:	00012083          	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+  LREG x2, 1 * REGBYTES(sp)
+8000091c:	00412103          	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x3, 2 * REGBYTES(sp)
+80000920:	00812183          	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x4, 3 * REGBYTES(sp)
+80000924:	00c12203          	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x5, 4 * REGBYTES(sp)
+80000928:	01012283          	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x6, 5 * REGBYTES(sp)
+8000092c:	01412303          	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x7, 6 * REGBYTES(sp)
+80000930:	01812383          	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x8, 7 * REGBYTES(sp)
+80000934:	01c12403          	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x9, 8 * REGBYTES(sp)
+80000938:	02012483          	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x10, 9 * REGBYTES(sp)
+8000093c:	02412503          	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x11, 10 * REGBYTES(sp)
+80000940:	02812583          	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x12, 11 * REGBYTES(sp)
+80000944:	02c12603          	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x13, 12 * REGBYTES(sp)
+80000948:	03012683          	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x14, 13 * REGBYTES(sp)
+8000094c:	03412703          	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x15, 14 * REGBYTES(sp)
+80000950:	03812783          	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x16, 15 * REGBYTES(sp)
+80000954:	03c12803          	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x17, 16 * REGBYTES(sp)
+80000958:	04012883          	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x18, 17 * REGBYTES(sp)
+8000095c:	04412903          	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x19, 18 * REGBYTES(sp)
+80000960:	04812983          	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x20, 19 * REGBYTES(sp)
+80000964:	04c12a03          	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x21, 20 * REGBYTES(sp)
+80000968:	05012a83          	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x22, 21 * REGBYTES(sp)
+8000096c:	05412b03          	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x23, 22 * REGBYTES(sp)
+80000970:	05812b83          	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x24, 23 * REGBYTES(sp)
+80000974:	05c12c03          	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x25, 24 * REGBYTES(sp)
+80000978:	06012c83          	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x26, 25 * REGBYTES(sp)
+8000097c:	06412d03          	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x27, 26 * REGBYTES(sp)
+80000980:	06812d83          	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x28, 27 * REGBYTES(sp)
+80000984:	06c12e03          	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x29, 28 * REGBYTES(sp)
+80000988:	07012e83          	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x30, 29 * REGBYTES(sp)
+8000098c:	07412f03          	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x31, 30 * REGBYTES(sp)
+80000990:	07812f83          	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:408
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+80000994:	08010113          	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  mret
+80000998:	30200073          	mret
+8000099c:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+800009a0 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:418
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+800009a0:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+  csrwi mie, 0
+800009a4:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  la ra, _start
+800009a8:	fffff097          	auipc	ra,0xfffff
+800009ac:	65808093          	addi	ra,ra,1624 # 80000000 <RAM_START_ADDRESS>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:424
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+800009b0:	0200c2b7          	lui	t0,0x200c
+800009b4:	ffc28293          	addi	t0,t0,-4 # 200bffc <RAM_SIZE+0x2003ffc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+  sw x0, 0(t0)
+800009b8:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:428
+#endif
+
+  csrr t0, misa
+800009bc:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+  andi t0, t0, A_EXTENSION_MASK
+800009c0:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+800009c4:	02029663          	bnez	t0,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:438
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+800009c8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+800009cc:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  li t1, MTVEC_VECTORED_MODE_VAL
+800009d0:	00100313          	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+800009d4:	00629e63          	bne	t0,t1,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:445
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+800009d8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+  andi t0, t0, 0xFFFFFFFC
+800009dc:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  la t1, trap_entry
+800009e0:	fffff317          	auipc	t1,0xfffff
+800009e4:	62430313          	addi	t1,t1,1572 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  bne t0, t1, vector_address_not_matching
+800009e8:	04629863          	bne	t0,t1,80000a38 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  j generic_reset_handling
+800009ec:	0100006f          	j	800009fc <generic_reset_handling>
+
+800009f0 <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:476
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+800009f0:	fffff297          	auipc	t0,0xfffff
+800009f4:	61428293          	addi	t0,t0,1556 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:482
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+800009f8:	30529073          	csrw	mtvec,t0
+
+800009fc <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:487
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+800009fc:	00001717          	auipc	a4,0x1
+80000a00:	20470713          	addi	a4,a4,516 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+    la a5, __sdata_start
+80000a04:	00001797          	auipc	a5,0x1
+80000a08:	1fc78793          	addi	a5,a5,508 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a6, __sdata_end
+80000a0c:	00001817          	auipc	a6,0x1
+80000a10:	1f480813          	addi	a6,a6,500 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+80000a14:	00f70863          	beq	a4,a5,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+80000a18:	01078663          	beq	a5,a6,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    call block_copy
+80000a1c:	00000097          	auipc	ra,0x0
+80000a20:	09c080e7          	jalr	156(ra) # 80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:496
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+80000a24:	00002197          	auipc	gp,0x2
+80000a28:	9dc18193          	addi	gp,gp,-1572 # 80002400 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:513
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+80000a2c:	010000ef          	jal	ra,80000a3c <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:515
+  /* Initialize stack pointer */
+  la sp, __stack_top
+80000a30:	10018113          	addi	sp,gp,256 # 80002500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:518
+
+  /* Jump into C code */
+  j _init
+80000a34:	4400006f          	j	80000e74 <_init>
+
+80000a38 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:523
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+80000a38:	00100073          	ebreak
+
+80000a3c <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:527
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+80000a3c:	00008293          	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+    la  a5, __bss_start
+80000a40:	8e018793          	addi	a5,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a6, __bss_end
+80000a44:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a48:	01078463          	beq	a5,a6,80000a50 <initializations+0x14>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    call zeroize_block
+80000a4c:	04c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:535
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000a50:	8c018793          	addi	a5,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+    la  a6, __sbss_end
+80000a54:	8e018813          	addi	a6,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a58:	01078c63          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    call zeroize_block
+80000a5c:	03c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:541
+
+/* Clear heap */
+    la  a5, __heap_start
+80000a60:	90018793          	addi	a5,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+    la  a6, __heap_end
+80000a64:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a68:	01078463          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    call zeroize_block
+80000a6c:	02c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:548
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000a70:	00001717          	auipc	a4,0x1
+80000a74:	19070713          	addi	a4,a4,400 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+    la  a5, __data_start
+80000a78:	00001797          	auipc	a5,0x1
+80000a7c:	18878793          	addi	a5,a5,392 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a6, __data_end
+80000a80:	8c018813          	addi	a6,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000a84:	00f70663          	beq	a4,a5,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000a88:	01078463          	beq	a5,a6,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    call block_copy
+80000a8c:	02c000ef          	jal	ra,80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:556
+
+1:
+    mv ra, t0           /* Retrieve ra */
+80000a90:	00028093          	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+    ret
+80000a94:	00008067          	ret
+
+80000a98 <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:560
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000a98:	04f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000a9c:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    andi a7, a7, 0x03u
+80000aa0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000aa4:	03104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000aa8 <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:565
+zeroize_loop:
+    sw x0, 0(a5)
+80000aa8:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+    add a5, a5, __SIZEOF_POINTER__
+80000aac:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    blt a5, a6, zeroize_loop
+80000ab0:	ff07cce3          	blt	a5,a6,80000aa8 <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    ret
+80000ab4:	00008067          	ret
+
+80000ab8 <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:571
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000ab8:	02f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000abc:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    andi a7, a7, 0x03u
+80000ac0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000ac4:	01104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000ac8 <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:576
+block_copy_loop:
+    lw a7, 0(a4)
+80000ac8:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+    sw a7, 0(a5)
+80000acc:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    addi a5, a5, 0x04
+80000ad0:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a4, a4, 0x04
+80000ad4:	00470713          	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    blt a5, a6, block_copy_loop
+80000ad8:	ff07c8e3          	blt	a5,a6,80000ac8 <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    j block_copy_exit
+80000adc:	0080006f          	j	80000ae4 <block_copy_exit>
+
+80000ae0 <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:584
+
+block_copy_error:
+    j block_copy_error
+80000ae0:	0000006f          	j	80000ae0 <block_copy_error>
+
+80000ae4 <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:587
+
+block_copy_exit:
+    ret
+80000ae4:	00008067          	ret
+
+80000ae8 <MRV_clear_soft_irq>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:730
+
+  @return
+  This function does not return any value.
+ */
+static inline void MRV_clear_soft_irq(void)
+{
+80000ae8:	ff010113          	addi	sp,sp,-16
+80000aec:	00812623          	sw	s0,12(sp)
+80000af0:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000af4:	000067b7          	lui	a5,0x6
+80000af8:	0207a703          	lw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+80000afc:	000067b7          	lui	a5,0x6
+80000b00:	ffd77713          	andi	a4,a4,-3
+80000b04:	02e7a023          	sw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:737
+#endif
+}
+80000b08:	00000013          	nop
+80000b0c:	00c12403          	lw	s0,12(sp)
+80000b10:	01010113          	addi	sp,sp,16
+80000b14:	00008067          	ret
+
+80000b18 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000b18:	fd010113          	addi	sp,sp,-48
+80000b1c:	02112623          	sw	ra,44(sp)
+80000b20:	02812423          	sw	s0,40(sp)
+80000b24:	03010413          	addi	s0,sp,48
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+80000b28:	08000793          	li	a5,128
+80000b2c:	3047b7f3          	csrrc	a5,mie,a5
+80000b30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MTIME;
+80000b34:	0200c7b7          	lui	a5,0x200c
+80000b38:	ff878793          	addi	a5,a5,-8 # 200bff8 <RAM_SIZE+0x2003ff8>
+80000b3c:	0007a783          	lw	a5,0(a5)
+80000b40:	fef42023          	sw	a5,-32(s0)
+80000b44:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000b48:	05c0006f          	j	80000ba4 <handle_m_timer_interrupt+0x8c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000b4c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b50:	0047a803          	lw	a6,4(a5)
+80000b54:	0007a783          	lw	a5,0(a5)
+80000b58:	8c018713          	addi	a4,gp,-1856 # 80001cc0 <__data_end>
+80000b5c:	00072583          	lw	a1,0(a4)
+80000b60:	00472603          	lw	a2,4(a4)
+80000b64:	00b786b3          	add	a3,a5,a1
+80000b68:	00068513          	mv	a0,a3
+80000b6c:	00f53533          	sltu	a0,a0,a5
+80000b70:	00c80733          	add	a4,a6,a2
+80000b74:	00e507b3          	add	a5,a0,a4
+80000b78:	00078713          	mv	a4,a5
+80000b7c:	00068793          	mv	a5,a3
+80000b80:	00070813          	mv	a6,a4
+80000b84:	8c818713          	addi	a4,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b88:	00f72023          	sw	a5,0(a4)
+80000b8c:	01072223          	sw	a6,4(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:205
+
+#ifndef NDEBUG
+        d_tick += 1;
+80000b90:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000b94:	0007a783          	lw	a5,0(a5)
+80000b98:	00178713          	addi	a4,a5,1
+80000b9c:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000ba0:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000ba4:	fe042783          	lw	a5,-32(s0)
+80000ba8:	fe442803          	lw	a6,-28(s0)
+80000bac:	00500593          	li	a1,5
+80000bb0:	00000613          	li	a2,0
+80000bb4:	00b786b3          	add	a3,a5,a1
+80000bb8:	00068513          	mv	a0,a3
+80000bbc:	00f53533          	sltu	a0,a0,a5
+80000bc0:	00c80733          	add	a4,a6,a2
+80000bc4:	00e507b3          	add	a5,a0,a4
+80000bc8:	00078713          	mv	a4,a5
+80000bcc:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000bd0:	0047a803          	lw	a6,4(a5)
+80000bd4:	0007a783          	lw	a5,0(a5)
+80000bd8:	00070593          	mv	a1,a4
+80000bdc:	00080613          	mv	a2,a6
+80000be0:	f6b666e3          	bltu	a2,a1,80000b4c <handle_m_timer_interrupt+0x34>
+80000be4:	00070593          	mv	a1,a4
+80000be8:	00080613          	mv	a2,a6
+80000bec:	00c59663          	bne	a1,a2,80000bf8 <handle_m_timer_interrupt+0xe0>
+80000bf0:	00068713          	mv	a4,a3
+80000bf4:	f4e7ece3          	bltu	a5,a4,80000b4c <handle_m_timer_interrupt+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+80000bf8:	020047b7          	lui	a5,0x2004
+80000bfc:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c00:	fff00713          	li	a4,-1
+80000c04:	00e7a023          	sw	a4,0(a5)
+80000c08:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c0c:	0047a803          	lw	a6,4(a5)
+80000c10:	0007a783          	lw	a5,0(a5)
+80000c14:	02004737          	lui	a4,0x2004
+80000c18:	00f72023          	sw	a5,0(a4) # 2004000 <RAM_SIZE+0x1ffc000>
+80000c1c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c20:	0047a803          	lw	a6,4(a5)
+80000c24:	0007a783          	lw	a5,0(a5)
+80000c28:	00085313          	srli	t1,a6,0x0
+80000c2c:	00000393          	li	t2,0
+80000c30:	020047b7          	lui	a5,0x2004
+80000c34:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c38:	00030713          	mv	a4,t1
+80000c3c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000c40:	290000ef          	jal	ra,80000ed0 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000c44:	08000793          	li	a5,128
+80000c48:	3047a7f3          	csrrs	a5,mie,a5
+80000c4c:	fcf42e23          	sw	a5,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+80000c50:	00000013          	nop
+80000c54:	02c12083          	lw	ra,44(sp)
+80000c58:	02812403          	lw	s0,40(sp)
+80000c5c:	03010113          	addi	sp,sp,48
+80000c60:	00008067          	ret
+
+80000c64 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+80000c64:	ff010113          	addi	sp,sp,-16
+80000c68:	00112623          	sw	ra,12(sp)
+80000c6c:	00812423          	sw	s0,8(sp)
+80000c70:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+80000c74:	244000ef          	jal	ra,80000eb8 <Software_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:233
+    MRV_clear_soft_irq();
+80000c78:	e71ff0ef          	jal	ra,80000ae8 <MRV_clear_soft_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+}
+80000c7c:	00000013          	nop
+80000c80:	00c12083          	lw	ra,12(sp)
+80000c84:	00812403          	lw	s0,8(sp)
+80000c88:	01010113          	addi	sp,sp,16
+80000c8c:	00008067          	ret
+
+80000c90 <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:305
+
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+80000c90:	fc010113          	addi	sp,sp,-64
+80000c94:	02112e23          	sw	ra,60(sp)
+80000c98:	02812c23          	sw	s0,56(sp)
+80000c9c:	04010413          	addi	s0,sp,64
+80000ca0:	00050793          	mv	a5,a0
+80000ca4:	fcf407a3          	sb	a5,-49(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+    uint64_t mhart_id = read_csr(mhartid);
+80000ca8:	f14027f3          	csrr	a5,mhartid
+80000cac:	fef42623          	sw	a5,-20(s0)
+80000cb0:	fec42783          	lw	a5,-20(s0)
+80000cb4:	fef42023          	sw	a5,-32(s0)
+80000cb8:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+80000cbc:	fcf44703          	lbu	a4,-49(s0)
+80000cc0:	01f00793          	li	a5,31
+80000cc4:	00e7f463          	bgeu	a5,a4,80000ccc <handle_local_ei_interrupts+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307 (discriminator 1)
+80000cc8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+80000ccc:	fcf44703          	lbu	a4,-49(s0)
+80000cd0:	00f00793          	li	a5,15
+80000cd4:	00e7e463          	bltu	a5,a4,80000cdc <handle_local_ei_interrupts+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308 (discriminator 1)
+80000cd8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+80000cdc:	fcf44783          	lbu	a5,-49(s0)
+80000ce0:	ff078793          	addi	a5,a5,-16
+80000ce4:	fcf40fa3          	sb	a5,-33(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+80000ce8:	fdf44783          	lbu	a5,-33(s0)
+80000cec:	00001717          	auipc	a4,0x1
+80000cf0:	ed470713          	addi	a4,a4,-300 # 80001bc0 <local_irq_handler_table>
+80000cf4:	00279793          	slli	a5,a5,0x2
+80000cf8:	00f707b3          	add	a5,a4,a5
+80000cfc:	0007a783          	lw	a5,0(a5)
+80000d00:	000780e7          	jalr	a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:312
+}
+80000d04:	00000013          	nop
+80000d08:	03c12083          	lw	ra,60(sp)
+80000d0c:	03812403          	lw	s0,56(sp)
+80000d10:	04010113          	addi	sp,sp,64
+80000d14:	00008067          	ret
+
+80000d18 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+
+/*------------------------------------------------------------------------------
+ * Trap handler. This function is invoked in the non-vectored mode.
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+80000d18:	fa010113          	addi	sp,sp,-96
+80000d1c:	04112e23          	sw	ra,92(sp)
+80000d20:	04812c23          	sw	s0,88(sp)
+80000d24:	06010413          	addi	s0,sp,96
+80000d28:	faa42623          	sw	a0,-84(s0)
+80000d2c:	fab42423          	sw	a1,-88(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:321
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+80000d30:	fac42703          	lw	a4,-84(s0)
+80000d34:	00070793          	mv	a5,a4
+80000d38:	00000813          	li	a6,0
+80000d3c:	80000737          	lui	a4,0x80000
+80000d40:	00e7f733          	and	a4,a5,a4
+80000d44:	fee42423          	sw	a4,-24(s0)
+80000d48:	00087793          	andi	a5,a6,0
+80000d4c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+
+    if (is_interrupt)
+80000d50:	fe842783          	lw	a5,-24(s0)
+80000d54:	fec42703          	lw	a4,-20(s0)
+80000d58:	00e7e7b3          	or	a5,a5,a4
+80000d5c:	0a078063          	beqz	a5,80000dfc <handle_trap+0xe4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+80000d60:	fac42703          	lw	a4,-84(s0)
+80000d64:	800007b7          	lui	a5,0x80000
+80000d68:	ff07c793          	xori	a5,a5,-16
+80000d6c:	00f777b3          	and	a5,a4,a5
+80000d70:	02078663          	beqz	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+80000d74:	fac42703          	lw	a4,-84(s0)
+80000d78:	800007b7          	lui	a5,0x80000
+80000d7c:	fe07c793          	xori	a5,a5,-32
+80000d80:	00f777b3          	and	a5,a4,a5
+80000d84:	00079c63          	bnez	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000d88:	fac42783          	lw	a5,-84(s0)
+80000d8c:	0ff7f793          	andi	a5,a5,255
+80000d90:	00078513          	mv	a0,a5
+80000d94:	efdff0ef          	jal	ra,80000c90 <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+#endif  /* NDEBUG */
+    }
+}
+80000d98:	0c80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000d9c:	fac42703          	lw	a4,-84(s0)
+80000da0:	800007b7          	lui	a5,0x80000
+80000da4:	fff7c793          	not	a5,a5
+80000da8:	00f77733          	and	a4,a4,a5
+80000dac:	00b00793          	li	a5,11
+80000db0:	00f71663          	bne	a4,a5,80000dbc <handle_trap+0xa4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+            External_IRQHandler();
+80000db4:	138000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000db8:	0a80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000dbc:	fac42703          	lw	a4,-84(s0)
+80000dc0:	800007b7          	lui	a5,0x80000
+80000dc4:	fff7c793          	not	a5,a5
+80000dc8:	00f77733          	and	a4,a4,a5
+80000dcc:	00300793          	li	a5,3
+80000dd0:	00f71663          	bne	a4,a5,80000ddc <handle_trap+0xc4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+            handle_m_soft_interrupt();
+80000dd4:	e91ff0ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000dd8:	0880006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+80000ddc:	fac42703          	lw	a4,-84(s0)
+80000de0:	800007b7          	lui	a5,0x80000
+80000de4:	fff7c793          	not	a5,a5
+80000de8:	00f77733          	and	a4,a4,a5
+80000dec:	00700793          	li	a5,7
+80000df0:	06f71863          	bne	a4,a5,80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+            handle_m_timer_interrupt();
+80000df4:	d25ff0ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000df8:	0680006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:382
+         uintptr_t mip      = read_csr(mip);
+80000dfc:	344027f3          	csrr	a5,mip
+80000e00:	fef42223          	sw	a5,-28(s0)
+80000e04:	fe442783          	lw	a5,-28(s0)
+80000e08:	fef42023          	sw	a5,-32(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:385
+         uintptr_t mtval = read_csr(mtval);
+80000e0c:	343027f3          	csrr	a5,mtval
+80000e10:	fcf42e23          	sw	a5,-36(s0)
+80000e14:	fdc42783          	lw	a5,-36(s0)
+80000e18:	fcf42c23          	sw	a5,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:388
+         uintptr_t mtvec    = read_csr(mtvec);
+80000e1c:	305027f3          	csrr	a5,mtvec
+80000e20:	fcf42a23          	sw	a5,-44(s0)
+80000e24:	fd442783          	lw	a5,-44(s0)
+80000e28:	fcf42823          	sw	a5,-48(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:391
+         uintptr_t mscratch = read_csr(mscratch);
+80000e2c:	340027f3          	csrr	a5,mscratch
+80000e30:	fcf42623          	sw	a5,-52(s0)
+80000e34:	fcc42783          	lw	a5,-52(s0)
+80000e38:	fcf42423          	sw	a5,-56(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:394
+         uintptr_t mstatus  = read_csr(mstatus);
+80000e3c:	300027f3          	csrr	a5,mstatus
+80000e40:	fcf42223          	sw	a5,-60(s0)
+80000e44:	fc442783          	lw	a5,-60(s0)
+80000e48:	fcf42023          	sw	a5,-64(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:397
+         uintptr_t mmepc  = read_csr(mepc);
+80000e4c:	341027f3          	csrr	a5,mepc
+80000e50:	faf42e23          	sw	a5,-68(s0)
+80000e54:	fbc42783          	lw	a5,-68(s0)
+80000e58:	faf42c23          	sw	a5,-72(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:400
+        __asm__("ebreak");
+80000e5c:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000e60:	00000013          	nop
+80000e64:	05c12083          	lw	ra,92(sp)
+80000e68:	05812403          	lw	s0,88(sp)
+80000e6c:	06010113          	addi	sp,sp,96
+80000e70:	00008067          	ret
+
+80000e74 <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:21
+#endif
+
+extern void main(void);
+
+void _init(void)
+{
+80000e74:	ff010113          	addi	sp,sp,-16
+80000e78:	00112623          	sw	ra,12(sp)
+80000e7c:	00812423          	sw	s0,8(sp)
+80000e80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+80000e84:	4b1000ef          	jal	ra,80001b34 <main>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:28
+}
+80000e88:	00000013          	nop
+80000e8c:	00c12083          	lw	ra,12(sp)
+80000e90:	00812403          	lw	s0,8(sp)
+80000e94:	01010113          	addi	sp,sp,16
+80000e98:	00008067          	ret
+
+80000e9c <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:33
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+80000e9c:	ff010113          	addi	sp,sp,-16
+80000ea0:	00812623          	sw	s0,12(sp)
+80000ea4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+}
+80000ea8:	00000013          	nop
+80000eac:	00c12403          	lw	s0,12(sp)
+80000eb0:	01010113          	addi	sp,sp,16
+80000eb4:	00008067          	ret
+
+80000eb8 <Software_IRQHandler>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000eb8:	ff010113          	addi	sp,sp,-16
+80000ebc:	00112623          	sw	ra,12(sp)
+80000ec0:	00812423          	sw	s0,8(sp)
+80000ec4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000ec8:	00a00513          	li	a0,10
+80000ecc:	188000ef          	jal	ra,80001054 <_exit>
+
+80000ed0 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:28
+}
+
+__attribute__((weak)) void SysTick_Handler(void)
+{
+80000ed0:	ff010113          	addi	sp,sp,-16
+80000ed4:	00812623          	sw	s0,12(sp)
+80000ed8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:30
+    /* Default handler */
+}
+80000edc:	00000013          	nop
+80000ee0:	00c12403          	lw	s0,12(sp)
+80000ee4:	01010113          	addi	sp,sp,16
+80000ee8:	00008067          	ret
+
+80000eec <External_IRQHandler>:
+External_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:195
+    return(0U); /* Default handler */
+}
+
+#else
+__attribute__((weak)) void External_IRQHandler(void)
+{
+80000eec:	ff010113          	addi	sp,sp,-16
+80000ef0:	00812623          	sw	s0,12(sp)
+80000ef4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:196
+}
+80000ef8:	00000013          	nop
+80000efc:	00c12403          	lw	s0,12(sp)
+80000f00:	01010113          	addi	sp,sp,16
+80000f04:	00008067          	ret
+
+80000f08 <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:198
+__attribute__((weak)) void MGECI_IRQHandler(void)
+{
+80000f08:	ff010113          	addi	sp,sp,-16
+80000f0c:	00812623          	sw	s0,12(sp)
+80000f10:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:199
+}
+80000f14:	00000013          	nop
+80000f18:	00c12403          	lw	s0,12(sp)
+80000f1c:	01010113          	addi	sp,sp,16
+80000f20:	00008067          	ret
+
+80000f24 <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:201
+__attribute__((weak)) void MGEUI_IRQHandler(void)
+{
+80000f24:	ff010113          	addi	sp,sp,-16
+80000f28:	00812623          	sw	s0,12(sp)
+80000f2c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:202
+}
+80000f30:	00000013          	nop
+80000f34:	00c12403          	lw	s0,12(sp)
+80000f38:	01010113          	addi	sp,sp,16
+80000f3c:	00008067          	ret
+
+80000f40 <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:204
+__attribute__((weak)) void SUBSYS_IRQHandler(void)
+{
+80000f40:	ff010113          	addi	sp,sp,-16
+80000f44:	00812623          	sw	s0,12(sp)
+80000f48:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:205
+}
+80000f4c:	00000013          	nop
+80000f50:	00c12403          	lw	s0,12(sp)
+80000f54:	01010113          	addi	sp,sp,16
+80000f58:	00008067          	ret
+
+80000f5c <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:210
+__attribute__((weak)) void MSYS_EI0_IRQHandler(void)
+{
+}
+__attribute__((weak)) void MSYS_EI1_IRQHandler(void)
+{
+80000f5c:	ff010113          	addi	sp,sp,-16
+80000f60:	00812623          	sw	s0,12(sp)
+80000f64:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:211
+}
+80000f68:	00000013          	nop
+80000f6c:	00c12403          	lw	s0,12(sp)
+80000f70:	01010113          	addi	sp,sp,16
+80000f74:	00008067          	ret
+
+80000f78 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:213
+__attribute__((weak)) void MSYS_EI2_IRQHandler(void)
+{
+80000f78:	ff010113          	addi	sp,sp,-16
+80000f7c:	00812623          	sw	s0,12(sp)
+80000f80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:214
+}
+80000f84:	00000013          	nop
+80000f88:	00c12403          	lw	s0,12(sp)
+80000f8c:	01010113          	addi	sp,sp,16
+80000f90:	00008067          	ret
+
+80000f94 <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:216
+__attribute__((weak)) void MSYS_EI3_IRQHandler(void)
+{
+80000f94:	ff010113          	addi	sp,sp,-16
+80000f98:	00812623          	sw	s0,12(sp)
+80000f9c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:217
+}
+80000fa0:	00000013          	nop
+80000fa4:	00c12403          	lw	s0,12(sp)
+80000fa8:	01010113          	addi	sp,sp,16
+80000fac:	00008067          	ret
+
+80000fb0 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:219
+__attribute__((weak)) void MSYS_EI4_IRQHandler(void)
+{
+80000fb0:	ff010113          	addi	sp,sp,-16
+80000fb4:	00812623          	sw	s0,12(sp)
+80000fb8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:220
+}
+80000fbc:	00000013          	nop
+80000fc0:	00c12403          	lw	s0,12(sp)
+80000fc4:	01010113          	addi	sp,sp,16
+80000fc8:	00008067          	ret
+
+80000fcc <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:222
+__attribute__((weak)) void MSYS_EI5_IRQHandler(void)
+{
+80000fcc:	ff010113          	addi	sp,sp,-16
+80000fd0:	00812623          	sw	s0,12(sp)
+80000fd4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:223
+}
+80000fd8:	00000013          	nop
+80000fdc:	00c12403          	lw	s0,12(sp)
+80000fe0:	01010113          	addi	sp,sp,16
+80000fe4:	00008067          	ret
+
+80000fe8 <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:225
+__attribute__((weak)) void Reserved_IRQHandler(void)
+{
+80000fe8:	ff010113          	addi	sp,sp,-16
+80000fec:	00112623          	sw	ra,12(sp)
+80000ff0:	00812423          	sw	s0,8(sp)
+80000ff4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:226
+    _exit(10);
+80000ff8:	00a00513          	li	a0,10
+80000ffc:	058000ef          	jal	ra,80001054 <_exit>
+
+80001000 <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:230
+}
+#ifndef MIV_RV32_V3_0 /* For MIV_RV32 v3.0 */
+__attribute__((weak)) void MSYS_EI6_IRQHandler(void)
+{
+80001000:	ff010113          	addi	sp,sp,-16
+80001004:	00812623          	sw	s0,12(sp)
+80001008:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:231
+}
+8000100c:	00000013          	nop
+80001010:	00c12403          	lw	s0,12(sp)
+80001014:	01010113          	addi	sp,sp,16
+80001018:	00008067          	ret
+
+8000101c <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:233
+__attribute__((weak)) void MSYS_EI7_IRQHandler(void)
+{
+8000101c:	ff010113          	addi	sp,sp,-16
+80001020:	00812623          	sw	s0,12(sp)
+80001024:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:234
+}
+80001028:	00000013          	nop
+8000102c:	00c12403          	lw	s0,12(sp)
+80001030:	01010113          	addi	sp,sp,16
+80001034:	00008067          	ret
+
+80001038 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:236
+__attribute__((weak)) void SUBSYSR_IRQHandler(void)
+{
+80001038:	ff010113          	addi	sp,sp,-16
+8000103c:	00812623          	sw	s0,12(sp)
+80001040:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:237
+}
+80001044:	00000013          	nop
+80001048:	00c12403          	lw	s0,12(sp)
+8000104c:	01010113          	addi	sp,sp,16
+80001050:	00008067          	ret
+
+80001054 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:142
+#ifdef GDB_TESTING
+void __attribute__((optimize("O0"))) _exit(int code)
+#else
+void _exit(int code)
+#endif
+{
+80001054:	fe010113          	addi	sp,sp,-32
+80001058:	00812e23          	sw	s0,28(sp)
+8000105c:	02010413          	addi	s0,sp,32
+80001060:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80001064:	0000006f          	j	80001064 <_exit+0x10>
+
+80001068 <MRV_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:616
+
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+80001068:	fe010113          	addi	sp,sp,-32
+8000106c:	00812e23          	sw	s0,28(sp)
+80001070:	02010413          	addi	s0,sp,32
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80001074:	300467f3          	csrrsi	a5,mstatus,8
+80001078:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:618
+}
+8000107c:	00000013          	nop
+80001080:	01c12403          	lw	s0,28(sp)
+80001084:	02010113          	addi	sp,sp,32
+80001088:	00008067          	ret
+
+8000108c <HAL_enable_interrupts>:
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:22
+#endif
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+8000108c:	ff010113          	addi	sp,sp,-16
+80001090:	00112623          	sw	ra,12(sp)
+80001094:	00812423          	sw	s0,8(sp)
+80001098:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:23
+    MRV_enable_interrupts();
+8000109c:	fcdff0ef          	jal	ra,80001068 <MRV_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:24
+}
+800010a0:	00000013          	nop
+800010a4:	00c12083          	lw	ra,12(sp)
+800010a8:	00812403          	lw	s0,8(sp)
+800010ac:	01010113          	addi	sp,sp,16
+800010b0:	00008067          	ret
+
+800010b4 <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+800010b4:	00b52023          	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:40
+    ret
+800010b8:	00008067          	ret
+
+800010bc <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+800010bc:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:52
+    ret
+800010c0:	00008067          	ret
+
+800010c4 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+800010c4:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+800010c8:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+800010cc:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+800010d0:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+800010d4:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+800010d8:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+800010dc:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+800010e0:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+800010e4:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:73
+    ret
+800010e8:	00008067          	ret
+
+800010ec <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+800010ec:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+800010f0:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+800010f4:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:90
+    ret
+800010f8:	00008067          	ret
+
+800010fc <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+800010fc:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:101
+    ret
+80001100:	00008067          	ret
+
+80001104 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+80001104:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:113
+    ret
+80001108:	00008067          	ret
+
+8000110c <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+8000110c:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80001110:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80001114:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80001118:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+8000111c:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+80001120:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80001124:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80001128:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+8000112c:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:135
+    ret
+80001130:	00008067          	ret
+
+80001134 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80001134:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80001138:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+8000113c:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:152
+    ret
+80001140:	00008067          	ret
+
+80001144 <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+80001144:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:163
+    ret
+80001148:	00008067          	ret
+
+8000114c <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+8000114c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:175
+    ret
+80001150:	00008067          	ret
+
+80001154 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80001154:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+80001158:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+8000115c:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80001160:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80001164:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80001168:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+8000116c:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80001170:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80001174:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:196
+    ret
+80001178:	00008067          	ret
+
+8000117c <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+8000117c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+80001180:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80001184:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:213
+    ret
+80001188:	00008067          	ret
+
+8000118c <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+    UART_instance_t * this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+)
+{
+8000118c:	fd010113          	addi	sp,sp,-48
+80001190:	02112623          	sw	ra,44(sp)
+80001194:	02812423          	sw	s0,40(sp)
+80001198:	03010413          	addi	s0,sp,48
+8000119c:	fca42e23          	sw	a0,-36(s0)
+800011a0:	fcb42c23          	sw	a1,-40(s0)
+800011a4:	00060793          	mv	a5,a2
+800011a8:	00068713          	mv	a4,a3
+800011ac:	fcf41b23          	sh	a5,-42(s0)
+800011b0:	00070793          	mv	a5,a4
+800011b4:	fcf40aa3          	sb	a5,-43(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49
+    uint8_t rx_full;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+800011b8:	fdc42783          	lw	a5,-36(s0)
+800011bc:	00079463          	bnez	a5,800011c4 <UART_init+0x38>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49 (discriminator 1)
+800011c0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+800011c4:	fd544703          	lbu	a4,-43(s0)
+800011c8:	00700793          	li	a5,7
+800011cc:	00e7f463          	bgeu	a5,a4,800011d4 <UART_init+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50 (discriminator 1)
+800011d0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+800011d4:	fd645703          	lhu	a4,-42(s0)
+800011d8:	000027b7          	lui	a5,0x2
+800011dc:	00f76463          	bltu	a4,a5,800011e4 <UART_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51 (discriminator 1)
+800011e0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+800011e4:	fdc42783          	lw	a5,-36(s0)
+800011e8:	16078463          	beqz	a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+800011ec:	fd544703          	lbu	a4,-43(s0)
+800011f0:	00700793          	li	a5,7
+800011f4:	14e7ee63          	bltu	a5,a4,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+800011f8:	fd645703          	lhu	a4,-42(s0)
+800011fc:	000027b7          	lui	a5,0x2
+80001200:	14f77863          	bgeu	a4,a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80001204:	fd842783          	lw	a5,-40(s0)
+80001208:	00878713          	addi	a4,a5,8 # 2008 <STACK_SIZE+0x1808>
+8000120c:	fd645783          	lhu	a5,-42(s0)
+80001210:	0ff7f793          	andi	a5,a5,255
+80001214:	00078593          	mv	a1,a5
+80001218:	00070513          	mv	a0,a4
+8000121c:	f29ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80001220:	fd842783          	lw	a5,-40(s0)
+80001224:	00c78693          	addi	a3,a5,12
+80001228:	fd544703          	lbu	a4,-43(s0)
+8000122c:	fd645783          	lhu	a5,-42(s0)
+80001230:	4057d793          	srai	a5,a5,0x5
+80001234:	7f87f793          	andi	a5,a5,2040
+80001238:	00f767b3          	or	a5,a4,a5
+8000123c:	00078593          	mv	a1,a5
+80001240:	00068513          	mv	a0,a3
+80001244:	f01ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+                                           (uint_fast8_t)((baud_value &
+                                   BAUDVALUE_MSB) >> BAUDVALUE_SHIFT ) );
+    
+        this_uart->base_address = base_addr;
+80001248:	fdc42783          	lw	a5,-36(s0)
+8000124c:	fd842703          	lw	a4,-40(s0)
+80001250:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:77
+#ifndef NDEBUG
+        {
+            uint8_t  config;
+            uint8_t  temp;
+            uint16_t baud_val;
+            baud_val = HAL_get_8bit_reg( this_uart->base_address, CTRL1 );
+80001254:	fdc42783          	lw	a5,-36(s0)
+80001258:	0007a783          	lw	a5,0(a5)
+8000125c:	00878793          	addi	a5,a5,8
+80001260:	00078513          	mv	a0,a5
+80001264:	ee9ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001268:	00050793          	mv	a5,a0
+8000126c:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:78
+            config =  HAL_get_8bit_reg( this_uart->base_address, CTRL2 );
+80001270:	fdc42783          	lw	a5,-36(s0)
+80001274:	0007a783          	lw	a5,0(a5)
+80001278:	00c78793          	addi	a5,a5,12
+8000127c:	00078513          	mv	a0,a5
+80001280:	ecdff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001284:	00050793          	mv	a5,a0
+80001288:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:82
+            /*
+             * To resolve operator precedence between & and <<
+             */
+            temp =  ( config  &  (uint8_t)(CTRL2_BAUDVALUE_MASK ) );
+8000128c:	feb44783          	lbu	a5,-21(s0)
+80001290:	ff87f793          	andi	a5,a5,-8
+80001294:	fef40523          	sb	a5,-22(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:83
+            baud_val |= (uint16_t)( (uint16_t)(temp) << BAUDVALUE_SHIFT );
+80001298:	fea44783          	lbu	a5,-22(s0)
+8000129c:	01079793          	slli	a5,a5,0x10
+800012a0:	0107d793          	srli	a5,a5,0x10
+800012a4:	00579793          	slli	a5,a5,0x5
+800012a8:	01079713          	slli	a4,a5,0x10
+800012ac:	01075713          	srli	a4,a4,0x10
+800012b0:	fec45783          	lhu	a5,-20(s0)
+800012b4:	00f767b3          	or	a5,a4,a5
+800012b8:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:84
+            config &= (uint8_t)(~CTRL2_BAUDVALUE_MASK);
+800012bc:	feb44783          	lbu	a5,-21(s0)
+800012c0:	0077f793          	andi	a5,a5,7
+800012c4:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85
+            HAL_ASSERT( baud_val == baud_value );
+800012c8:	fec45703          	lhu	a4,-20(s0)
+800012cc:	fd645783          	lhu	a5,-42(s0)
+800012d0:	00f70463          	beq	a4,a5,800012d8 <UART_init+0x14c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85 (discriminator 1)
+800012d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86
+            HAL_ASSERT( config == line_config );
+800012d8:	feb44703          	lbu	a4,-21(s0)
+800012dc:	fd544783          	lbu	a5,-43(s0)
+800012e0:	00f70463          	beq	a4,a5,800012e8 <UART_init+0x15c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86 (discriminator 1)
+800012e4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800012e8:	fdc42783          	lw	a5,-36(s0)
+800012ec:	0007a783          	lw	a5,0(a5)
+800012f0:	01078793          	addi	a5,a5,16
+800012f4:	00078513          	mv	a0,a5
+800012f8:	e55ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800012fc:	00050793          	mv	a5,a0
+80001300:	0027f793          	andi	a5,a5,2
+80001304:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+80001308:	0380006f          	j	80001340 <UART_init+0x1b4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+8000130c:	fdc42783          	lw	a5,-36(s0)
+80001310:	0007a783          	lw	a5,0(a5)
+80001314:	00478793          	addi	a5,a5,4
+80001318:	00078513          	mv	a0,a5
+8000131c:	e31ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80001320:	fdc42783          	lw	a5,-36(s0)
+80001324:	0007a783          	lw	a5,0(a5)
+80001328:	01078793          	addi	a5,a5,16
+8000132c:	00078513          	mv	a0,a5
+80001330:	e1dff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001334:	00050793          	mv	a5,a0
+80001338:	0027f793          	andi	a5,a5,2
+8000133c:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+80001340:	fef44783          	lbu	a5,-17(s0)
+80001344:	fc0794e3          	bnez	a5,8000130c <UART_init+0x180>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+80001348:	fdc42783          	lw	a5,-36(s0)
+8000134c:	00078223          	sb	zero,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+80001350:	00000013          	nop
+80001354:	02c12083          	lw	ra,44(sp)
+80001358:	02812403          	lw	s0,40(sp)
+8000135c:	03010113          	addi	sp,sp,48
+80001360:	00008067          	ret
+
+80001364 <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+UART_polled_tx_string
+( 
+    UART_instance_t * this_uart, 
+    const uint8_t * p_sz_string
+)
+{
+80001364:	fd010113          	addi	sp,sp,-48
+80001368:	02112623          	sw	ra,44(sp)
+8000136c:	02812423          	sw	s0,40(sp)
+80001370:	03010413          	addi	s0,sp,48
+80001374:	fca42e23          	sw	a0,-36(s0)
+80001378:	fcb42c23          	sw	a1,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243
+    uint32_t char_idx;
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+8000137c:	fdc42783          	lw	a5,-36(s0)
+80001380:	00079463          	bnez	a5,80001388 <UART_polled_tx_string+0x24>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243 (discriminator 1)
+80001384:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+80001388:	fd842783          	lw	a5,-40(s0)
+8000138c:	00079463          	bnez	a5,80001394 <UART_polled_tx_string+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244 (discriminator 1)
+80001390:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+80001394:	fdc42783          	lw	a5,-36(s0)
+80001398:	08078063          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+8000139c:	fd842783          	lw	a5,-40(s0)
+800013a0:	06078c63          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:248
+    {
+        char_idx = 0U;
+800013a4:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+800013a8:	05c0006f          	j	80001404 <UART_polled_tx_string+0xa0>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+        {
+            /* Wait for UART to become ready to transmit. */
+            do {
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800013ac:	fdc42783          	lw	a5,-36(s0)
+800013b0:	0007a783          	lw	a5,0(a5)
+800013b4:	01078793          	addi	a5,a5,16
+800013b8:	00078513          	mv	a0,a5
+800013bc:	d91ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800013c0:	00050793          	mv	a5,a0
+800013c4:	0017f793          	andi	a5,a5,1
+800013c8:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+                                                              STATUS_TXRDY_MASK;
+            } while ( !tx_ready );
+800013cc:	feb44783          	lbu	a5,-21(s0)
+800013d0:	fc078ee3          	beqz	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            /* Send next character in the buffer. */
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+800013d4:	fdc42783          	lw	a5,-36(s0)
+800013d8:	0007a683          	lw	a3,0(a5)
+800013dc:	fd842703          	lw	a4,-40(s0)
+800013e0:	fec42783          	lw	a5,-20(s0)
+800013e4:	00f707b3          	add	a5,a4,a5
+800013e8:	0007c783          	lbu	a5,0(a5)
+800013ec:	00078593          	mv	a1,a5
+800013f0:	00068513          	mv	a0,a3
+800013f4:	d51ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+800013f8:	fec42783          	lw	a5,-20(s0)
+800013fc:	00178793          	addi	a5,a5,1
+80001400:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+80001404:	fd842703          	lw	a4,-40(s0)
+80001408:	fec42783          	lw	a5,-20(s0)
+8000140c:	00f707b3          	add	a5,a4,a5
+80001410:	0007c783          	lbu	a5,0(a5)
+80001414:	f8079ce3          	bnez	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+        }
+    }
+}
+80001418:	00000013          	nop
+8000141c:	02c12083          	lw	ra,44(sp)
+80001420:	02812403          	lw	s0,40(sp)
+80001424:	03010113          	addi	sp,sp,48
+80001428:	00008067          	ret
+
+8000142c <TMR_init>:
+TMR_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:30
+    addr_t address,
+    uint8_t mode,
+    uint32_t prescale,
+    uint32_t load_value
+)
+{
+8000142c:	fd010113          	addi	sp,sp,-48
+80001430:	02112623          	sw	ra,44(sp)
+80001434:	02812423          	sw	s0,40(sp)
+80001438:	03010413          	addi	s0,sp,48
+8000143c:	fea42623          	sw	a0,-20(s0)
+80001440:	feb42423          	sw	a1,-24(s0)
+80001444:	00060793          	mv	a5,a2
+80001448:	fed42023          	sw	a3,-32(s0)
+8000144c:	fce42e23          	sw	a4,-36(s0)
+80001450:	fef403a3          	sb	a5,-25(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001454:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001458:	0007a783          	lw	a5,0(a5)
+8000145c:	fec42703          	lw	a4,-20(s0)
+80001460:	00f71463          	bne	a4,a5,80001468 <TMR_init+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31 (discriminator 1)
+80001464:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32
+    HAL_ASSERT( prescale <= PRESCALER_DIV_1024 )
+80001468:	fe042703          	lw	a4,-32(s0)
+8000146c:	00900793          	li	a5,9
+80001470:	00e7f463          	bgeu	a5,a4,80001478 <TMR_init+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32 (discriminator 1)
+80001474:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33
+    HAL_ASSERT( load_value != 0 )
+80001478:	fdc42783          	lw	a5,-36(s0)
+8000147c:	00079463          	bnez	a5,80001484 <TMR_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33 (discriminator 1)
+80001480:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:35
+    
+    this_timer->base_address = address;
+80001484:	fec42783          	lw	a5,-20(s0)
+80001488:	fe842703          	lw	a4,-24(s0)
+8000148c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:38
+
+    /* Disable interrupts. */
+    HAL_set_32bit_reg_field( address, InterruptEnable,0 );
+80001490:	fe842783          	lw	a5,-24(s0)
+80001494:	00878793          	addi	a5,a5,8
+80001498:	00000693          	li	a3,0
+8000149c:	00200613          	li	a2,2
+800014a0:	00100593          	li	a1,1
+800014a4:	00078513          	mv	a0,a5
+800014a8:	c1dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:41
+
+    /* Disable timer. */
+    HAL_set_32bit_reg_field( address, TimerEnable, 0 );
+800014ac:	fe842783          	lw	a5,-24(s0)
+800014b0:	00878793          	addi	a5,a5,8
+800014b4:	00000693          	li	a3,0
+800014b8:	00100613          	li	a2,1
+800014bc:	00000593          	li	a1,0
+800014c0:	00078513          	mv	a0,a5
+800014c4:	c01ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:44
+
+    /* Clear pending interrupt. */
+    HAL_set_32bit_reg( address, TimerIntClr, 1 );
+800014c8:	fe842783          	lw	a5,-24(s0)
+800014cc:	01078793          	addi	a5,a5,16
+800014d0:	00100593          	li	a1,1
+800014d4:	00078513          	mv	a0,a5
+800014d8:	bddff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:47
+
+    /* Configure prescaler and load value. */    
+    HAL_set_32bit_reg( address, TimerPrescale, prescale );
+800014dc:	fe842783          	lw	a5,-24(s0)
+800014e0:	00c78793          	addi	a5,a5,12
+800014e4:	fe042583          	lw	a1,-32(s0)
+800014e8:	00078513          	mv	a0,a5
+800014ec:	bc9ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:48
+    HAL_set_32bit_reg( address, TimerLoad, load_value );
+800014f0:	fdc42583          	lw	a1,-36(s0)
+800014f4:	fe842503          	lw	a0,-24(s0)
+800014f8:	bbdff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:51
+
+    /* Set the interrupt mode. */
+    if ( mode == TMR_CONTINUOUS_MODE )
+800014fc:	fe744783          	lbu	a5,-25(s0)
+80001500:	02079263          	bnez	a5,80001524 <TMR_init+0xf8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:53
+    {
+        HAL_set_32bit_reg_field( address, TimerMode, 0 );
+80001504:	fe842783          	lw	a5,-24(s0)
+80001508:	00878793          	addi	a5,a5,8
+8000150c:	00000693          	li	a3,0
+80001510:	00400613          	li	a2,4
+80001514:	00200593          	li	a1,2
+80001518:	00078513          	mv	a0,a5
+8000151c:	ba9ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+    else
+    {
+        /* TMR_ONE_SHOT_MODE */
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+    }
+}
+80001520:	0200006f          	j	80001540 <TMR_init+0x114>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:58
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+80001524:	fe842783          	lw	a5,-24(s0)
+80001528:	00878793          	addi	a5,a5,8
+8000152c:	00100693          	li	a3,1
+80001530:	00400613          	li	a2,4
+80001534:	00200593          	li	a1,2
+80001538:	00078513          	mv	a0,a5
+8000153c:	b89ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+}
+80001540:	00000013          	nop
+80001544:	02c12083          	lw	ra,44(sp)
+80001548:	02812403          	lw	s0,40(sp)
+8000154c:	03010113          	addi	sp,sp,48
+80001550:	00008067          	ret
+
+80001554 <TMR_start>:
+TMR_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:71
+void
+TMR_start
+(
+    timer_instance_t * this_timer
+)
+{
+80001554:	fe010113          	addi	sp,sp,-32
+80001558:	00112e23          	sw	ra,28(sp)
+8000155c:	00812c23          	sw	s0,24(sp)
+80001560:	02010413          	addi	s0,sp,32
+80001564:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001568:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+8000156c:	0007a783          	lw	a5,0(a5)
+80001570:	fec42703          	lw	a4,-20(s0)
+80001574:	00f71463          	bne	a4,a5,8000157c <TMR_start+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72 (discriminator 1)
+80001578:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:74
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 );
+8000157c:	fec42783          	lw	a5,-20(s0)
+80001580:	0007a783          	lw	a5,0(a5)
+80001584:	00878793          	addi	a5,a5,8
+80001588:	00100693          	li	a3,1
+8000158c:	00100613          	li	a2,1
+80001590:	00000593          	li	a1,0
+80001594:	00078513          	mv	a0,a5
+80001598:	b2dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:75
+}
+8000159c:	00000013          	nop
+800015a0:	01c12083          	lw	ra,28(sp)
+800015a4:	01812403          	lw	s0,24(sp)
+800015a8:	02010113          	addi	sp,sp,32
+800015ac:	00008067          	ret
+
+800015b0 <TMR_enable_int>:
+TMR_enable_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:102
+void
+TMR_enable_int
+(
+    timer_instance_t * this_timer
+)
+{
+800015b0:	fe010113          	addi	sp,sp,-32
+800015b4:	00112e23          	sw	ra,28(sp)
+800015b8:	00812c23          	sw	s0,24(sp)
+800015bc:	02010413          	addi	s0,sp,32
+800015c0:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+800015c4:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+800015c8:	0007a783          	lw	a5,0(a5)
+800015cc:	fec42703          	lw	a4,-20(s0)
+800015d0:	00f71463          	bne	a4,a5,800015d8 <TMR_enable_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103 (discriminator 1)
+800015d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:105
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 );
+800015d8:	fec42783          	lw	a5,-20(s0)
+800015dc:	0007a783          	lw	a5,0(a5)
+800015e0:	00878793          	addi	a5,a5,8
+800015e4:	00100693          	li	a3,1
+800015e8:	00200613          	li	a2,2
+800015ec:	00100593          	li	a1,1
+800015f0:	00078513          	mv	a0,a5
+800015f4:	ad1ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:106
+}
+800015f8:	00000013          	nop
+800015fc:	01c12083          	lw	ra,28(sp)
+80001600:	01812403          	lw	s0,24(sp)
+80001604:	02010113          	addi	sp,sp,32
+80001608:	00008067          	ret
+
+8000160c <TMR_clear_int>:
+TMR_clear_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:117
+void
+TMR_clear_int
+(
+    timer_instance_t * this_timer
+)
+{
+8000160c:	fe010113          	addi	sp,sp,-32
+80001610:	00112e23          	sw	ra,28(sp)
+80001614:	00812c23          	sw	s0,24(sp)
+80001618:	02010413          	addi	s0,sp,32
+8000161c:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001620:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001624:	0007a783          	lw	a5,0(a5)
+80001628:	fec42703          	lw	a4,-20(s0)
+8000162c:	00f71463          	bne	a4,a5,80001634 <TMR_clear_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118 (discriminator 1)
+80001630:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:120
+    
+    HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 );
+80001634:	fec42783          	lw	a5,-20(s0)
+80001638:	0007a783          	lw	a5,0(a5)
+8000163c:	01078793          	addi	a5,a5,16
+80001640:	00100593          	li	a1,1
+80001644:	00078513          	mv	a0,a5
+80001648:	a6dff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:121
+}
+8000164c:	00000013          	nop
+80001650:	01c12083          	lw	ra,28(sp)
+80001654:	01812403          	lw	s0,24(sp)
+80001658:	02010113          	addi	sp,sp,32
+8000165c:	00008067          	ret
+
+80001660 <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+80001660:	fd010113          	addi	sp,sp,-48
+80001664:	02112623          	sw	ra,44(sp)
+80001668:	02812423          	sw	s0,40(sp)
+8000166c:	03010413          	addi	s0,sp,48
+80001670:	fca42e23          	sw	a0,-36(s0)
+80001674:	fcb42c23          	sw	a1,-40(s0)
+80001678:	fcc42a23          	sw	a2,-44(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:38
+    uint8_t i = 0;
+8000167c:	fe0407a3          	sb	zero,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:39
+    addr_t cfg_reg_addr = base_addr;
+80001680:	fd842783          	lw	a5,-40(s0)
+80001684:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    
+    this_gpio->base_addr = base_addr;
+80001688:	fdc42783          	lw	a5,-36(s0)
+8000168c:	fd842703          	lw	a4,-40(s0)
+80001690:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+80001694:	fdc42783          	lw	a5,-36(s0)
+80001698:	fd442703          	lw	a4,-44(s0)
+8000169c:	00e7a223          	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016a0:	fe0407a3          	sb	zero,-17(s0)
+800016a4:	fd842783          	lw	a5,-40(s0)
+800016a8:	fef42423          	sw	a5,-24(s0)
+800016ac:	0280006f          	j	800016d4 <GPIO_init+0x74>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+800016b0:	00000593          	li	a1,0
+800016b4:	fe842503          	lw	a0,-24(s0)
+800016b8:	a8dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+800016bc:	fe842783          	lw	a5,-24(s0)
+800016c0:	00478793          	addi	a5,a5,4
+800016c4:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016c8:	fef44783          	lbu	a5,-17(s0)
+800016cc:	00178793          	addi	a5,a5,1
+800016d0:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 1)
+800016d4:	fef44703          	lbu	a4,-17(s0)
+800016d8:	01f00793          	li	a5,31
+800016dc:	fce7fae3          	bgeu	a5,a4,800016b0 <GPIO_init+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+800016e0:	fdc42783          	lw	a5,-36(s0)
+800016e4:	0047a783          	lw	a5,4(a5)
+800016e8:	00100713          	li	a4,1
+800016ec:	02e78663          	beq	a5,a4,80001718 <GPIO_init+0xb8>
+800016f0:	06078263          	beqz	a5,80001754 <GPIO_init+0xf4>
+800016f4:	00200713          	li	a4,2
+800016f8:	0ce79063          	bne	a5,a4,800017b8 <GPIO_init+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+800016fc:	fdc42783          	lw	a5,-36(s0)
+80001700:	0007a783          	lw	a5,0(a5)
+80001704:	08078793          	addi	a5,a5,128
+80001708:	fff00593          	li	a1,-1
+8000170c:	00078513          	mv	a0,a5
+80001710:	9a5ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:55
+            break;
+80001714:	0ac0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+80001718:	fdc42783          	lw	a5,-36(s0)
+8000171c:	0007a783          	lw	a5,0(a5)
+80001720:	08078713          	addi	a4,a5,128
+80001724:	000107b7          	lui	a5,0x10
+80001728:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+8000172c:	00070513          	mv	a0,a4
+80001730:	9cdff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80001734:	fdc42783          	lw	a5,-36(s0)
+80001738:	0007a783          	lw	a5,0(a5)
+8000173c:	08478713          	addi	a4,a5,132
+80001740:	000107b7          	lui	a5,0x10
+80001744:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+80001748:	00070513          	mv	a0,a4
+8000174c:	9b1ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:60
+            break;
+80001750:	0700006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+80001754:	fdc42783          	lw	a5,-36(s0)
+80001758:	0007a783          	lw	a5,0(a5)
+8000175c:	08078793          	addi	a5,a5,128
+80001760:	0ff00593          	li	a1,255
+80001764:	00078513          	mv	a0,a5
+80001768:	9ddff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+8000176c:	fdc42783          	lw	a5,-36(s0)
+80001770:	0007a783          	lw	a5,0(a5)
+80001774:	08478793          	addi	a5,a5,132
+80001778:	0ff00593          	li	a1,255
+8000177c:	00078513          	mv	a0,a5
+80001780:	9c5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+80001784:	fdc42783          	lw	a5,-36(s0)
+80001788:	0007a783          	lw	a5,0(a5)
+8000178c:	08878793          	addi	a5,a5,136
+80001790:	0ff00593          	li	a1,255
+80001794:	00078513          	mv	a0,a5
+80001798:	9adff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+8000179c:	fdc42783          	lw	a5,-36(s0)
+800017a0:	0007a783          	lw	a5,0(a5)
+800017a4:	08c78793          	addi	a5,a5,140
+800017a8:	0ff00593          	li	a1,255
+800017ac:	00078513          	mv	a0,a5
+800017b0:	995ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:67
+            break;
+800017b4:	00c0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:70 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+800017b8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:71 (discriminator 1)
+            break;
+800017bc:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+    }
+}
+800017c0:	00000013          	nop
+800017c4:	02c12083          	lw	ra,44(sp)
+800017c8:	02812403          	lw	s0,40(sp)
+800017cc:	03010113          	addi	sp,sp,48
+800017d0:	00008067          	ret
+
+800017d4 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+void GPIO_set_outputs
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+800017d4:	fe010113          	addi	sp,sp,-32
+800017d8:	00112e23          	sw	ra,28(sp)
+800017dc:	00812c23          	sw	s0,24(sp)
+800017e0:	02010413          	addi	s0,sp,32
+800017e4:	fea42623          	sw	a0,-20(s0)
+800017e8:	feb42423          	sw	a1,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+800017ec:	fec42783          	lw	a5,-20(s0)
+800017f0:	0047a783          	lw	a5,4(a5)
+800017f4:	00100713          	li	a4,1
+800017f8:	02e78663          	beq	a5,a4,80001824 <GPIO_set_outputs+0x50>
+800017fc:	06078c63          	beqz	a5,80001874 <GPIO_set_outputs+0xa0>
+80001800:	00200713          	li	a4,2
+80001804:	10e79063          	bne	a5,a4,80001904 <GPIO_set_outputs+0x130>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80001808:	fec42783          	lw	a5,-20(s0)
+8000180c:	0007a783          	lw	a5,0(a5)
+80001810:	0a078793          	addi	a5,a5,160
+80001814:	fe842583          	lw	a1,-24(s0)
+80001818:	00078513          	mv	a0,a5
+8000181c:	899ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:119
+            break;
+80001820:	0ec0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+80001824:	fec42783          	lw	a5,-20(s0)
+80001828:	0007a783          	lw	a5,0(a5)
+8000182c:	0a078793          	addi	a5,a5,160
+80001830:	fe842703          	lw	a4,-24(s0)
+80001834:	01071713          	slli	a4,a4,0x10
+80001838:	01075713          	srli	a4,a4,0x10
+8000183c:	00070593          	mv	a1,a4
+80001840:	00078513          	mv	a0,a5
+80001844:	8b9ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80001848:	fec42783          	lw	a5,-20(s0)
+8000184c:	0007a783          	lw	a5,0(a5)
+80001850:	0a478713          	addi	a4,a5,164
+80001854:	fe842783          	lw	a5,-24(s0)
+80001858:	0107d793          	srli	a5,a5,0x10
+8000185c:	01079793          	slli	a5,a5,0x10
+80001860:	0107d793          	srli	a5,a5,0x10
+80001864:	00078593          	mv	a1,a5
+80001868:	00070513          	mv	a0,a4
+8000186c:	891ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:124
+            break;
+80001870:	09c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+80001874:	fec42783          	lw	a5,-20(s0)
+80001878:	0007a783          	lw	a5,0(a5)
+8000187c:	0a078793          	addi	a5,a5,160
+80001880:	fe842703          	lw	a4,-24(s0)
+80001884:	0ff77713          	andi	a4,a4,255
+80001888:	00070593          	mv	a1,a4
+8000188c:	00078513          	mv	a0,a5
+80001890:	8b5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+80001894:	fec42783          	lw	a5,-20(s0)
+80001898:	0007a783          	lw	a5,0(a5)
+8000189c:	0a478713          	addi	a4,a5,164
+800018a0:	fe842783          	lw	a5,-24(s0)
+800018a4:	0087d793          	srli	a5,a5,0x8
+800018a8:	0ff7f793          	andi	a5,a5,255
+800018ac:	00078593          	mv	a1,a5
+800018b0:	00070513          	mv	a0,a4
+800018b4:	891ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+800018b8:	fec42783          	lw	a5,-20(s0)
+800018bc:	0007a783          	lw	a5,0(a5)
+800018c0:	0a878713          	addi	a4,a5,168
+800018c4:	fe842783          	lw	a5,-24(s0)
+800018c8:	0107d793          	srli	a5,a5,0x10
+800018cc:	0ff7f793          	andi	a5,a5,255
+800018d0:	00078593          	mv	a1,a5
+800018d4:	00070513          	mv	a0,a4
+800018d8:	86dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+800018dc:	fec42783          	lw	a5,-20(s0)
+800018e0:	0007a783          	lw	a5,0(a5)
+800018e4:	0ac78713          	addi	a4,a5,172
+800018e8:	fe842783          	lw	a5,-24(s0)
+800018ec:	0187d793          	srli	a5,a5,0x18
+800018f0:	0ff7f793          	andi	a5,a5,255
+800018f4:	00078593          	mv	a1,a5
+800018f8:	00070513          	mv	a0,a4
+800018fc:	849ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:131
+            break;
+80001900:	00c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:134 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001904:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:135 (discriminator 1)
+            break;
+80001908:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145
+     * the expected value may indicate that some of the GPIOs may not exist due to
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+8000190c:	fec42503          	lw	a0,-20(s0)
+80001910:	028000ef          	jal	ra,80001938 <GPIO_get_outputs>
+80001914:	00050713          	mv	a4,a0
+80001918:	fe842783          	lw	a5,-24(s0)
+8000191c:	00e78463          	beq	a5,a4,80001924 <GPIO_set_outputs+0x150>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145 (discriminator 1)
+80001920:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001924:	00000013          	nop
+80001928:	01c12083          	lw	ra,28(sp)
+8000192c:	01812403          	lw	s0,24(sp)
+80001930:	02010113          	addi	sp,sp,32
+80001934:	00008067          	ret
+
+80001938 <GPIO_get_outputs>:
+GPIO_get_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:193
+ */
+uint32_t GPIO_get_outputs
+(
+    gpio_instance_t *   this_gpio
+)
+{
+80001938:	fd010113          	addi	sp,sp,-48
+8000193c:	02112623          	sw	ra,44(sp)
+80001940:	02812423          	sw	s0,40(sp)
+80001944:	03010413          	addi	s0,sp,48
+80001948:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:194
+    uint32_t gpio_out = 0;
+8000194c:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:196
+    
+    switch( this_gpio->apb_bus_width )
+80001950:	fdc42783          	lw	a5,-36(s0)
+80001954:	0047a783          	lw	a5,4(a5)
+80001958:	00100713          	li	a4,1
+8000195c:	02e78663          	beq	a5,a4,80001988 <GPIO_get_outputs+0x50>
+80001960:	08078063          	beqz	a5,800019e0 <GPIO_get_outputs+0xa8>
+80001964:	00200713          	li	a4,2
+80001968:	12e79463          	bne	a5,a4,80001a90 <GPIO_get_outputs+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:199
+    {
+        case GPIO_APB_32_BITS_BUS:
+            gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
+8000196c:	fdc42783          	lw	a5,-36(s0)
+80001970:	0007a783          	lw	a5,0(a5)
+80001974:	0a078793          	addi	a5,a5,160
+80001978:	00078513          	mv	a0,a5
+8000197c:	f40ff0ef          	jal	ra,800010bc <HW_get_32bit_reg>
+80001980:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:200
+            break;
+80001984:	1140006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:203
+            
+        case GPIO_APB_16_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+80001988:	fdc42783          	lw	a5,-36(s0)
+8000198c:	0007a783          	lw	a5,0(a5)
+80001990:	0a078793          	addi	a5,a5,160
+80001994:	00078513          	mv	a0,a5
+80001998:	f6cff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+8000199c:	00050793          	mv	a5,a0
+800019a0:	00078713          	mv	a4,a5
+800019a4:	fec42783          	lw	a5,-20(s0)
+800019a8:	00e7e7b3          	or	a5,a5,a4
+800019ac:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:204
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
+800019b0:	fdc42783          	lw	a5,-36(s0)
+800019b4:	0007a783          	lw	a5,0(a5)
+800019b8:	0a478793          	addi	a5,a5,164
+800019bc:	00078513          	mv	a0,a5
+800019c0:	f44ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019c4:	00050793          	mv	a5,a0
+800019c8:	01079793          	slli	a5,a5,0x10
+800019cc:	00078713          	mv	a4,a5
+800019d0:	fec42783          	lw	a5,-20(s0)
+800019d4:	00e7e7b3          	or	a5,a5,a4
+800019d8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:205
+            break;
+800019dc:	0bc0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:208
+            
+        case GPIO_APB_8_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+800019e0:	fdc42783          	lw	a5,-36(s0)
+800019e4:	0007a783          	lw	a5,0(a5)
+800019e8:	0a078793          	addi	a5,a5,160
+800019ec:	00078513          	mv	a0,a5
+800019f0:	f14ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019f4:	00050793          	mv	a5,a0
+800019f8:	00078713          	mv	a4,a5
+800019fc:	fec42783          	lw	a5,-20(s0)
+80001a00:	00e7e7b3          	or	a5,a5,a4
+80001a04:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:209
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
+80001a08:	fdc42783          	lw	a5,-36(s0)
+80001a0c:	0007a783          	lw	a5,0(a5)
+80001a10:	0a478793          	addi	a5,a5,164
+80001a14:	00078513          	mv	a0,a5
+80001a18:	eecff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a1c:	00050793          	mv	a5,a0
+80001a20:	00879793          	slli	a5,a5,0x8
+80001a24:	00078713          	mv	a4,a5
+80001a28:	fec42783          	lw	a5,-20(s0)
+80001a2c:	00e7e7b3          	or	a5,a5,a4
+80001a30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:210
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
+80001a34:	fdc42783          	lw	a5,-36(s0)
+80001a38:	0007a783          	lw	a5,0(a5)
+80001a3c:	0a878793          	addi	a5,a5,168
+80001a40:	00078513          	mv	a0,a5
+80001a44:	ec0ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a48:	00050793          	mv	a5,a0
+80001a4c:	01079793          	slli	a5,a5,0x10
+80001a50:	00078713          	mv	a4,a5
+80001a54:	fec42783          	lw	a5,-20(s0)
+80001a58:	00e7e7b3          	or	a5,a5,a4
+80001a5c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:211
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
+80001a60:	fdc42783          	lw	a5,-36(s0)
+80001a64:	0007a783          	lw	a5,0(a5)
+80001a68:	0ac78793          	addi	a5,a5,172
+80001a6c:	00078513          	mv	a0,a5
+80001a70:	e94ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a74:	00050793          	mv	a5,a0
+80001a78:	01879793          	slli	a5,a5,0x18
+80001a7c:	00078713          	mv	a4,a5
+80001a80:	fec42783          	lw	a5,-20(s0)
+80001a84:	00e7e7b3          	or	a5,a5,a4
+80001a88:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:212
+            break;
+80001a8c:	00c0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:215 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001a90:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:216 (discriminator 1)
+            break;
+80001a94:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:219
+    }
+    
+    return gpio_out;
+80001a98:	fec42783          	lw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:220
+}
+80001a9c:	00078513          	mv	a0,a5
+80001aa0:	02c12083          	lw	ra,44(sp)
+80001aa4:	02812403          	lw	s0,40(sp)
+80001aa8:	03010113          	addi	sp,sp,48
+80001aac:	00008067          	ret
+
+80001ab0 <MRV_enable_local_irq>:
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:586
+{
+80001ab0:	fd010113          	addi	sp,sp,-48
+80001ab4:	02812623          	sw	s0,44(sp)
+80001ab8:	03010413          	addi	s0,sp,48
+80001abc:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80001ac0:	fdc42783          	lw	a5,-36(s0)
+80001ac4:	3047a7f3          	csrrs	a5,mie,a5
+80001ac8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:588
+}
+80001acc:	00000013          	nop
+80001ad0:	02c12403          	lw	s0,44(sp)
+80001ad4:	03010113          	addi	sp,sp,48
+80001ad8:	00008067          	ret
+
+80001adc <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:48
+/*--------------------------------------------------------------------------------------------------
+ * Interrupt handler for the MIV_RV32 MSYS_EI interrupt connected to CoreTimer 0
+ */
+uint8_t
+MSYS_EI0_IRQHandler(void)
+{
+80001adc:	ff010113          	addi	sp,sp,-16
+80001ae0:	00112623          	sw	ra,12(sp)
+80001ae4:	00812423          	sw	s0,8(sp)
+80001ae8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:61
+     */
+
+    /* LEDs 1 - 4 are connected to GPIO pins 0 - 3.
+     * Invert the state of GPIO pins 0 - 3 every time the interrupt is triggered
+     */
+    gpio_pins_state = gpio_pins_state ^ (GPIO_0_MASK | GPIO_1_MASK | GPIO_2_MASK | GPIO_3_MASK);
+80001aec:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001af0:	0007a783          	lw	a5,0(a5)
+80001af4:	00f7c713          	xori	a4,a5,15
+80001af8:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001afc:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:63
+
+    GPIO_set_outputs(&g_gpio, gpio_pins_state);
+80001b00:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001b04:	0007a783          	lw	a5,0(a5)
+80001b08:	00078593          	mv	a1,a5
+80001b0c:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b10:	cc5ff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:66
+
+    /* Clear the interrupt within the timer */
+    TMR_clear_int(&g_core_timer_0);
+80001b14:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001b18:	af5ff0ef          	jal	ra,8000160c <TMR_clear_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:67
+    return (EXT_IRQ_KEEP_ENABLED);
+80001b1c:	00000793          	li	a5,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:68
+}
+80001b20:	00078513          	mv	a0,a5
+80001b24:	00c12083          	lw	ra,12(sp)
+80001b28:	00812403          	lw	s0,8(sp)
+80001b2c:	01010113          	addi	sp,sp,16
+80001b30:	00008067          	ret
+
+80001b34 <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:72
+
+int
+main(void)
+{
+80001b34:	ff010113          	addi	sp,sp,-16
+80001b38:	00112623          	sw	ra,12(sp)
+80001b3c:	00812423          	sw	s0,8(sp)
+80001b40:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:74
+    /* Initialise the UART and print the greeting message*/
+    UART_init(&g_core_uart_0, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, DATA_8_BITS | NO_PARITY);
+80001b44:	00100693          	li	a3,1
+80001b48:	01a00613          	li	a2,26
+80001b4c:	710005b7          	lui	a1,0x71000
+80001b50:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b54:	e38ff0ef          	jal	ra,8000118c <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:76
+
+    UART_polled_tx_string(&g_core_uart_0, g_message);
+80001b58:	00000597          	auipc	a1,0x0
+80001b5c:	0a858593          	addi	a1,a1,168 # 80001c00 <__data_load>
+80001b60:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b64:	801ff0ef          	jal	ra,80001364 <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:79
+
+    /* Enable local interrupt for the MSYS_EI interrupt pin */
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
+80001b68:	01000537          	lui	a0,0x1000
+80001b6c:	f45ff0ef          	jal	ra,80001ab0 <MRV_enable_local_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:82
+
+    /* Initialise the GPIO */
+    GPIO_init(&g_gpio, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+80001b70:	00200613          	li	a2,2
+80001b74:	750005b7          	lui	a1,0x75000
+80001b78:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b7c:	ae5ff0ef          	jal	ra,80001660 <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:85
+
+    /* Configure the GPIOs, turn them all off initially */
+    GPIO_set_outputs(&g_gpio, 0x00u);
+80001b80:	00000593          	li	a1,0
+80001b84:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b88:	c4dff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:88
+
+    /* Initialise and configure the timer */
+    TMR_init(&g_core_timer_0,
+80001b8c:	000147b7          	lui	a5,0x14
+80001b90:	c9a78713          	addi	a4,a5,-870 # 13c9a <RAM_SIZE+0xbc9a>
+80001b94:	00900693          	li	a3,9
+80001b98:	00000613          	li	a2,0
+80001b9c:	730005b7          	lui	a1,0x73000
+80001ba0:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001ba4:	889ff0ef          	jal	ra,8000142c <TMR_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:95
+             TMR_CONTINUOUS_MODE,
+             PRESCALER_DIV_1024,
+             TIMER_LOAD_VALUE);
+
+    /* Enable interrupts in general.*/
+    HAL_enable_interrupts();
+80001ba8:	ce4ff0ef          	jal	ra,8000108c <HAL_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:98
+
+    /* Enable the timer to generate interrupts */
+    TMR_enable_int(&g_core_timer_0);
+80001bac:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb0:	a01ff0ef          	jal	ra,800015b0 <TMR_enable_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:101
+
+    /* Start the timer */
+    TMR_start(&g_core_timer_0);
+80001bb4:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb8:	99dff0ef          	jal	ra,80001554 <TMR_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:103 (discriminator 1)
+
+    while (1u)
+80001bbc:	0000006f          	j	80001bbc <main+0x88>
+
+80001bc0 <local_irq_handler_table>:
+80001bc0:	80000f24 80000f08 80000f40 80001038     $.......@...8...
+80001bd0:	80000fe8 80000fe8 80000fe8 80000fe8     ................
+80001be0:	80001adc 80000f5c 80000f78 80000f94     ....\...x.......
+80001bf0:	80000fb0 80000fcc 80001000 8000101c     ................
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.hex
index 2ad3820..d1cdff8 100644
--- a/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.hex
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.hex
@@ -1,391 +1,797 @@
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.lst
new file mode 100644
index 0000000..cb38eb2
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG2/hex/miv-rv32i-systick-blinky.lst
@@ -0,0 +1,5184 @@
+
+miv-rv32i-systick-blinky.elf:     file format elf32-littleriscv
+miv-rv32i-systick-blinky.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00003134 memsz 0x00003134 flags r-x
+    LOAD off    0x00005000 vaddr 0x80004000 paddr 0x80003140 align 2**12
+         filesz 0x00000070 memsz 0x000000a0 flags rw-
+    LOAD off    0x000050a0 vaddr 0x800040a0 paddr 0x800031b0 align 2**12
+         filesz 0x00000000 memsz 0x00000060 flags rw-
+    LOAD off    0x00005100 vaddr 0x80004100 paddr 0x800031b0 align 2**12
+         filesz 0x00000000 memsz 0x00000400 flags rw-
+
+Sections:
+Idx Name                       Size      VMA       LMA       File off  Algn  Flags
+  0 .entry                     000009e0  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text                      00002750  800009e0  800009e0  000019e0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata2._global_impure_ptr 00000004  80003130  80003130  00004130  2**2  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .sdata                     00000010  80004000  80003140  00005000  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .data                      00000060  80004010  80003150  00005010  2**4  CONTENTS, ALLOC, LOAD, DATA
+  5 .sbss                      00000030  80004070  800031b0  00005070  2**4  ALLOC
+  6 .bss                       00000060  800040a0  800031b0  000050a0  2**4  ALLOC
+  7 .heap                      00000000  80004100  80004100  00005070  2**4  CONTENTS
+  8 .stack                     00000400  80004100  800031b0  00005100  2**4  ALLOC
+  9 .riscv.attributes          00000021  00000000  00000000  00005070  2**0  CONTENTS, READONLY
+ 10 .comment                   00000051  00000000  00000000  00005091  2**0  CONTENTS, READONLY
+ 11 .debug_line                000034f7  00000000  00000000  000050e2  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_info                00003c3c  00000000  00000000  000085d9  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev              00001098  00000000  00000000  0000c215  2**0  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges             000002b0  00000000  00000000  0000d2b0  2**3  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_str                 00001393  00000000  00000000  0000d560  2**0  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_ranges              00000310  00000000  00000000  0000e8f8  2**3  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_loc                 00001863  00000000  00000000  0000ec08  2**0  CONTENTS, READONLY, DEBUGGING
+ 18 .debug_frame               000010d4  00000000  00000000  0001046c  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+800009e0 l    d  .text	00000000 .text
+80003130 l    d  .sdata2._global_impure_ptr	00000000 .sdata2._global_impure_ptr
+80004000 l    d  .sdata	00000000 .sdata
+80004010 l    d  .data	00000000 .data
+80004070 l    d  .sbss	00000000 .sbss
+800040a0 l    d  .bss	00000000 .bss
+80004100 l    d  .heap	00000000 .heap
+80004100 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_loc	00000000 .debug_loc
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+800009e0 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+80000124 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+800001b0 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+8000023c l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800002c8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000354 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+800008cc l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+80000728 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+800003e0 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+8000046c l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800004f8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000584 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+80000610 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+8000069c l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+800007b4 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000840 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000958 l       .entry	00000000 generic_restore
+80000a30 l       .text	00000000 ima_cores_setup
+80000a78 l       .text	00000000 vector_address_not_matching
+80000a3c l       .text	00000000 generic_reset_handling
+80000af4 l       .text	00000000 block_copy
+80000a7c l       .text	00000000 initializations
+80000ad4 l       .text	00000000 zeroize_block
+80000b1c l       .text	00000000 block_copy_error
+80000ae4 l       .text	00000000 zeroize_loop
+80000b04 l       .text	00000000 block_copy_loop
+80000b20 l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000b24 l     F .text	0000003c MRV_read_mtime
+80004070 l     O .sbss	00000008 g_systick_cmp_value
+80004078 l     O .sbss	00000008 g_systick_increment
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+80000da0 l     F .text	00000010 Software_IRQHandler.localalias.0
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+80004000 l     O .sdata	00000004 curbrk.2478
+00000000 l    df *ABS*	00000000 hal_irq.c
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80004084 l     O .sbss	00000004 interrupt_counter.2878
+80004088 l     O .sbss	00000004 val.2879
+00000000 l    df *ABS*	00000000 printf.c
+00000000 l    df *ABS*	00000000 sysisatty.c
+00000000 l    df *ABS*	00000000 writer.c
+00000000 l    df *ABS*	00000000 findfp.c
+80001544 l     F .text	00000088 std
+00000000 l    df *ABS*	00000000 fwalk.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 nano-vfprintf.c
+800019e8 l     F .text	0000003c __sfputc_r
+00000000 l    df *ABS*	00000000 nano-vfprintf_i.c
+00000000 l    df *ABS*	00000000 sbrkr.c
+00000000 l    df *ABS*	00000000 stdio.c
+00000000 l    df *ABS*	00000000 wbuf.c
+00000000 l    df *ABS*	00000000 wsetup.c
+00000000 l    df *ABS*	00000000 closer.c
+00000000 l    df *ABS*	00000000 fflush.c
+00000000 l    df *ABS*	00000000 lseekr.c
+00000000 l    df *ABS*	00000000 makebuf.c
+00000000 l    df *ABS*	00000000 memchr.c
+00000000 l    df *ABS*	00000000 mlock.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 readr.c
+00000000 l    df *ABS*	00000000 fstatr.c
+00000000 l    df *ABS*	00000000 isattyr.c
+00000000 l    df *ABS*	00000000 impure.c
+80004010 l     O .data	00000060 impure_data
+00000000 l    df *ABS*	00000000 reent.c
+80002e68 g     F .text	00000044 _isatty_r
+80002adc g     F .text	0000004c _lseek_r
+00000400 g       *ABS*	00000000 STACK_SIZE
+80001478 g     F .text	0000007c printf
+80004800 g       .sdata	00000000 __global_pointer$
+80001014 g     F .text	000000c0 UART_get_rx
+800024f4 g     F .text	00000058 __sseek
+80001644 g     F .text	000000b4 __sinit
+80002554 g     F .text	00000138 __swbuf_r
+800015d8 g     F .text	0000006c __sfmoreglue
+80002ccc g     F .text	00000004 __malloc_unlock
+80003150 g       *ABS*	00000000 __data_load
+80001358 g     F .text	00000054 SysTick_Handler
+80004004 g     O .sdata	00000004 g_hello_msg
+80000f58 g       .text	00000000 HW_get_8bit_reg_field
+80004070 g       .sbss	00000000 __sbss_start
+800040a0 g     O .bss	00000040 g_rx_buff
+80000d0c g     F .text	00000024 handle_local_ei_interrupts
+80002e20 g     F .text	00000048 _fstat_r
+800040f0 g     O .bss	00000004 errno
+80000e90 g       .text	00000000 HW_set_32bit_reg
+800040e0 g     O .bss	00000008 g_gpio_out
+800015cc g     F .text	0000000c _cleanup_r
+80004000 g       .sdata	00000000 __sdata_start
+80000dd0  w    F .text	00000004 MSYS_EI4_IRQHandler
+800040e8 g     O .bss	00000008 g_uart
+80000f30 g       .text	00000000 HW_set_8bit_reg_field
+80000dbc  w    F .text	00000004 SUBSYS_IRQHandler
+800014f4 g     F .text	00000004 isatty
+80000e34 g     F .text	00000038 _fstat
+80000d30 g     F .text	00000068 handle_trap
+80000ddc  w    F .text	00000004 MSYS_EI6_IRQHandler
+800023dc g     F .text	00000044 _sbrk_r
+80000de4  w    F .text	00000004 SUBSYSR_IRQHandler
+80002dd4 g     F .text	0000004c _read_r
+80000b60 g     F .text	000000e8 MRV_systick_config
+80000db4  w    F .text	00000004 MGECI_IRQHandler
+80004100 g       .heap	00000000 _heap_end
+80002eb0 g     O .text	00000040 local_irq_handler_table
+80000de0  w    F .text	00000004 MSYS_EI7_IRQHandler
+80000e24 g     F .text	00000008 _isatty
+80003130 g     O .sdata2._global_impure_ptr	00000004 _global_impure_ptr
+80004100 g       .bss	00000000 __bss_end
+80000dec g     F .text	00000038 _sbrk
+80000d98 g     F .text	00000004 _init
+80000f20 g       .text	00000000 HW_set_8bit_reg
+80000f28 g       .text	00000000 HW_get_8bit_reg
+80000dc4  w    F .text	00000004 MSYS_EI1_IRQHandler
+800040a0 g       .sbss	00000000 __sbss_end
+80000ea0 g       .text	00000000 HW_set_32bit_reg_field
+80004500 g       .stack	00000000 __stack_top
+8000308c g     O .text	00000020 __sf_fake_stderr
+800010d4 g     F .text	00000068 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001a24 g     F .text	00000074 __sfputs_r
+80002ca4 g     F .text	00000024 memchr
+80002cd0 g     F .text	00000104 _free_r
+80001258 g     F .text	000000ec GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+80000e6c g     F .text	0000000c _lseek
+80000c48 g     F .text	0000009c handle_m_timer_interrupt
+80003140 g       *ABS*	00000000 __sdata_load
+80004070 g       .data	00000000 __data_end
+80000ec8 g       .text	00000000 HW_get_32bit_reg_field
+8000280c g     F .text	00000044 _close_r
+8000113c g     F .text	0000011c GPIO_init
+8000268c g     F .text	00000180 __swsetup_r
+800016f8 g     F .text	000000f0 __sfp
+80002420 g     F .text	00000050 __sread
+80002cc8 g     F .text	00000004 __malloc_lock
+80002a3c g     F .text	000000a0 _fflush_r
+800030ac g     O .text	00000020 __sf_fake_stdin
+800040a0 g       .bss	00000000 __bss_start
+80000e88 g     F .text	00000008 HAL_enable_interrupts
+8000145c g     F .text	0000001c memset
+800013ac g     F .text	000000b0 main
+80000dd4  w    F .text	00000004 MSYS_EI5_IRQHandler
+8000254c g     F .text	00000008 __sclose
+8000189c g     F .text	0000014c _malloc_r
+80000db8  w    F .text	00000004 MGEUI_IRQHandler
+80000ee0 g       .text	00000000 HW_get_16bit_reg
+80004010 g       .sdata	00000000 __sdata_end
+80004100 g       .heap	00000000 __heap_end
+80004080 g     O .sbss	00000001 g_rx_size
+80000d9c g     F .text	00000004 _fini
+80001478 g     F .text	0000007c iprintf
+800014f8 g     F .text	0000004c _write_r
+80000ee8 g       .text	00000000 HW_set_16bit_reg_field
+80000dc8  w    F .text	00000004 MSYS_EI2_IRQHandler
+80001e60 g     F .text	000001b0 _printf_common
+80004008 g     O .sdata	00000004 _impure_ptr
+80004100 g       .stack	00000000 __stack_bottom
+80002850 g     F .text	000001ec __sflush_r
+80001344 g     F .text	00000014 Software_IRQHandler
+80004100 g       .heap	00000000 __heap_start
+80002b28 g     F .text	0000008c __swhatbuf_r
+80000e80 g     F .text	00000008 _write
+80004100 g       .bss	00000000 _end
+80000dd8  w    F .text	00000004 Reserved_IRQHandler
+80002470 g     F .text	00000084 __swrite
+80001a98 g     F .text	000003c8 _vfiprintf_r
+800017e8 g     F .text	000000b4 _fwalk_reent
+80000f68 g     F .text	000000ac UART_init
+800030cc g     O .text	00000020 __sf_fake_stdout
+80000e98 g       .text	00000000 HW_get_32bit_reg
+80000e78 g     F .text	00000008 _read
+80000de8 g     F .text	00000004 _exit
+80000ed8 g       .text	00000000 HW_set_16bit_reg
+80002bb4 g     F .text	000000f0 __smakebuf_r
+80002010 g     F .text	000003cc _printf_i
+80000dcc  w    F .text	00000004 MSYS_EI3_IRQHandler
+80004090 g     O .sbss	00000004 __malloc_sbrk_start
+80000db0  w    F .text	00000004 External_IRQHandler
+80004010 g       .data	00000000 __data_start
+8000408c g     O .sbss	00000004 __malloc_free_list
+80001a98 g     F .text	000003c8 _vfprintf_r
+80000ce4 g     F .text	00000028 handle_m_soft_interrupt
+80000f10 g       .text	00000000 HW_get_16bit_reg_field
+80000e2c g     F .text	00000008 _close
+80000dc0  w    F .text	00000004 MSYS_EI0_IRQHandler
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:114
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	1e10006f          	j	800009e0 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:125
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:131
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	1140006f          	j	80000124 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:140
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	1900006f          	j	800001b0 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:149
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	20c0006f          	j	8000023c <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:160
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	2840006f          	j	800002c8 <vector_MGEUI_trap_handler>
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:166
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	30c0006f          	j	80000354 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:178
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	0710006f          	j	800008cc <vector_SUBSYSR_IRQHandler>
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:185
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	6c80006f          	j	80000728 <vector_SUBSYS_IRQHandler>
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:192
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	37c0006f          	j	800003e0 <vector_MSYS_EI0_trap_handler>
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:198
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	4040006f          	j	8000046c <vector_MSYS_EI1_trap_handler>
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:204
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	48c0006f          	j	800004f8 <vector_MSYS_EI2_trap_handler>
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:210
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	5140006f          	j	80000584 <vector_MSYS_EI3_trap_handler>
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:216
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	59c0006f          	j	80000610 <vector_MSYS_EI4_trap_handler>
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:222
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	6240006f          	j	8000069c <vector_MSYS_EI5_trap_handler>
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:229
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	7380006f          	j	800007b4 <vector_MSYS_EI6_trap_handler>
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:239
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	7c00006f          	j	80000840 <vector_MSYS_EI7_trap_handler>
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	f8010113          	addi	sp,sp,-128
+80000094:	00112023          	sw	ra,0(sp)
+80000098:	00112023          	sw	ra,0(sp)
+8000009c:	00212223          	sw	sp,4(sp)
+800000a0:	00312423          	sw	gp,8(sp)
+800000a4:	00412623          	sw	tp,12(sp)
+800000a8:	00512823          	sw	t0,16(sp)
+800000ac:	00612a23          	sw	t1,20(sp)
+800000b0:	00712c23          	sw	t2,24(sp)
+800000b4:	00812e23          	sw	s0,28(sp)
+800000b8:	02912023          	sw	s1,32(sp)
+800000bc:	02a12223          	sw	a0,36(sp)
+800000c0:	02b12423          	sw	a1,40(sp)
+800000c4:	02c12623          	sw	a2,44(sp)
+800000c8:	02d12823          	sw	a3,48(sp)
+800000cc:	02e12a23          	sw	a4,52(sp)
+800000d0:	02f12c23          	sw	a5,56(sp)
+800000d4:	03012e23          	sw	a6,60(sp)
+800000d8:	05112023          	sw	a7,64(sp)
+800000dc:	05212223          	sw	s2,68(sp)
+800000e0:	05312423          	sw	s3,72(sp)
+800000e4:	05412623          	sw	s4,76(sp)
+800000e8:	05512823          	sw	s5,80(sp)
+800000ec:	05612a23          	sw	s6,84(sp)
+800000f0:	05712c23          	sw	s7,88(sp)
+800000f4:	05812e23          	sw	s8,92(sp)
+800000f8:	07912023          	sw	s9,96(sp)
+800000fc:	07a12223          	sw	s10,100(sp)
+80000100:	07b12423          	sw	s11,104(sp)
+80000104:	07c12623          	sw	t3,108(sp)
+80000108:	07d12823          	sw	t4,112(sp)
+8000010c:	07e12a23          	sw	t5,116(sp)
+80000110:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a0, mcause
+80000114:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  csrr a1, mepc
+80000118:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  jal handle_trap
+8000011c:	415000ef          	jal	ra,80000d30 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:252
+  j generic_restore
+80000120:	0390006f          	j	80000958 <generic_restore>
+
+80000124 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+80000124:	f8010113          	addi	sp,sp,-128
+80000128:	00112023          	sw	ra,0(sp)
+8000012c:	00112023          	sw	ra,0(sp)
+80000130:	00212223          	sw	sp,4(sp)
+80000134:	00312423          	sw	gp,8(sp)
+80000138:	00412623          	sw	tp,12(sp)
+8000013c:	00512823          	sw	t0,16(sp)
+80000140:	00612a23          	sw	t1,20(sp)
+80000144:	00712c23          	sw	t2,24(sp)
+80000148:	00812e23          	sw	s0,28(sp)
+8000014c:	02912023          	sw	s1,32(sp)
+80000150:	02a12223          	sw	a0,36(sp)
+80000154:	02b12423          	sw	a1,40(sp)
+80000158:	02c12623          	sw	a2,44(sp)
+8000015c:	02d12823          	sw	a3,48(sp)
+80000160:	02e12a23          	sw	a4,52(sp)
+80000164:	02f12c23          	sw	a5,56(sp)
+80000168:	03012e23          	sw	a6,60(sp)
+8000016c:	05112023          	sw	a7,64(sp)
+80000170:	05212223          	sw	s2,68(sp)
+80000174:	05312423          	sw	s3,72(sp)
+80000178:	05412623          	sw	s4,76(sp)
+8000017c:	05512823          	sw	s5,80(sp)
+80000180:	05612a23          	sw	s6,84(sp)
+80000184:	05712c23          	sw	s7,88(sp)
+80000188:	05812e23          	sw	s8,92(sp)
+8000018c:	07912023          	sw	s9,96(sp)
+80000190:	07a12223          	sw	s10,100(sp)
+80000194:	07b12423          	sw	s11,104(sp)
+80000198:	07c12623          	sw	t3,108(sp)
+8000019c:	07d12823          	sw	t4,112(sp)
+800001a0:	07e12a23          	sw	t5,116(sp)
+800001a4:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  jal handle_m_soft_interrupt
+800001a8:	33d000ef          	jal	ra,80000ce4 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:257
+  j generic_restore
+800001ac:	7ac0006f          	j	80000958 <generic_restore>
+
+800001b0 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+800001b0:	f8010113          	addi	sp,sp,-128
+800001b4:	00112023          	sw	ra,0(sp)
+800001b8:	00112023          	sw	ra,0(sp)
+800001bc:	00212223          	sw	sp,4(sp)
+800001c0:	00312423          	sw	gp,8(sp)
+800001c4:	00412623          	sw	tp,12(sp)
+800001c8:	00512823          	sw	t0,16(sp)
+800001cc:	00612a23          	sw	t1,20(sp)
+800001d0:	00712c23          	sw	t2,24(sp)
+800001d4:	00812e23          	sw	s0,28(sp)
+800001d8:	02912023          	sw	s1,32(sp)
+800001dc:	02a12223          	sw	a0,36(sp)
+800001e0:	02b12423          	sw	a1,40(sp)
+800001e4:	02c12623          	sw	a2,44(sp)
+800001e8:	02d12823          	sw	a3,48(sp)
+800001ec:	02e12a23          	sw	a4,52(sp)
+800001f0:	02f12c23          	sw	a5,56(sp)
+800001f4:	03012e23          	sw	a6,60(sp)
+800001f8:	05112023          	sw	a7,64(sp)
+800001fc:	05212223          	sw	s2,68(sp)
+80000200:	05312423          	sw	s3,72(sp)
+80000204:	05412623          	sw	s4,76(sp)
+80000208:	05512823          	sw	s5,80(sp)
+8000020c:	05612a23          	sw	s6,84(sp)
+80000210:	05712c23          	sw	s7,88(sp)
+80000214:	05812e23          	sw	s8,92(sp)
+80000218:	07912023          	sw	s9,96(sp)
+8000021c:	07a12223          	sw	s10,100(sp)
+80000220:	07b12423          	sw	s11,104(sp)
+80000224:	07c12623          	sw	t3,108(sp)
+80000228:	07d12823          	sw	t4,112(sp)
+8000022c:	07e12a23          	sw	t5,116(sp)
+80000230:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  jal handle_m_timer_interrupt
+80000234:	215000ef          	jal	ra,80000c48 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:262
+  j generic_restore
+80000238:	7200006f          	j	80000958 <generic_restore>
+
+8000023c <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:265
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+8000023c:	f8010113          	addi	sp,sp,-128
+80000240:	00112023          	sw	ra,0(sp)
+80000244:	00112023          	sw	ra,0(sp)
+80000248:	00212223          	sw	sp,4(sp)
+8000024c:	00312423          	sw	gp,8(sp)
+80000250:	00412623          	sw	tp,12(sp)
+80000254:	00512823          	sw	t0,16(sp)
+80000258:	00612a23          	sw	t1,20(sp)
+8000025c:	00712c23          	sw	t2,24(sp)
+80000260:	00812e23          	sw	s0,28(sp)
+80000264:	02912023          	sw	s1,32(sp)
+80000268:	02a12223          	sw	a0,36(sp)
+8000026c:	02b12423          	sw	a1,40(sp)
+80000270:	02c12623          	sw	a2,44(sp)
+80000274:	02d12823          	sw	a3,48(sp)
+80000278:	02e12a23          	sw	a4,52(sp)
+8000027c:	02f12c23          	sw	a5,56(sp)
+80000280:	03012e23          	sw	a6,60(sp)
+80000284:	05112023          	sw	a7,64(sp)
+80000288:	05212223          	sw	s2,68(sp)
+8000028c:	05312423          	sw	s3,72(sp)
+80000290:	05412623          	sw	s4,76(sp)
+80000294:	05512823          	sw	s5,80(sp)
+80000298:	05612a23          	sw	s6,84(sp)
+8000029c:	05712c23          	sw	s7,88(sp)
+800002a0:	05812e23          	sw	s8,92(sp)
+800002a4:	07912023          	sw	s9,96(sp)
+800002a8:	07a12223          	sw	s10,100(sp)
+800002ac:	07b12423          	sw	s11,104(sp)
+800002b0:	07c12623          	sw	t3,108(sp)
+800002b4:	07d12823          	sw	t4,112(sp)
+800002b8:	07e12a23          	sw	t5,116(sp)
+800002bc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:269
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800002c0:	2f1000ef          	jal	ra,80000db0 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:271
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800002c4:	6940006f          	j	80000958 <generic_restore>
+
+800002c8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800002c8:	f8010113          	addi	sp,sp,-128
+800002cc:	00112023          	sw	ra,0(sp)
+800002d0:	00112023          	sw	ra,0(sp)
+800002d4:	00212223          	sw	sp,4(sp)
+800002d8:	00312423          	sw	gp,8(sp)
+800002dc:	00412623          	sw	tp,12(sp)
+800002e0:	00512823          	sw	t0,16(sp)
+800002e4:	00612a23          	sw	t1,20(sp)
+800002e8:	00712c23          	sw	t2,24(sp)
+800002ec:	00812e23          	sw	s0,28(sp)
+800002f0:	02912023          	sw	s1,32(sp)
+800002f4:	02a12223          	sw	a0,36(sp)
+800002f8:	02b12423          	sw	a1,40(sp)
+800002fc:	02c12623          	sw	a2,44(sp)
+80000300:	02d12823          	sw	a3,48(sp)
+80000304:	02e12a23          	sw	a4,52(sp)
+80000308:	02f12c23          	sw	a5,56(sp)
+8000030c:	03012e23          	sw	a6,60(sp)
+80000310:	05112023          	sw	a7,64(sp)
+80000314:	05212223          	sw	s2,68(sp)
+80000318:	05312423          	sw	s3,72(sp)
+8000031c:	05412623          	sw	s4,76(sp)
+80000320:	05512823          	sw	s5,80(sp)
+80000324:	05612a23          	sw	s6,84(sp)
+80000328:	05712c23          	sw	s7,88(sp)
+8000032c:	05812e23          	sw	s8,92(sp)
+80000330:	07912023          	sw	s9,96(sp)
+80000334:	07a12223          	sw	s10,100(sp)
+80000338:	07b12423          	sw	s11,104(sp)
+8000033c:	07c12623          	sw	t3,108(sp)
+80000340:	07d12823          	sw	t4,112(sp)
+80000344:	07e12a23          	sw	t5,116(sp)
+80000348:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  jal MGEUI_IRQHandler
+8000034c:	26d000ef          	jal	ra,80000db8 <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:277
+  j generic_restore
+80000350:	6080006f          	j	80000958 <generic_restore>
+
+80000354 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000354:	f8010113          	addi	sp,sp,-128
+80000358:	00112023          	sw	ra,0(sp)
+8000035c:	00112023          	sw	ra,0(sp)
+80000360:	00212223          	sw	sp,4(sp)
+80000364:	00312423          	sw	gp,8(sp)
+80000368:	00412623          	sw	tp,12(sp)
+8000036c:	00512823          	sw	t0,16(sp)
+80000370:	00612a23          	sw	t1,20(sp)
+80000374:	00712c23          	sw	t2,24(sp)
+80000378:	00812e23          	sw	s0,28(sp)
+8000037c:	02912023          	sw	s1,32(sp)
+80000380:	02a12223          	sw	a0,36(sp)
+80000384:	02b12423          	sw	a1,40(sp)
+80000388:	02c12623          	sw	a2,44(sp)
+8000038c:	02d12823          	sw	a3,48(sp)
+80000390:	02e12a23          	sw	a4,52(sp)
+80000394:	02f12c23          	sw	a5,56(sp)
+80000398:	03012e23          	sw	a6,60(sp)
+8000039c:	05112023          	sw	a7,64(sp)
+800003a0:	05212223          	sw	s2,68(sp)
+800003a4:	05312423          	sw	s3,72(sp)
+800003a8:	05412623          	sw	s4,76(sp)
+800003ac:	05512823          	sw	s5,80(sp)
+800003b0:	05612a23          	sw	s6,84(sp)
+800003b4:	05712c23          	sw	s7,88(sp)
+800003b8:	05812e23          	sw	s8,92(sp)
+800003bc:	07912023          	sw	s9,96(sp)
+800003c0:	07a12223          	sw	s10,100(sp)
+800003c4:	07b12423          	sw	s11,104(sp)
+800003c8:	07c12623          	sw	t3,108(sp)
+800003cc:	07d12823          	sw	t4,112(sp)
+800003d0:	07e12a23          	sw	t5,116(sp)
+800003d4:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  jal MGECI_IRQHandler
+800003d8:	1dd000ef          	jal	ra,80000db4 <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:282
+  j generic_restore
+800003dc:	57c0006f          	j	80000958 <generic_restore>
+
+800003e0 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+800003e0:	f8010113          	addi	sp,sp,-128
+800003e4:	00112023          	sw	ra,0(sp)
+800003e8:	00112023          	sw	ra,0(sp)
+800003ec:	00212223          	sw	sp,4(sp)
+800003f0:	00312423          	sw	gp,8(sp)
+800003f4:	00412623          	sw	tp,12(sp)
+800003f8:	00512823          	sw	t0,16(sp)
+800003fc:	00612a23          	sw	t1,20(sp)
+80000400:	00712c23          	sw	t2,24(sp)
+80000404:	00812e23          	sw	s0,28(sp)
+80000408:	02912023          	sw	s1,32(sp)
+8000040c:	02a12223          	sw	a0,36(sp)
+80000410:	02b12423          	sw	a1,40(sp)
+80000414:	02c12623          	sw	a2,44(sp)
+80000418:	02d12823          	sw	a3,48(sp)
+8000041c:	02e12a23          	sw	a4,52(sp)
+80000420:	02f12c23          	sw	a5,56(sp)
+80000424:	03012e23          	sw	a6,60(sp)
+80000428:	05112023          	sw	a7,64(sp)
+8000042c:	05212223          	sw	s2,68(sp)
+80000430:	05312423          	sw	s3,72(sp)
+80000434:	05412623          	sw	s4,76(sp)
+80000438:	05512823          	sw	s5,80(sp)
+8000043c:	05612a23          	sw	s6,84(sp)
+80000440:	05712c23          	sw	s7,88(sp)
+80000444:	05812e23          	sw	s8,92(sp)
+80000448:	07912023          	sw	s9,96(sp)
+8000044c:	07a12223          	sw	s10,100(sp)
+80000450:	07b12423          	sw	s11,104(sp)
+80000454:	07c12623          	sw	t3,108(sp)
+80000458:	07d12823          	sw	t4,112(sp)
+8000045c:	07e12a23          	sw	t5,116(sp)
+80000460:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  jal MSYS_EI0_IRQHandler
+80000464:	15d000ef          	jal	ra,80000dc0 <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:287
+  j generic_restore
+80000468:	4f00006f          	j	80000958 <generic_restore>
+
+8000046c <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+8000046c:	f8010113          	addi	sp,sp,-128
+80000470:	00112023          	sw	ra,0(sp)
+80000474:	00112023          	sw	ra,0(sp)
+80000478:	00212223          	sw	sp,4(sp)
+8000047c:	00312423          	sw	gp,8(sp)
+80000480:	00412623          	sw	tp,12(sp)
+80000484:	00512823          	sw	t0,16(sp)
+80000488:	00612a23          	sw	t1,20(sp)
+8000048c:	00712c23          	sw	t2,24(sp)
+80000490:	00812e23          	sw	s0,28(sp)
+80000494:	02912023          	sw	s1,32(sp)
+80000498:	02a12223          	sw	a0,36(sp)
+8000049c:	02b12423          	sw	a1,40(sp)
+800004a0:	02c12623          	sw	a2,44(sp)
+800004a4:	02d12823          	sw	a3,48(sp)
+800004a8:	02e12a23          	sw	a4,52(sp)
+800004ac:	02f12c23          	sw	a5,56(sp)
+800004b0:	03012e23          	sw	a6,60(sp)
+800004b4:	05112023          	sw	a7,64(sp)
+800004b8:	05212223          	sw	s2,68(sp)
+800004bc:	05312423          	sw	s3,72(sp)
+800004c0:	05412623          	sw	s4,76(sp)
+800004c4:	05512823          	sw	s5,80(sp)
+800004c8:	05612a23          	sw	s6,84(sp)
+800004cc:	05712c23          	sw	s7,88(sp)
+800004d0:	05812e23          	sw	s8,92(sp)
+800004d4:	07912023          	sw	s9,96(sp)
+800004d8:	07a12223          	sw	s10,100(sp)
+800004dc:	07b12423          	sw	s11,104(sp)
+800004e0:	07c12623          	sw	t3,108(sp)
+800004e4:	07d12823          	sw	t4,112(sp)
+800004e8:	07e12a23          	sw	t5,116(sp)
+800004ec:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  jal MSYS_EI1_IRQHandler
+800004f0:	0d5000ef          	jal	ra,80000dc4 <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:292
+  j generic_restore
+800004f4:	4640006f          	j	80000958 <generic_restore>
+
+800004f8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800004f8:	f8010113          	addi	sp,sp,-128
+800004fc:	00112023          	sw	ra,0(sp)
+80000500:	00112023          	sw	ra,0(sp)
+80000504:	00212223          	sw	sp,4(sp)
+80000508:	00312423          	sw	gp,8(sp)
+8000050c:	00412623          	sw	tp,12(sp)
+80000510:	00512823          	sw	t0,16(sp)
+80000514:	00612a23          	sw	t1,20(sp)
+80000518:	00712c23          	sw	t2,24(sp)
+8000051c:	00812e23          	sw	s0,28(sp)
+80000520:	02912023          	sw	s1,32(sp)
+80000524:	02a12223          	sw	a0,36(sp)
+80000528:	02b12423          	sw	a1,40(sp)
+8000052c:	02c12623          	sw	a2,44(sp)
+80000530:	02d12823          	sw	a3,48(sp)
+80000534:	02e12a23          	sw	a4,52(sp)
+80000538:	02f12c23          	sw	a5,56(sp)
+8000053c:	03012e23          	sw	a6,60(sp)
+80000540:	05112023          	sw	a7,64(sp)
+80000544:	05212223          	sw	s2,68(sp)
+80000548:	05312423          	sw	s3,72(sp)
+8000054c:	05412623          	sw	s4,76(sp)
+80000550:	05512823          	sw	s5,80(sp)
+80000554:	05612a23          	sw	s6,84(sp)
+80000558:	05712c23          	sw	s7,88(sp)
+8000055c:	05812e23          	sw	s8,92(sp)
+80000560:	07912023          	sw	s9,96(sp)
+80000564:	07a12223          	sw	s10,100(sp)
+80000568:	07b12423          	sw	s11,104(sp)
+8000056c:	07c12623          	sw	t3,108(sp)
+80000570:	07d12823          	sw	t4,112(sp)
+80000574:	07e12a23          	sw	t5,116(sp)
+80000578:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  jal MSYS_EI2_IRQHandler
+8000057c:	04d000ef          	jal	ra,80000dc8 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:297
+  j generic_restore
+80000580:	3d80006f          	j	80000958 <generic_restore>
+
+80000584 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000584:	f8010113          	addi	sp,sp,-128
+80000588:	00112023          	sw	ra,0(sp)
+8000058c:	00112023          	sw	ra,0(sp)
+80000590:	00212223          	sw	sp,4(sp)
+80000594:	00312423          	sw	gp,8(sp)
+80000598:	00412623          	sw	tp,12(sp)
+8000059c:	00512823          	sw	t0,16(sp)
+800005a0:	00612a23          	sw	t1,20(sp)
+800005a4:	00712c23          	sw	t2,24(sp)
+800005a8:	00812e23          	sw	s0,28(sp)
+800005ac:	02912023          	sw	s1,32(sp)
+800005b0:	02a12223          	sw	a0,36(sp)
+800005b4:	02b12423          	sw	a1,40(sp)
+800005b8:	02c12623          	sw	a2,44(sp)
+800005bc:	02d12823          	sw	a3,48(sp)
+800005c0:	02e12a23          	sw	a4,52(sp)
+800005c4:	02f12c23          	sw	a5,56(sp)
+800005c8:	03012e23          	sw	a6,60(sp)
+800005cc:	05112023          	sw	a7,64(sp)
+800005d0:	05212223          	sw	s2,68(sp)
+800005d4:	05312423          	sw	s3,72(sp)
+800005d8:	05412623          	sw	s4,76(sp)
+800005dc:	05512823          	sw	s5,80(sp)
+800005e0:	05612a23          	sw	s6,84(sp)
+800005e4:	05712c23          	sw	s7,88(sp)
+800005e8:	05812e23          	sw	s8,92(sp)
+800005ec:	07912023          	sw	s9,96(sp)
+800005f0:	07a12223          	sw	s10,100(sp)
+800005f4:	07b12423          	sw	s11,104(sp)
+800005f8:	07c12623          	sw	t3,108(sp)
+800005fc:	07d12823          	sw	t4,112(sp)
+80000600:	07e12a23          	sw	t5,116(sp)
+80000604:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  jal MSYS_EI3_IRQHandler
+80000608:	7c4000ef          	jal	ra,80000dcc <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:302
+  j generic_restore
+8000060c:	34c0006f          	j	80000958 <generic_restore>
+
+80000610 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+80000610:	f8010113          	addi	sp,sp,-128
+80000614:	00112023          	sw	ra,0(sp)
+80000618:	00112023          	sw	ra,0(sp)
+8000061c:	00212223          	sw	sp,4(sp)
+80000620:	00312423          	sw	gp,8(sp)
+80000624:	00412623          	sw	tp,12(sp)
+80000628:	00512823          	sw	t0,16(sp)
+8000062c:	00612a23          	sw	t1,20(sp)
+80000630:	00712c23          	sw	t2,24(sp)
+80000634:	00812e23          	sw	s0,28(sp)
+80000638:	02912023          	sw	s1,32(sp)
+8000063c:	02a12223          	sw	a0,36(sp)
+80000640:	02b12423          	sw	a1,40(sp)
+80000644:	02c12623          	sw	a2,44(sp)
+80000648:	02d12823          	sw	a3,48(sp)
+8000064c:	02e12a23          	sw	a4,52(sp)
+80000650:	02f12c23          	sw	a5,56(sp)
+80000654:	03012e23          	sw	a6,60(sp)
+80000658:	05112023          	sw	a7,64(sp)
+8000065c:	05212223          	sw	s2,68(sp)
+80000660:	05312423          	sw	s3,72(sp)
+80000664:	05412623          	sw	s4,76(sp)
+80000668:	05512823          	sw	s5,80(sp)
+8000066c:	05612a23          	sw	s6,84(sp)
+80000670:	05712c23          	sw	s7,88(sp)
+80000674:	05812e23          	sw	s8,92(sp)
+80000678:	07912023          	sw	s9,96(sp)
+8000067c:	07a12223          	sw	s10,100(sp)
+80000680:	07b12423          	sw	s11,104(sp)
+80000684:	07c12623          	sw	t3,108(sp)
+80000688:	07d12823          	sw	t4,112(sp)
+8000068c:	07e12a23          	sw	t5,116(sp)
+80000690:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  jal MSYS_EI4_IRQHandler
+80000694:	73c000ef          	jal	ra,80000dd0 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:307
+  j generic_restore
+80000698:	2c00006f          	j	80000958 <generic_restore>
+
+8000069c <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+8000069c:	f8010113          	addi	sp,sp,-128
+800006a0:	00112023          	sw	ra,0(sp)
+800006a4:	00112023          	sw	ra,0(sp)
+800006a8:	00212223          	sw	sp,4(sp)
+800006ac:	00312423          	sw	gp,8(sp)
+800006b0:	00412623          	sw	tp,12(sp)
+800006b4:	00512823          	sw	t0,16(sp)
+800006b8:	00612a23          	sw	t1,20(sp)
+800006bc:	00712c23          	sw	t2,24(sp)
+800006c0:	00812e23          	sw	s0,28(sp)
+800006c4:	02912023          	sw	s1,32(sp)
+800006c8:	02a12223          	sw	a0,36(sp)
+800006cc:	02b12423          	sw	a1,40(sp)
+800006d0:	02c12623          	sw	a2,44(sp)
+800006d4:	02d12823          	sw	a3,48(sp)
+800006d8:	02e12a23          	sw	a4,52(sp)
+800006dc:	02f12c23          	sw	a5,56(sp)
+800006e0:	03012e23          	sw	a6,60(sp)
+800006e4:	05112023          	sw	a7,64(sp)
+800006e8:	05212223          	sw	s2,68(sp)
+800006ec:	05312423          	sw	s3,72(sp)
+800006f0:	05412623          	sw	s4,76(sp)
+800006f4:	05512823          	sw	s5,80(sp)
+800006f8:	05612a23          	sw	s6,84(sp)
+800006fc:	05712c23          	sw	s7,88(sp)
+80000700:	05812e23          	sw	s8,92(sp)
+80000704:	07912023          	sw	s9,96(sp)
+80000708:	07a12223          	sw	s10,100(sp)
+8000070c:	07b12423          	sw	s11,104(sp)
+80000710:	07c12623          	sw	t3,108(sp)
+80000714:	07d12823          	sw	t4,112(sp)
+80000718:	07e12a23          	sw	t5,116(sp)
+8000071c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  jal MSYS_EI5_IRQHandler
+80000720:	6b4000ef          	jal	ra,80000dd4 <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:312
+  j generic_restore
+80000724:	2340006f          	j	80000958 <generic_restore>
+
+80000728 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+80000728:	f8010113          	addi	sp,sp,-128
+8000072c:	00112023          	sw	ra,0(sp)
+80000730:	00112023          	sw	ra,0(sp)
+80000734:	00212223          	sw	sp,4(sp)
+80000738:	00312423          	sw	gp,8(sp)
+8000073c:	00412623          	sw	tp,12(sp)
+80000740:	00512823          	sw	t0,16(sp)
+80000744:	00612a23          	sw	t1,20(sp)
+80000748:	00712c23          	sw	t2,24(sp)
+8000074c:	00812e23          	sw	s0,28(sp)
+80000750:	02912023          	sw	s1,32(sp)
+80000754:	02a12223          	sw	a0,36(sp)
+80000758:	02b12423          	sw	a1,40(sp)
+8000075c:	02c12623          	sw	a2,44(sp)
+80000760:	02d12823          	sw	a3,48(sp)
+80000764:	02e12a23          	sw	a4,52(sp)
+80000768:	02f12c23          	sw	a5,56(sp)
+8000076c:	03012e23          	sw	a6,60(sp)
+80000770:	05112023          	sw	a7,64(sp)
+80000774:	05212223          	sw	s2,68(sp)
+80000778:	05312423          	sw	s3,72(sp)
+8000077c:	05412623          	sw	s4,76(sp)
+80000780:	05512823          	sw	s5,80(sp)
+80000784:	05612a23          	sw	s6,84(sp)
+80000788:	05712c23          	sw	s7,88(sp)
+8000078c:	05812e23          	sw	s8,92(sp)
+80000790:	07912023          	sw	s9,96(sp)
+80000794:	07a12223          	sw	s10,100(sp)
+80000798:	07b12423          	sw	s11,104(sp)
+8000079c:	07c12623          	sw	t3,108(sp)
+800007a0:	07d12823          	sw	t4,112(sp)
+800007a4:	07e12a23          	sw	t5,116(sp)
+800007a8:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  jal SUBSYS_IRQHandler
+800007ac:	610000ef          	jal	ra,80000dbc <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:317
+  j generic_restore
+800007b0:	1a80006f          	j	80000958 <generic_restore>
+
+800007b4 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+800007b4:	f8010113          	addi	sp,sp,-128
+800007b8:	00112023          	sw	ra,0(sp)
+800007bc:	00112023          	sw	ra,0(sp)
+800007c0:	00212223          	sw	sp,4(sp)
+800007c4:	00312423          	sw	gp,8(sp)
+800007c8:	00412623          	sw	tp,12(sp)
+800007cc:	00512823          	sw	t0,16(sp)
+800007d0:	00612a23          	sw	t1,20(sp)
+800007d4:	00712c23          	sw	t2,24(sp)
+800007d8:	00812e23          	sw	s0,28(sp)
+800007dc:	02912023          	sw	s1,32(sp)
+800007e0:	02a12223          	sw	a0,36(sp)
+800007e4:	02b12423          	sw	a1,40(sp)
+800007e8:	02c12623          	sw	a2,44(sp)
+800007ec:	02d12823          	sw	a3,48(sp)
+800007f0:	02e12a23          	sw	a4,52(sp)
+800007f4:	02f12c23          	sw	a5,56(sp)
+800007f8:	03012e23          	sw	a6,60(sp)
+800007fc:	05112023          	sw	a7,64(sp)
+80000800:	05212223          	sw	s2,68(sp)
+80000804:	05312423          	sw	s3,72(sp)
+80000808:	05412623          	sw	s4,76(sp)
+8000080c:	05512823          	sw	s5,80(sp)
+80000810:	05612a23          	sw	s6,84(sp)
+80000814:	05712c23          	sw	s7,88(sp)
+80000818:	05812e23          	sw	s8,92(sp)
+8000081c:	07912023          	sw	s9,96(sp)
+80000820:	07a12223          	sw	s10,100(sp)
+80000824:	07b12423          	sw	s11,104(sp)
+80000828:	07c12623          	sw	t3,108(sp)
+8000082c:	07d12823          	sw	t4,112(sp)
+80000830:	07e12a23          	sw	t5,116(sp)
+80000834:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  jal MSYS_EI6_IRQHandler
+80000838:	5a4000ef          	jal	ra,80000ddc <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:323
+  j generic_restore
+8000083c:	11c0006f          	j	80000958 <generic_restore>
+
+80000840 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000840:	f8010113          	addi	sp,sp,-128
+80000844:	00112023          	sw	ra,0(sp)
+80000848:	00112023          	sw	ra,0(sp)
+8000084c:	00212223          	sw	sp,4(sp)
+80000850:	00312423          	sw	gp,8(sp)
+80000854:	00412623          	sw	tp,12(sp)
+80000858:	00512823          	sw	t0,16(sp)
+8000085c:	00612a23          	sw	t1,20(sp)
+80000860:	00712c23          	sw	t2,24(sp)
+80000864:	00812e23          	sw	s0,28(sp)
+80000868:	02912023          	sw	s1,32(sp)
+8000086c:	02a12223          	sw	a0,36(sp)
+80000870:	02b12423          	sw	a1,40(sp)
+80000874:	02c12623          	sw	a2,44(sp)
+80000878:	02d12823          	sw	a3,48(sp)
+8000087c:	02e12a23          	sw	a4,52(sp)
+80000880:	02f12c23          	sw	a5,56(sp)
+80000884:	03012e23          	sw	a6,60(sp)
+80000888:	05112023          	sw	a7,64(sp)
+8000088c:	05212223          	sw	s2,68(sp)
+80000890:	05312423          	sw	s3,72(sp)
+80000894:	05412623          	sw	s4,76(sp)
+80000898:	05512823          	sw	s5,80(sp)
+8000089c:	05612a23          	sw	s6,84(sp)
+800008a0:	05712c23          	sw	s7,88(sp)
+800008a4:	05812e23          	sw	s8,92(sp)
+800008a8:	07912023          	sw	s9,96(sp)
+800008ac:	07a12223          	sw	s10,100(sp)
+800008b0:	07b12423          	sw	s11,104(sp)
+800008b4:	07c12623          	sw	t3,108(sp)
+800008b8:	07d12823          	sw	t4,112(sp)
+800008bc:	07e12a23          	sw	t5,116(sp)
+800008c0:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  jal MSYS_EI7_IRQHandler
+800008c4:	51c000ef          	jal	ra,80000de0 <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:328
+  j generic_restore
+800008c8:	0900006f          	j	80000958 <generic_restore>
+
+800008cc <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+800008cc:	f8010113          	addi	sp,sp,-128
+800008d0:	00112023          	sw	ra,0(sp)
+800008d4:	00112023          	sw	ra,0(sp)
+800008d8:	00212223          	sw	sp,4(sp)
+800008dc:	00312423          	sw	gp,8(sp)
+800008e0:	00412623          	sw	tp,12(sp)
+800008e4:	00512823          	sw	t0,16(sp)
+800008e8:	00612a23          	sw	t1,20(sp)
+800008ec:	00712c23          	sw	t2,24(sp)
+800008f0:	00812e23          	sw	s0,28(sp)
+800008f4:	02912023          	sw	s1,32(sp)
+800008f8:	02a12223          	sw	a0,36(sp)
+800008fc:	02b12423          	sw	a1,40(sp)
+80000900:	02c12623          	sw	a2,44(sp)
+80000904:	02d12823          	sw	a3,48(sp)
+80000908:	02e12a23          	sw	a4,52(sp)
+8000090c:	02f12c23          	sw	a5,56(sp)
+80000910:	03012e23          	sw	a6,60(sp)
+80000914:	05112023          	sw	a7,64(sp)
+80000918:	05212223          	sw	s2,68(sp)
+8000091c:	05312423          	sw	s3,72(sp)
+80000920:	05412623          	sw	s4,76(sp)
+80000924:	05512823          	sw	s5,80(sp)
+80000928:	05612a23          	sw	s6,84(sp)
+8000092c:	05712c23          	sw	s7,88(sp)
+80000930:	05812e23          	sw	s8,92(sp)
+80000934:	07912023          	sw	s9,96(sp)
+80000938:	07a12223          	sw	s10,100(sp)
+8000093c:	07b12423          	sw	s11,104(sp)
+80000940:	07c12623          	sw	t3,108(sp)
+80000944:	07d12823          	sw	t4,112(sp)
+80000948:	07e12a23          	sw	t5,116(sp)
+8000094c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  jal SUBSYSR_IRQHandler
+80000950:	494000ef          	jal	ra,80000de4 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:334
+  j generic_restore
+80000954:	0040006f          	j	80000958 <generic_restore>
+
+80000958 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000958:	00012083          	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x2, 1 * REGBYTES(sp)
+8000095c:	00412103          	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x3, 2 * REGBYTES(sp)
+80000960:	00812183          	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x4, 3 * REGBYTES(sp)
+80000964:	00c12203          	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x5, 4 * REGBYTES(sp)
+80000968:	01012283          	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x6, 5 * REGBYTES(sp)
+8000096c:	01412303          	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x7, 6 * REGBYTES(sp)
+80000970:	01812383          	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x8, 7 * REGBYTES(sp)
+80000974:	01c12403          	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x9, 8 * REGBYTES(sp)
+80000978:	02012483          	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x10, 9 * REGBYTES(sp)
+8000097c:	02412503          	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x11, 10 * REGBYTES(sp)
+80000980:	02812583          	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x12, 11 * REGBYTES(sp)
+80000984:	02c12603          	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x13, 12 * REGBYTES(sp)
+80000988:	03012683          	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x14, 13 * REGBYTES(sp)
+8000098c:	03412703          	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x15, 14 * REGBYTES(sp)
+80000990:	03812783          	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x16, 15 * REGBYTES(sp)
+80000994:	03c12803          	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x17, 16 * REGBYTES(sp)
+80000998:	04012883          	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x18, 17 * REGBYTES(sp)
+8000099c:	04412903          	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x19, 18 * REGBYTES(sp)
+800009a0:	04812983          	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x20, 19 * REGBYTES(sp)
+800009a4:	04c12a03          	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x21, 20 * REGBYTES(sp)
+800009a8:	05012a83          	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x22, 21 * REGBYTES(sp)
+800009ac:	05412b03          	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x23, 22 * REGBYTES(sp)
+800009b0:	05812b83          	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x24, 23 * REGBYTES(sp)
+800009b4:	05c12c03          	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x25, 24 * REGBYTES(sp)
+800009b8:	06012c83          	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x26, 25 * REGBYTES(sp)
+800009bc:	06412d03          	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x27, 26 * REGBYTES(sp)
+800009c0:	06812d83          	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x28, 27 * REGBYTES(sp)
+800009c4:	06c12e03          	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x29, 28 * REGBYTES(sp)
+800009c8:	07012e83          	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x30, 29 * REGBYTES(sp)
+800009cc:	07412f03          	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:370
+  LREG x31, 30 * REGBYTES(sp)
+800009d0:	07812f83          	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+800009d4:	08010113          	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:410
+  mret
+800009d8:	30200073          	mret
+800009dc:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+800009e0 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+800009e0:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  csrwi mie, 0
+800009e4:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:421
+  la ra, _start
+800009e8:	fffff097          	auipc	ra,0xfffff
+800009ec:	61808093          	addi	ra,ra,1560 # 80000000 <_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+800009f0:	0200c2b7          	lui	t0,0x200c
+800009f4:	ffc28293          	addi	t0,t0,-4 # 200bffc <STACK_SIZE+0x200bbfc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:426
+  sw x0, 0(t0)
+800009f8:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+#endif
+
+  csrr t0, misa
+800009fc:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  andi t0, t0, A_EXTENSION_MASK
+80000a00:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:431
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+80000a04:	02029663          	bnez	t0,80000a30 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+80000a08:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+80000a0c:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  li t1, MTVEC_VECTORED_MODE_VAL
+80000a10:	00100313          	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:442
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+80000a14:	00629e63          	bne	t0,t1,80000a30 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+80000a18:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  andi t0, t0, 0xFFFFFFFC
+80000a1c:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  la t1, trap_entry
+80000a20:	fffff317          	auipc	t1,0xfffff
+80000a24:	5e430313          	addi	t1,t1,1508 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  bne t0, t1, vector_address_not_matching
+80000a28:	04629863          	bne	t0,t1,80000a78 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:450
+  j generic_reset_handling
+80000a2c:	0100006f          	j	80000a3c <generic_reset_handling>
+
+80000a30 <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:477
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+80000a30:	fffff297          	auipc	t0,0xfffff
+80000a34:	5d428293          	addi	t0,t0,1492 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:483
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+80000a38:	30529073          	csrw	mtvec,t0
+
+80000a3c <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+80000a3c:	00002717          	auipc	a4,0x2
+80000a40:	70470713          	addi	a4,a4,1796 # 80003140 <__sdata_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a5, __sdata_start
+80000a44:	00003797          	auipc	a5,0x3
+80000a48:	5bc78793          	addi	a5,a5,1468 # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    la a6, __sdata_end
+80000a4c:	00003817          	auipc	a6,0x3
+80000a50:	5c480813          	addi	a6,a6,1476 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+80000a54:	00f70863          	beq	a4,a5,80000a64 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+80000a58:	01078663          	beq	a5,a6,80000a64 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:493
+    call block_copy
+80000a5c:	00000097          	auipc	ra,0x0
+80000a60:	098080e7          	jalr	152(ra) # 80000af4 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:497
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+80000a64:	00004197          	auipc	gp,0x4
+80000a68:	d9c18193          	addi	gp,gp,-612 # 80004800 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:514
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+80000a6c:	010000ef          	jal	ra,80000a7c <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:516
+  /* Initialize stack pointer */
+  la sp, __stack_top
+80000a70:	d0018113          	addi	sp,gp,-768 # 80004500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:519
+
+  /* Jump into C code */
+  j _init
+80000a74:	3240006f          	j	80000d98 <_init>
+
+80000a78 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:524
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+80000a78:	00100073          	ebreak
+
+80000a7c <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+80000a7c:	00008293          	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a5, __bss_start
+80000a80:	8a018793          	addi	a5,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    la  a6, __bss_end
+80000a84:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a88:	01078463          	beq	a5,a6,80000a90 <initializations+0x14>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:532
+    call zeroize_block
+80000a8c:	048000ef          	jal	ra,80000ad4 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000a90:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    la  a6, __sbss_end
+80000a94:	8a018813          	addi	a6,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a98:	01078c63          	beq	a5,a6,80000ab0 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:539
+    call zeroize_block
+80000a9c:	038000ef          	jal	ra,80000ad4 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+
+/* Clear heap */
+    la  a5, __heap_start
+80000aa0:	90018793          	addi	a5,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    la  a6, __heap_end
+80000aa4:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000aa8:	01078463          	beq	a5,a6,80000ab0 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:545
+    call zeroize_block
+80000aac:	028000ef          	jal	ra,80000ad4 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000ab0:	00002717          	auipc	a4,0x2
+80000ab4:	6a070713          	addi	a4,a4,1696 # 80003150 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a5, __data_start
+80000ab8:	81018793          	addi	a5,gp,-2032 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    la  a6, __data_end
+80000abc:	87018813          	addi	a6,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000ac0:	00f70663          	beq	a4,a5,80000acc <initializations+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000ac4:	01078463          	beq	a5,a6,80000acc <initializations+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:554
+    call block_copy
+80000ac8:	02c000ef          	jal	ra,80000af4 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+
+1:
+    mv ra, t0           /* Retrieve ra */
+80000acc:	00028093          	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:558
+    ret
+80000ad0:	00008067          	ret
+
+80000ad4 <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000ad4:	04f86463          	bltu	a6,a5,80000b1c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000ad8:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    andi a7, a7, 0x03u
+80000adc:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:564
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000ae0:	03104e63          	bgtz	a7,80000b1c <block_copy_error>
+
+80000ae4 <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+zeroize_loop:
+    sw x0, 0(a5)
+80000ae4:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    add a5, a5, __SIZEOF_POINTER__
+80000ae8:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    blt a5, a6, zeroize_loop
+80000aec:	ff07cce3          	blt	a5,a6,80000ae4 <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:569
+    ret
+80000af0:	00008067          	ret
+
+80000af4 <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000af4:	02f86463          	bltu	a6,a5,80000b1c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000af8:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    andi a7, a7, 0x03u
+80000afc:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:575
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000b00:	01104e63          	bgtz	a7,80000b1c <block_copy_error>
+
+80000b04 <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+block_copy_loop:
+    lw a7, 0(a4)
+80000b04:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    sw a7, 0(a5)
+80000b08:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a5, a5, 0x04
+80000b0c:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    addi a4, a4, 0x04
+80000b10:	00470713          	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    blt a5, a6, block_copy_loop
+80000b14:	ff07c8e3          	blt	a5,a6,80000b04 <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:582
+    j block_copy_exit
+80000b18:	0080006f          	j	80000b20 <block_copy_exit>
+
+80000b1c <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:585
+
+block_copy_error:
+    j block_copy_error
+80000b1c:	0000006f          	j	80000b1c <block_copy_error>
+
+80000b20 <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:588
+
+block_copy_exit:
+    ret
+80000b20:	00008067          	ret
+
+80000b24 <MRV_read_mtime>:
+MRV_read_mtime():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:684
+
+/***************************************************************************//**
+  The MRV_read_mtime() function returns the current MTIME register value.
+ */
+static inline uint64_t MRV_read_mtime(void)
+{
+80000b24:	ff010113          	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:685
+    volatile uint32_t hi = 0u;
+80000b28:	00012423          	sw	zero,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:686
+    volatile uint32_t lo = 0u;
+80000b2c:	00012623          	sw	zero,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691
+
+    /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
+     * returned value could be wrong. */
+    do {
+        hi = MTIMEH;
+80000b30:	0200c7b7          	lui	a5,0x200c
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691 (discriminator 1)
+80000b34:	ffc7a683          	lw	a3,-4(a5) # 200bffc <STACK_SIZE+0x200bbfc>
+80000b38:	00d12423          	sw	a3,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:692 (discriminator 1)
+        lo = MTIME;
+80000b3c:	ff87a683          	lw	a3,-8(a5)
+80000b40:	00d12623          	sw	a3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:693 (discriminator 1)
+    } while(hi != MTIMEH);
+80000b44:	ffc7a603          	lw	a2,-4(a5)
+80000b48:	00812683          	lw	a3,8(sp)
+80000b4c:	fed614e3          	bne	a2,a3,80000b34 <MRV_read_mtime+0x10>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:695
+
+    return((((uint64_t)MTIMEH) << 32u) | lo);
+80000b50:	ffc7a583          	lw	a1,-4(a5)
+80000b54:	00c12503          	lw	a0,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:696
+}
+80000b58:	01010113          	addi	sp,sp,16
+80000b5c:	00008067          	ret
+
+80000b60 <MRV_systick_config>:
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+
+/*------------------------------------------------------------------------------
+ * Configure the machine timer to generate an interrupt.
+ */
+uint32_t MRV_systick_config(uint64_t ticks)
+{
+80000b60:	ff010113          	addi	sp,sp,-16
+80000b64:	00812423          	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    uint32_t ret_val = ERROR;
+    uint64_t remainder = ticks;
+    g_systick_increment = 0U;
+80000b68:	00000713          	li	a4,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+80000b6c:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+{
+80000b70:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+80000b74:	87818413          	addi	s0,gp,-1928 # 80004078 <g_systick_increment>
+80000b78:	00000693          	li	a3,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+80000b7c:	00e7a223          	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+80000b80:	00e42223          	sw	a4,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+80000b84:	00d7a023          	sw	a3,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+80000b88:	00d42023          	sw	a3,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:169
+
+    while (remainder >= MTIME_PRESCALER)
+80000b8c:	00000793          	li	a5,0
+80000b90:	00000713          	li	a4,0
+80000b94:	00000613          	li	a2,0
+80000b98:	02005837          	lui	a6,0x2005
+80000b9c:	00178893          	addi	a7,a5,1
+80000ba0:	00082303          	lw	t1,0(a6) # 2005000 <STACK_SIZE+0x2004c00>
+80000ba4:	00f8b6b3          	sltu	a3,a7,a5
+80000ba8:	00e686b3          	add	a3,a3,a4
+80000bac:	06059c63          	bnez	a1,80000c24 <MRV_systick_config+0xc4>
+80000bb0:	06657a63          	bgeu	a0,t1,80000c24 <MRV_systick_config+0xc4>
+80000bb4:	00060663          	beqz	a2,80000bc0 <MRV_systick_config+0x60>
+80000bb8:	86f1ac23          	sw	a5,-1928(gp) # 80004078 <g_systick_increment>
+80000bbc:	86e1ae23          	sw	a4,-1924(gp) # 8000407c <g_systick_increment+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:175
+    {
+        remainder -= MTIME_PRESCALER;
+        g_systick_increment++;
+    }
+
+    g_systick_cmp_value = g_systick_increment + MRV_read_mtime();
+80000bc0:	f65ff0ef          	jal	ra,80000b24 <MRV_read_mtime>
+80000bc4:	00042783          	lw	a5,0(s0)
+80000bc8:	00442683          	lw	a3,4(s0)
+80000bcc:	00f50733          	add	a4,a0,a5
+80000bd0:	00a73533          	sltu	a0,a4,a0
+80000bd4:	00d585b3          	add	a1,a1,a3
+80000bd8:	00b505b3          	add	a1,a0,a1
+80000bdc:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000be0:	86b1aa23          	sw	a1,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+
+    if (g_systick_increment > 0U)
+80000be4:	00d7e7b3          	or	a5,a5,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:164
+    uint32_t ret_val = ERROR;
+80000be8:	00100513          	li	a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+    if (g_systick_increment > 0U)
+80000bec:	02078463          	beqz	a5,80000c14 <MRV_systick_config+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:179
+    {
+        WRITE_MTIMECMP(g_systick_cmp_value);
+80000bf0:	020047b7          	lui	a5,0x2004
+80000bf4:	fff00693          	li	a3,-1
+80000bf8:	00d7a223          	sw	a3,4(a5) # 2004004 <STACK_SIZE+0x2003c04>
+80000bfc:	00e7a023          	sw	a4,0(a5)
+80000c00:	00b7a223          	sw	a1,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:180
+        set_csr(mie, MIP_MTIP);
+80000c04:	08000793          	li	a5,128
+80000c08:	3047a7f3          	csrrs	a5,mie,a5
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80000c0c:	300467f3          	csrrsi	a5,mstatus,8
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:182
+        MRV_enable_interrupts();
+        ret_val = SUCCESS;
+80000c10:	00000513          	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:186
+    }
+
+    return ret_val;
+}
+80000c14:	00c12083          	lw	ra,12(sp)
+80000c18:	00812403          	lw	s0,8(sp)
+80000c1c:	01010113          	addi	sp,sp,16
+80000c20:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:171
+        remainder -= MTIME_PRESCALER;
+80000c24:	00082783          	lw	a5,0(a6)
+80000c28:	00100613          	li	a2,1
+80000c2c:	40f507b3          	sub	a5,a0,a5
+80000c30:	00f53733          	sltu	a4,a0,a5
+80000c34:	40e585b3          	sub	a1,a1,a4
+80000c38:	00078513          	mv	a0,a5
+80000c3c:	00068713          	mv	a4,a3
+80000c40:	00088793          	mv	a5,a7
+80000c44:	f59ff06f          	j	80000b9c <MRV_systick_config+0x3c>
+
+80000c48 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000c48:	ff010113          	addi	sp,sp,-16
+80000c4c:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+80000c50:	08000793          	li	a5,128
+80000c54:	3047b7f3          	csrrc	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MRV_read_mtime();
+80000c58:	ecdff0ef          	jal	ra,80000b24 <MRV_read_mtime>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000c5c:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+80000c60:	0007a703          	lw	a4,0(a5)
+80000c64:	00550613          	addi	a2,a0,5
+80000c68:	0047a783          	lw	a5,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000c6c:	87818693          	addi	a3,gp,-1928 # 80004078 <g_systick_increment>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000c70:	00a63533          	sltu	a0,a2,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000c74:	0006a803          	lw	a6,0(a3)
+80000c78:	0046a883          	lw	a7,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000c7c:	00b505b3          	add	a1,a0,a1
+80000c80:	00000693          	li	a3,0
+80000c84:	04b7e263          	bltu	a5,a1,80000cc8 <handle_m_timer_interrupt+0x80>
+80000c88:	00f59463          	bne	a1,a5,80000c90 <handle_m_timer_interrupt+0x48>
+80000c8c:	02c76e63          	bltu	a4,a2,80000cc8 <handle_m_timer_interrupt+0x80>
+80000c90:	00068663          	beqz	a3,80000c9c <handle_m_timer_interrupt+0x54>
+80000c94:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000c98:	86f1aa23          	sw	a5,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+80000c9c:	020046b7          	lui	a3,0x2004
+80000ca0:	fff00613          	li	a2,-1
+80000ca4:	00c6a223          	sw	a2,4(a3) # 2004004 <STACK_SIZE+0x2003c04>
+80000ca8:	00e6a023          	sw	a4,0(a3)
+80000cac:	00f6a223          	sw	a5,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000cb0:	6a8000ef          	jal	ra,80001358 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000cb4:	08000793          	li	a5,128
+80000cb8:	3047a7f3          	csrrs	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+80000cbc:	00c12083          	lw	ra,12(sp)
+80000cc0:	01010113          	addi	sp,sp,16
+80000cc4:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000cc8:	010706b3          	add	a3,a4,a6
+80000ccc:	00e6b533          	sltu	a0,a3,a4
+80000cd0:	011787b3          	add	a5,a5,a7
+80000cd4:	00068713          	mv	a4,a3
+80000cd8:	00f507b3          	add	a5,a0,a5
+80000cdc:	00100693          	li	a3,1
+80000ce0:	fa5ff06f          	j	80000c84 <handle_m_timer_interrupt+0x3c>
+
+80000ce4 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+80000ce4:	ff010113          	addi	sp,sp,-16
+80000ce8:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+80000cec:	658000ef          	jal	ra,80001344 <Software_IRQHandler>
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000cf0:	00006737          	lui	a4,0x6
+80000cf4:	02072783          	lw	a5,32(a4) # 6020 <STACK_SIZE+0x5c20>
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+    MRV_clear_soft_irq();
+}
+80000cf8:	00c12083          	lw	ra,12(sp)
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+80000cfc:	ffd7f793          	andi	a5,a5,-3
+80000d00:	02f72023          	sw	a5,32(a4)
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+80000d04:	01010113          	addi	sp,sp,16
+80000d08:	00008067          	ret
+
+80000d0c <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+    uint64_t mhart_id = read_csr(mhartid);
+80000d0c:	f14027f3          	csrr	a5,mhartid
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+80000d10:	ff050513          	addi	a0,a0,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+80000d14:	0ff57513          	andi	a0,a0,255
+80000d18:	00251513          	slli	a0,a0,0x2
+80000d1c:	00002797          	auipc	a5,0x2
+80000d20:	19478793          	addi	a5,a5,404 # 80002eb0 <local_irq_handler_table>
+80000d24:	00a78533          	add	a0,a5,a0
+80000d28:	00052303          	lw	t1,0(a0)
+80000d2c:	00030067          	jr	t1
+
+80000d30 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+
+    if (is_interrupt)
+80000d30:	04055a63          	bgez	a0,80000d84 <handle_trap+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+80000d34:	800007b7          	lui	a5,0x80000
+80000d38:	ff07c713          	xori	a4,a5,-16
+80000d3c:	00e57733          	and	a4,a0,a4
+80000d40:	00070c63          	beqz	a4,80000d58 <handle_trap+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+80000d44:	fe07c793          	xori	a5,a5,-32
+80000d48:	00f577b3          	and	a5,a0,a5
+80000d4c:	00079663          	bnez	a5,80000d58 <handle_trap+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000d50:	0ff57513          	andi	a0,a0,255
+80000d54:	fb9ff06f          	j	80000d0c <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000d58:	00151513          	slli	a0,a0,0x1
+80000d5c:	00155513          	srli	a0,a0,0x1
+80000d60:	00b00793          	li	a5,11
+80000d64:	00f51463          	bne	a0,a5,80000d6c <handle_trap+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+#else
+        if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+#endif
+        {
+#ifndef MIV_LEGACY_RV32
+            External_IRQHandler();
+80000d68:	0480006f          	j	80000db0 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+#else
+            handle_m_ext_interrupt();
+#endif
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000d6c:	00300793          	li	a5,3
+80000d70:	00f51463          	bne	a0,a5,80000d78 <handle_trap+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+        {
+            handle_m_soft_interrupt();
+80000d74:	f71ff06f          	j	80000ce4 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+80000d78:	00700793          	li	a5,7
+80000d7c:	00f51c63          	bne	a0,a5,80000d94 <handle_trap+0x64>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+        {
+            handle_m_timer_interrupt();
+80000d80:	ec9ff06f          	j	80000c48 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000d84:	ff010113          	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+         uintptr_t mmepc  = read_csr(mepc);
+
+        /* breakpoint */
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+80000d88:	00150513          	addi	a0,a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000d8c:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+        _exit(1 + mcause);
+80000d90:	058000ef          	jal	ra,80000de8 <_exit>
+80000d94:	00008067          	ret
+
+80000d98 <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+80000d98:	6140006f          	j	800013ac <main>
+
+80000d9c <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+}
+80000d9c:	00008067          	ret
+
+80000da0 <Software_IRQHandler.localalias.0>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000da0:	ff010113          	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000da4:	00a00513          	li	a0,10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+{
+80000da8:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000dac:	03c000ef          	jal	ra,80000de8 <_exit>
+
+80000db0 <External_IRQHandler>:
+External_IRQHandler():
+80000db0:	00008067          	ret
+
+80000db4 <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+80000db4:	00008067          	ret
+
+80000db8 <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+80000db8:	00008067          	ret
+
+80000dbc <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+80000dbc:	00008067          	ret
+
+80000dc0 <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+80000dc0:	00008067          	ret
+
+80000dc4 <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+80000dc4:	00008067          	ret
+
+80000dc8 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+80000dc8:	00008067          	ret
+
+80000dcc <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+80000dcc:	00008067          	ret
+
+80000dd0 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+80000dd0:	00008067          	ret
+
+80000dd4 <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+80000dd4:	00008067          	ret
+
+80000dd8 <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+80000dd8:	fc9ff06f          	j	80000da0 <Software_IRQHandler.localalias.0>
+
+80000ddc <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+80000ddc:	00008067          	ret
+
+80000de0 <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+80000de0:	00008067          	ret
+
+80000de4 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+80000de4:	00008067          	ret
+
+80000de8 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80000de8:	0000006f          	j	80000de8 <_exit>
+
+80000dec <_sbrk>:
+_sbrk():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169
+     * You need to set HEAP_SIZE to a non-zero value in your linker script if
+     * the following assertion fires.
+     */
+    ASSERT(&__heap_end > &__heap_start);
+
+    if (((curbrk + incr) < &_end) || ((curbrk + incr) > &_heap_end))
+80000dec:	00003797          	auipc	a5,0x3
+80000df0:	21478793          	addi	a5,a5,532 # 80004000 <__sdata_start>
+80000df4:	0007a783          	lw	a5,0(a5)
+80000df8:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+80000dfc:	00a78533          	add	a0,a5,a0
+80000e00:	00e56e63          	bltu	a0,a4,80000e1c <_sbrk+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169 (discriminator 1)
+80000e04:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+80000e08:	00a76a63          	bltu	a4,a0,80000e1c <_sbrk+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:176
+        errno = ENOMEM;
+        ret = ((char *) - 1);
+    }
+    else
+    {
+        curbrk += incr;
+80000e0c:	00003717          	auipc	a4,0x3
+80000e10:	1ea72a23          	sw	a0,500(a4) # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:188
+     * assertion fires.
+     * */
+    ASSERT(curbrk <= &__heap_end);
+
+    return(ret);
+}
+80000e14:	00078513          	mv	a0,a5
+80000e18:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:172
+        ret = ((char *) - 1);
+80000e1c:	fff00793          	li	a5,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:187
+    return(ret);
+80000e20:	ff5ff06f          	j	80000e14 <_sbrk+0x28>
+
+80000e24 <_isatty>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:205
+        errno = EBADF;
+        ret = 0;
+    }
+
+    return(ret);
+}
+80000e24:	00352513          	slti	a0,a0,3
+80000e28:	00008067          	ret
+
+80000e2c <_close>:
+_close():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:226
+}
+
+int _close(int fd)
+{
+    return stub(EBADF);
+}
+80000e2c:	fff00513          	li	a0,-1
+80000e30:	00008067          	ret
+
+80000e34 <_fstat>:
+_fstat():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:239
+{
+    return stub(EAGAIN);
+}
+
+int _fstat(int fd, struct stat *st)
+{
+80000e34:	fe010113          	addi	sp,sp,-32
+80000e38:	00112e23          	sw	ra,28(sp)
+80000e3c:	00b12623          	sw	a1,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:242
+    int ret = 0;
+
+    if (isatty(fd))
+80000e40:	6b4000ef          	jal	ra,800014f4 <isatty>
+80000e44:	02050063          	beqz	a0,80000e64 <_fstat+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+    {
+        st->st_mode = S_IFCHR;
+80000e48:	00c12583          	lw	a1,12(sp)
+80000e4c:	000027b7          	lui	a5,0x2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:245
+        ret = 0;
+80000e50:	00000513          	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+        st->st_mode = S_IFCHR;
+80000e54:	00f5a223          	sw	a5,4(a1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:253
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+80000e58:	01c12083          	lw	ra,28(sp)
+80000e5c:	02010113          	addi	sp,sp,32
+80000e60:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:249
+        ret = stub(EBADF);
+80000e64:	fff00513          	li	a0,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:252
+    return ret;
+80000e68:	ff1ff06f          	j	80000e58 <_fstat+0x24>
+
+80000e6c <_lseek>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:194
+    if (fd <= 2)    /* one of stdin, stdout, stderr */
+80000e6c:	00352513          	slti	a0,a0,3
+_lseek():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:283
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+80000e70:	fff50513          	addi	a0,a0,-1
+80000e74:	00008067          	ret
+
+80000e78 <_read>:
+_read():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:313
+        return  count;          /* Filled the buffer */
+    }
+#endif
+
+    return stub(EBADF);
+}
+80000e78:	fff00513          	li	a0,-1
+80000e7c:	00008067          	ret
+
+80000e80 <_write>:
+_write():
+80000e80:	fff00513          	li	a0,-1
+80000e84:	00008067          	ret
+
+80000e88 <HAL_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+    set_csr(mstatus, MSTATUS_MIE);
+80000e88:	300467f3          	csrrsi	a5,mstatus,8
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hal_irq.c:24
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+    MRV_enable_interrupts();
+}
+80000e8c:	00008067          	ret
+
+80000e90 <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+80000e90:	00b52023          	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:40
+    ret
+80000e94:	00008067          	ret
+
+80000e98 <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+80000e98:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:52
+    ret
+80000e9c:	00008067          	ret
+
+80000ea0 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+80000ea0:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+80000ea4:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+80000ea8:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+80000eac:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+80000eb0:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+80000eb4:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+80000eb8:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+80000ebc:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+80000ec0:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:73
+    ret
+80000ec4:	00008067          	ret
+
+80000ec8 <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+80000ec8:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+80000ecc:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+80000ed0:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:90
+    ret
+80000ed4:	00008067          	ret
+
+80000ed8 <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+80000ed8:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:101
+    ret
+80000edc:	00008067          	ret
+
+80000ee0 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+80000ee0:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:113
+    ret
+80000ee4:	00008067          	ret
+
+80000ee8 <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+80000ee8:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80000eec:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80000ef0:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80000ef4:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+80000ef8:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+80000efc:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80000f00:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80000f04:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+80000f08:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:135
+    ret
+80000f0c:	00008067          	ret
+
+80000f10 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80000f10:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80000f14:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+80000f18:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:152
+    ret
+80000f1c:	00008067          	ret
+
+80000f20 <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+80000f20:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:163
+    ret
+80000f24:	00008067          	ret
+
+80000f28 <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+80000f28:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:175
+    ret
+80000f2c:	00008067          	ret
+
+80000f30 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80000f30:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+80000f34:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+80000f38:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80000f3c:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80000f40:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80000f44:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+80000f48:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80000f4c:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80000f50:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:196
+    ret
+80000f54:	00008067          	ret
+
+80000f58 <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+80000f58:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+80000f5c:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80000f60:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:213
+    ret
+80000f64:	00008067          	ret
+
+80000f68 <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+80000f68:	0a050463          	beqz	a0,80001010 <UART_init+0xa8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+80000f6c:	00700793          	li	a5,7
+80000f70:	0ad7e063          	bltu	a5,a3,80001010 <UART_init+0xa8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+80000f74:	000027b7          	lui	a5,0x2
+80000f78:	08f67c63          	bgeu	a2,a5,80001010 <UART_init+0xa8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+80000f7c:	fe010113          	addi	sp,sp,-32
+80000f80:	00812c23          	sw	s0,24(sp)
+80000f84:	01212823          	sw	s2,16(sp)
+80000f88:	00060413          	mv	s0,a2
+80000f8c:	00058913          	mv	s2,a1
+80000f90:	00912a23          	sw	s1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000f94:	0ff67593          	andi	a1,a2,255
+80000f98:	00050493          	mv	s1,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000f9c:	40545413          	srai	s0,s0,0x5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000fa0:	00890513          	addi	a0,s2,8
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+80000fa4:	00112e23          	sw	ra,28(sp)
+80000fa8:	01312623          	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000fac:	7f847413          	andi	s0,s0,2040
+80000fb0:	00068993          	mv	s3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000fb4:	f6dff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000fb8:	00c90513          	addi	a0,s2,12
+80000fbc:	013465b3          	or	a1,s0,s3
+80000fc0:	f61ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80000fc4:	01090513          	addi	a0,s2,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+        this_uart->base_address = base_addr;
+80000fc8:	0124a023          	sw	s2,0(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80000fcc:	f5dff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+80000fd0:	00257513          	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+80000fd4:	02051263          	bnez	a0,80000ff8 <UART_init+0x90>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+80000fd8:	00048223          	sb	zero,4(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+80000fdc:	01c12083          	lw	ra,28(sp)
+80000fe0:	01812403          	lw	s0,24(sp)
+80000fe4:	01412483          	lw	s1,20(sp)
+80000fe8:	01012903          	lw	s2,16(sp)
+80000fec:	00c12983          	lw	s3,12(sp)
+80000ff0:	02010113          	addi	sp,sp,32
+80000ff4:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+80000ff8:	0004a503          	lw	a0,0(s1)
+80000ffc:	00450513          	addi	a0,a0,4
+80001000:	f29ff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80001004:	0004a503          	lw	a0,0(s1)
+80001008:	01050513          	addi	a0,a0,16
+8000100c:	fc1ff06f          	j	80000fcc <UART_init+0x64>
+80001010:	00008067          	ret
+
+80001014 <UART_get_rx>:
+UART_get_rx():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:199
+(
+    UART_instance_t * this_uart,
+    uint8_t * rx_buffer,
+    size_t buff_size
+)
+{
+80001014:	fe010113          	addi	sp,sp,-32
+80001018:	00112e23          	sw	ra,28(sp)
+8000101c:	00812c23          	sw	s0,24(sp)
+80001020:	00912a23          	sw	s1,20(sp)
+80001024:	01212823          	sw	s2,16(sp)
+80001028:	01312623          	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( rx_buffer != NULL_BUFFER )
+    HAL_ASSERT( buff_size > 0 )
+      
+    if( (this_uart != NULL_INSTANCE) &&
+8000102c:	08050c63          	beqz	a0,800010c4 <UART_get_rx+0xb0>
+80001030:	00058993          	mv	s3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208 (discriminator 1)
+80001034:	08058863          	beqz	a1,800010c4 <UART_get_rx+0xb0>
+80001038:	00060493          	mv	s1,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:209
+        (rx_buffer != NULL_BUFFER)   &&
+8000103c:	02060863          	beqz	a2,8000106c <UART_get_rx+0x58>
+80001040:	00050413          	mv	s0,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        (buff_size > 0u) )
+    {
+        rx_idx = 0u;
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+80001044:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:212
+        rx_idx = 0u;
+80001048:	00000913          	li	s2,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+8000104c:	01050513          	addi	a0,a0,16
+80001050:	ed9ff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:214
+        this_uart->status |= new_status;
+80001054:	00444783          	lbu	a5,4(s0)
+80001058:	00f567b3          	or	a5,a0,a5
+8000105c:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:215
+        rx_full = new_status & STATUS_RXFULL_MASK;
+80001060:	00257513          	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216
+        while ( ( rx_full ) && ( rx_idx < buff_size ) )
+80001064:	06050463          	beqz	a0,800010cc <UART_get_rx+0xb8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216 (discriminator 1)
+80001068:	02991263          	bne	s2,s1,8000108c <UART_get_rx+0x78>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:227
+            this_uart->status |= new_status;
+            rx_full = new_status & STATUS_RXFULL_MASK;
+        }
+    }
+    return rx_idx;
+}
+8000106c:	01c12083          	lw	ra,28(sp)
+80001070:	01812403          	lw	s0,24(sp)
+80001074:	00048513          	mv	a0,s1
+80001078:	01012903          	lw	s2,16(sp)
+8000107c:	01412483          	lw	s1,20(sp)
+80001080:	00c12983          	lw	s3,12(sp)
+80001084:	02010113          	addi	sp,sp,32
+80001088:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:218
+            rx_buffer[rx_idx] = HAL_get_8bit_reg( this_uart->base_address,
+8000108c:	00042503          	lw	a0,0(s0)
+80001090:	00450513          	addi	a0,a0,4
+80001094:	e95ff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+80001098:	012987b3          	add	a5,s3,s2
+8000109c:	00a78023          	sb	a0,0(a5) # 2000 <STACK_SIZE+0x1c00>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800010a0:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:220
+            rx_idx++;
+800010a4:	00190913          	addi	s2,s2,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800010a8:	01050513          	addi	a0,a0,16
+800010ac:	e7dff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:222
+            this_uart->status |= new_status;
+800010b0:	00444783          	lbu	a5,4(s0)
+800010b4:	00f567b3          	or	a5,a0,a5
+800010b8:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:223
+            rx_full = new_status & STATUS_RXFULL_MASK;
+800010bc:	00257513          	andi	a0,a0,2
+800010c0:	fa5ff06f          	j	80001064 <UART_get_rx+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:202
+    size_t rx_idx = 0u;
+800010c4:	00000493          	li	s1,0
+800010c8:	fa5ff06f          	j	8000106c <UART_get_rx+0x58>
+800010cc:	00090493          	mv	s1,s2
+800010d0:	f9dff06f          	j	8000106c <UART_get_rx+0x58>
+
+800010d4 <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+800010d4:	06050263          	beqz	a0,80001138 <UART_polled_tx_string+0x64>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+800010d8:	06058063          	beqz	a1,80001138 <UART_polled_tx_string+0x64>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+{
+800010dc:	ff010113          	addi	sp,sp,-16
+800010e0:	00812423          	sw	s0,8(sp)
+800010e4:	00912223          	sw	s1,4(sp)
+800010e8:	00112623          	sw	ra,12(sp)
+800010ec:	00050493          	mv	s1,a0
+800010f0:	00058413          	mv	s0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+    {
+        char_idx = 0U;
+        while( 0U != p_sz_string[char_idx] )
+800010f4:	00044783          	lbu	a5,0(s0)
+800010f8:	00079c63          	bnez	a5,80001110 <UART_polled_tx_string+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+        }
+    }
+}
+800010fc:	00c12083          	lw	ra,12(sp)
+80001100:	00812403          	lw	s0,8(sp)
+80001104:	00412483          	lw	s1,4(sp)
+80001108:	01010113          	addi	sp,sp,16
+8000110c:	00008067          	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80001110:	0004a503          	lw	a0,0(s1)
+80001114:	01050513          	addi	a0,a0,16
+80001118:	e11ff0ef          	jal	ra,80000f28 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+            } while ( !tx_ready );
+8000111c:	00157513          	andi	a0,a0,1
+80001120:	fe0508e3          	beqz	a0,80001110 <UART_polled_tx_string+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+80001124:	00044583          	lbu	a1,0(s0)
+80001128:	0004a503          	lw	a0,0(s1)
+8000112c:	00140413          	addi	s0,s0,1
+80001130:	df1ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+            char_idx++;
+80001134:	fc1ff06f          	j	800010f4 <UART_polled_tx_string+0x20>
+80001138:	00008067          	ret
+
+8000113c <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+8000113c:	ff010113          	addi	sp,sp,-16
+80001140:	00812423          	sw	s0,8(sp)
+80001144:	00050413          	mv	s0,a0
+80001148:	00912223          	sw	s1,4(sp)
+8000114c:	01212023          	sw	s2,0(sp)
+80001150:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    uint8_t i = 0;
+    addr_t cfg_reg_addr = base_addr;
+    
+    this_gpio->base_addr = base_addr;
+80001154:	00b42023          	sw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+{
+80001158:	00058493          	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+8000115c:	00c52223          	sw	a2,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80001160:	08058913          	addi	s2,a1,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80001164:	00048513          	mv	a0,s1
+80001168:	00000593          	li	a1,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+8000116c:	00448493          	addi	s1,s1,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80001170:	db1ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80001174:	ff2498e3          	bne	s1,s2,80001164 <GPIO_init+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+80001178:	00442783          	lw	a5,4(s0)
+8000117c:	00100713          	li	a4,1
+80001180:	02e78a63          	beq	a5,a4,800011b4 <GPIO_init+0x78>
+80001184:	06078463          	beqz	a5,800011ec <GPIO_init+0xb0>
+80001188:	00200713          	li	a4,2
+8000118c:	0ae79a63          	bne	a5,a4,80001240 <GPIO_init+0x104>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80001190:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+80001194:	00812403          	lw	s0,8(sp)
+80001198:	00c12083          	lw	ra,12(sp)
+8000119c:	00412483          	lw	s1,4(sp)
+800011a0:	00012903          	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+800011a4:	fff00593          	li	a1,-1
+800011a8:	08050513          	addi	a0,a0,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+800011ac:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+800011b0:	ce1ff06f          	j	80000e90 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+800011b4:	00042503          	lw	a0,0(s0)
+800011b8:	000104b7          	lui	s1,0x10
+800011bc:	fff48593          	addi	a1,s1,-1 # ffff <STACK_SIZE+0xfbff>
+800011c0:	08050513          	addi	a0,a0,128
+800011c4:	d15ff0ef          	jal	ra,80000ed8 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+800011c8:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+800011cc:	00812403          	lw	s0,8(sp)
+800011d0:	00c12083          	lw	ra,12(sp)
+800011d4:	00012903          	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+800011d8:	fff48593          	addi	a1,s1,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+800011dc:	00412483          	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+800011e0:	08450513          	addi	a0,a0,132
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+800011e4:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+800011e8:	cf1ff06f          	j	80000ed8 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+800011ec:	00042503          	lw	a0,0(s0)
+800011f0:	0ff00593          	li	a1,255
+800011f4:	08050513          	addi	a0,a0,128
+800011f8:	d29ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+800011fc:	00042503          	lw	a0,0(s0)
+80001200:	0ff00593          	li	a1,255
+80001204:	08450513          	addi	a0,a0,132
+80001208:	d19ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+8000120c:	00042503          	lw	a0,0(s0)
+80001210:	0ff00593          	li	a1,255
+80001214:	08850513          	addi	a0,a0,136
+80001218:	d09ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+8000121c:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80001220:	00812403          	lw	s0,8(sp)
+80001224:	00c12083          	lw	ra,12(sp)
+80001228:	00412483          	lw	s1,4(sp)
+8000122c:	00012903          	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80001230:	0ff00593          	li	a1,255
+80001234:	08c50513          	addi	a0,a0,140
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80001238:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+8000123c:	ce5ff06f          	j	80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80001240:	00c12083          	lw	ra,12(sp)
+80001244:	00812403          	lw	s0,8(sp)
+80001248:	00412483          	lw	s1,4(sp)
+8000124c:	00012903          	lw	s2,0(sp)
+80001250:	01010113          	addi	sp,sp,16
+80001254:	00008067          	ret
+
+80001258 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+    switch( this_gpio->apb_bus_width )
+80001258:	00452783          	lw	a5,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+8000125c:	ff010113          	addi	sp,sp,-16
+80001260:	00812423          	sw	s0,8(sp)
+80001264:	00912223          	sw	s1,4(sp)
+80001268:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+8000126c:	00100713          	li	a4,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+80001270:	00050413          	mv	s0,a0
+80001274:	00058493          	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+80001278:	02e78663          	beq	a5,a4,800012a4 <GPIO_set_outputs+0x4c>
+8000127c:	04078e63          	beqz	a5,800012d8 <GPIO_set_outputs+0x80>
+80001280:	00200713          	li	a4,2
+80001284:	0ae79663          	bne	a5,a4,80001330 <GPIO_set_outputs+0xd8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80001288:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+}
+8000128c:	00812403          	lw	s0,8(sp)
+80001290:	00c12083          	lw	ra,12(sp)
+80001294:	00412483          	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80001298:	0a050513          	addi	a0,a0,160
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+8000129c:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+800012a0:	bf1ff06f          	j	80000e90 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+800012a4:	00052503          	lw	a0,0(a0)
+800012a8:	01059593          	slli	a1,a1,0x10
+800012ac:	0105d593          	srli	a1,a1,0x10
+800012b0:	0a050513          	addi	a0,a0,160
+800012b4:	c25ff0ef          	jal	ra,80000ed8 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+800012b8:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+800012bc:	00812403          	lw	s0,8(sp)
+800012c0:	00c12083          	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+800012c4:	0104d593          	srli	a1,s1,0x10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+800012c8:	00412483          	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+800012cc:	0a450513          	addi	a0,a0,164
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+800012d0:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+800012d4:	c05ff06f          	j	80000ed8 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+800012d8:	00052503          	lw	a0,0(a0)
+800012dc:	0ff5f593          	andi	a1,a1,255
+800012e0:	0a050513          	addi	a0,a0,160
+800012e4:	c3dff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+800012e8:	00042503          	lw	a0,0(s0)
+800012ec:	0084d593          	srli	a1,s1,0x8
+800012f0:	0ff5f593          	andi	a1,a1,255
+800012f4:	0a450513          	addi	a0,a0,164
+800012f8:	c29ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+800012fc:	00042503          	lw	a0,0(s0)
+80001300:	0104d593          	srli	a1,s1,0x10
+80001304:	0ff5f593          	andi	a1,a1,255
+80001308:	0a850513          	addi	a0,a0,168
+8000130c:	c15ff0ef          	jal	ra,80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80001310:	00042503          	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001314:	00812403          	lw	s0,8(sp)
+80001318:	00c12083          	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+8000131c:	0184d593          	srli	a1,s1,0x18
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001320:	00412483          	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80001324:	0ac50513          	addi	a0,a0,172
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001328:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+8000132c:	bf5ff06f          	j	80000f20 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001330:	00c12083          	lw	ra,12(sp)
+80001334:	00812403          	lw	s0,8(sp)
+80001338:	00412483          	lw	s1,4(sp)
+8000133c:	01010113          	addi	sp,sp,16
+80001340:	00008067          	ret
+
+80001344 <Software_IRQHandler>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80001344:	00006737          	lui	a4,0x6
+80001348:	02072783          	lw	a5,32(a4) # 6020 <STACK_SIZE+0x5c20>
+8000134c:	ffd7f793          	andi	a5,a5,-3
+80001350:	02f72023          	sw	a5,32(a4)
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:45
+ * in miv_rv32_stubs.c.
+ */
+void Software_IRQHandler()
+{
+    MRV_clear_soft_irq();
+}
+80001354:	00008067          	ret
+
+80001358 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+ * Toggles the LEDs on the board through the GPIO and counts the number of Ticks
+ * that have occured and prints the interrupt count in message on the UART.
+ */
+
+void SysTick_Handler(void)
+{
+80001358:	ff010113          	addi	sp,sp,-16
+8000135c:	00812423          	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    static uint32_t interrupt_counter = 0;
+    interrupt_counter++;
+80001360:	88418413          	addi	s0,gp,-1916 # 80004084 <interrupt_counter.2878>
+80001364:	00042783          	lw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+{
+80001368:	00112623          	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    static volatile uint32_t val = 0u;
+    val ^= 0xFu;
+    GPIO_set_outputs(&g_gpio_out, val);
+8000136c:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    interrupt_counter++;
+80001370:	00178793          	addi	a5,a5,1
+80001374:	00f42023          	sw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:58
+    val ^= 0xFu;
+80001378:	88818793          	addi	a5,gp,-1912 # 80004088 <val.2879>
+8000137c:	0007a703          	lw	a4,0(a5)
+80001380:	00f74713          	xori	a4,a4,15
+80001384:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    GPIO_set_outputs(&g_gpio_out, val);
+80001388:	0007a583          	lw	a1,0(a5)
+8000138c:	ecdff0ef          	jal	ra,80001258 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80001390:	00042583          	lw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+80001394:	00812403          	lw	s0,8(sp)
+80001398:	00c12083          	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+8000139c:	00002517          	auipc	a0,0x2
+800013a0:	b5450513          	addi	a0,a0,-1196 # 80002ef0 <local_irq_handler_table+0x40>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+800013a4:	01010113          	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+800013a8:	0d00006f          	j	80001478 <iprintf>
+
+800013ac <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+
+/*-------------------------------------------------------------------------//**
+  main() function.
+*/
+int main(void)
+{
+800013ac:	ff010113          	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    uint8_t rx_char;
+    uint8_t rx_count;
+    uint32_t switches;
+
+    UART_init(&g_uart,
+800013b0:	00100693          	li	a3,1
+800013b4:	01a00613          	li	a2,26
+800013b8:	710005b7          	lui	a1,0x71000
+800013bc:	8e818513          	addi	a0,gp,-1816 # 800040e8 <g_uart>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+{
+800013c0:	00112623          	sw	ra,12(sp)
+800013c4:	00812423          	sw	s0,8(sp)
+800013c8:	00912223          	sw	s1,4(sp)
+800013cc:	01212023          	sw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    UART_init(&g_uart,
+800013d0:	b99ff0ef          	jal	ra,80000f68 <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:77
+              COREUARTAPB0_BASE_ADDR,
+              BAUD_VALUE_115200,
+              (DATA_8_BITS | NO_PARITY));
+
+    printf(g_hello_msg);
+800013d4:	00003797          	auipc	a5,0x3
+800013d8:	c3078793          	addi	a5,a5,-976 # 80004004 <g_hello_msg>
+800013dc:	0007a503          	lw	a0,0(a5)
+800013e0:	098000ef          	jal	ra,80001478 <iprintf>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:80
+
+    /* Initializing GPIOs */
+    GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+800013e4:	00200613          	li	a2,2
+800013e8:	750005b7          	lui	a1,0x75000
+800013ec:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+800013f0:	d4dff0ef          	jal	ra,8000113c <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:98
+	 * GPIO_config(&g_gpio_out, 0, GPIO_OUTPUT_MODE);
+     * GPIO_config(&g_gpio_out, 1, GPIO_OUTPUT_MODE);
+	 */
+
+    /* set the output value */
+    GPIO_set_outputs(&g_gpio_out, 0x0u);
+800013f4:	00000593          	li	a1,0
+800013f8:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+800013fc:	e5dff0ef          	jal	ra,80001258 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:101
+
+    /* This must be done for all Mi-V cores to enable interrupts globally. */
+    HAL_enable_interrupts();
+80001400:	a89ff0ef          	jal	ra,80000e88 <HAL_enable_interrupts>
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80001404:	070007b7          	lui	a5,0x7000
+80001408:	3047a7f3          	csrrs	a5,mie,a5
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:107
+
+#ifndef MIV_LEGACY_RV32
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn | MRV32_MSYS_EIE1_IRQn | MRV32_MSYS_EIE2_IRQn);
+#endif
+
+    MRV_systick_config(SYS_CLK_FREQ);
+8000140c:	02faf537          	lui	a0,0x2faf
+80001410:	08050513          	addi	a0,a0,128 # 2faf080 <STACK_SIZE+0x2faec80>
+80001414:	00000593          	li	a1,0
+80001418:	f48ff0ef          	jal	ra,80000b60 <MRV_systick_config>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:114
+    /**************************************************************************
+    * Loop
+    *************************************************************************/
+    do
+    {
+        g_rx_size = UART_get_rx(&g_uart, g_rx_buff, sizeof(g_rx_buff));
+8000141c:	8a018493          	addi	s1,gp,-1888 # 800040a0 <__sbss_end>
+80001420:	8e818413          	addi	s0,gp,-1816 # 800040e8 <g_uart>
+80001424:	88018913          	addi	s2,gp,-1920 # 80004080 <g_rx_size>
+80001428:	04000613          	li	a2,64
+8000142c:	8a018593          	addi	a1,gp,-1888 # 800040a0 <__sbss_end>
+80001430:	00040513          	mv	a0,s0
+80001434:	be1ff0ef          	jal	ra,80001014 <UART_get_rx>
+80001438:	88a18023          	sb	a0,-1920(gp) # 80004080 <g_rx_size>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:116
+
+        if (g_rx_size > 0u)
+8000143c:	00094783          	lbu	a5,0(s2)
+80001440:	0ff7f793          	andi	a5,a5,255
+80001444:	fe0782e3          	beqz	a5,80001428 <main+0x7c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:119
+        {
+            /* Echo the characters received from the terminal */
+            UART_polled_tx_string(&g_uart, (const uint8_t *)g_rx_buff);
+80001448:	00048593          	mv	a1,s1
+8000144c:	00040513          	mv	a0,s0
+80001450:	c85ff0ef          	jal	ra,800010d4 <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:120
+            g_rx_size = 0u;
+80001454:	88018023          	sb	zero,-1920(gp) # 80004080 <g_rx_size>
+80001458:	fd1ff06f          	j	80001428 <main+0x7c>
+
+8000145c <memset>:
+memset():
+8000145c:	00050313          	mv	t1,a0
+80001460:	00060a63          	beqz	a2,80001474 <memset+0x18>
+80001464:	00b30023          	sb	a1,0(t1)
+80001468:	fff60613          	addi	a2,a2,-1
+8000146c:	00130313          	addi	t1,t1,1
+80001470:	fe061ae3          	bnez	a2,80001464 <memset+0x8>
+80001474:	00008067          	ret
+
+80001478 <iprintf>:
+printf():
+80001478:	fc010113          	addi	sp,sp,-64
+8000147c:	02f12a23          	sw	a5,52(sp)
+80001480:	02b12223          	sw	a1,36(sp)
+80001484:	02c12423          	sw	a2,40(sp)
+80001488:	02d12623          	sw	a3,44(sp)
+8000148c:	02e12823          	sw	a4,48(sp)
+80001490:	03012c23          	sw	a6,56(sp)
+80001494:	03112e23          	sw	a7,60(sp)
+80001498:	00003797          	auipc	a5,0x3
+8000149c:	b7078793          	addi	a5,a5,-1168 # 80004008 <_impure_ptr>
+800014a0:	00812c23          	sw	s0,24(sp)
+800014a4:	0007a403          	lw	s0,0(a5)
+800014a8:	00912a23          	sw	s1,20(sp)
+800014ac:	00112e23          	sw	ra,28(sp)
+800014b0:	00050493          	mv	s1,a0
+800014b4:	00040a63          	beqz	s0,800014c8 <iprintf+0x50>
+800014b8:	01842783          	lw	a5,24(s0)
+800014bc:	00079663          	bnez	a5,800014c8 <iprintf+0x50>
+800014c0:	00040513          	mv	a0,s0
+800014c4:	180000ef          	jal	ra,80001644 <__sinit>
+800014c8:	00842583          	lw	a1,8(s0)
+800014cc:	02410693          	addi	a3,sp,36
+800014d0:	00048613          	mv	a2,s1
+800014d4:	00040513          	mv	a0,s0
+800014d8:	00d12623          	sw	a3,12(sp)
+800014dc:	5bc000ef          	jal	ra,80001a98 <_vfiprintf_r>
+800014e0:	01c12083          	lw	ra,28(sp)
+800014e4:	01812403          	lw	s0,24(sp)
+800014e8:	01412483          	lw	s1,20(sp)
+800014ec:	04010113          	addi	sp,sp,64
+800014f0:	00008067          	ret
+
+800014f4 <isatty>:
+isatty():
+800014f4:	931ff06f          	j	80000e24 <_isatty>
+
+800014f8 <_write_r>:
+_write_r():
+800014f8:	ff010113          	addi	sp,sp,-16
+800014fc:	00812423          	sw	s0,8(sp)
+80001500:	00050413          	mv	s0,a0
+80001504:	00058513          	mv	a0,a1
+80001508:	00060593          	mv	a1,a2
+8000150c:	00068613          	mv	a2,a3
+80001510:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001514:	00112623          	sw	ra,12(sp)
+80001518:	969ff0ef          	jal	ra,80000e80 <_write>
+8000151c:	fff00793          	li	a5,-1
+80001520:	00f51a63          	bne	a0,a5,80001534 <_write_r+0x3c>
+80001524:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001528:	0007a783          	lw	a5,0(a5)
+8000152c:	00078463          	beqz	a5,80001534 <_write_r+0x3c>
+80001530:	00f42023          	sw	a5,0(s0)
+80001534:	00c12083          	lw	ra,12(sp)
+80001538:	00812403          	lw	s0,8(sp)
+8000153c:	01010113          	addi	sp,sp,16
+80001540:	00008067          	ret
+
+80001544 <std>:
+std():
+80001544:	ff010113          	addi	sp,sp,-16
+80001548:	00812423          	sw	s0,8(sp)
+8000154c:	00112623          	sw	ra,12(sp)
+80001550:	00050413          	mv	s0,a0
+80001554:	00b51623          	sh	a1,12(a0)
+80001558:	00c51723          	sh	a2,14(a0)
+8000155c:	00052023          	sw	zero,0(a0)
+80001560:	00052223          	sw	zero,4(a0)
+80001564:	00052423          	sw	zero,8(a0)
+80001568:	06052223          	sw	zero,100(a0)
+8000156c:	00052823          	sw	zero,16(a0)
+80001570:	00052a23          	sw	zero,20(a0)
+80001574:	00052c23          	sw	zero,24(a0)
+80001578:	00800613          	li	a2,8
+8000157c:	00000593          	li	a1,0
+80001580:	05c50513          	addi	a0,a0,92
+80001584:	ed9ff0ef          	jal	ra,8000145c <memset>
+80001588:	00001797          	auipc	a5,0x1
+8000158c:	e9878793          	addi	a5,a5,-360 # 80002420 <__sread>
+80001590:	02f42223          	sw	a5,36(s0)
+80001594:	00001797          	auipc	a5,0x1
+80001598:	edc78793          	addi	a5,a5,-292 # 80002470 <__swrite>
+8000159c:	02f42423          	sw	a5,40(s0)
+800015a0:	00001797          	auipc	a5,0x1
+800015a4:	f5478793          	addi	a5,a5,-172 # 800024f4 <__sseek>
+800015a8:	02f42623          	sw	a5,44(s0)
+800015ac:	00001797          	auipc	a5,0x1
+800015b0:	fa078793          	addi	a5,a5,-96 # 8000254c <__sclose>
+800015b4:	02842023          	sw	s0,32(s0)
+800015b8:	02f42823          	sw	a5,48(s0)
+800015bc:	00c12083          	lw	ra,12(sp)
+800015c0:	00812403          	lw	s0,8(sp)
+800015c4:	01010113          	addi	sp,sp,16
+800015c8:	00008067          	ret
+
+800015cc <_cleanup_r>:
+_cleanup_r():
+800015cc:	00001597          	auipc	a1,0x1
+800015d0:	47058593          	addi	a1,a1,1136 # 80002a3c <_fflush_r>
+800015d4:	2140006f          	j	800017e8 <_fwalk_reent>
+
+800015d8 <__sfmoreglue>:
+__sfmoreglue():
+800015d8:	ff010113          	addi	sp,sp,-16
+800015dc:	00912223          	sw	s1,4(sp)
+800015e0:	06800613          	li	a2,104
+800015e4:	fff58493          	addi	s1,a1,-1
+800015e8:	02c484b3          	mul	s1,s1,a2
+800015ec:	01212023          	sw	s2,0(sp)
+800015f0:	00058913          	mv	s2,a1
+800015f4:	00812423          	sw	s0,8(sp)
+800015f8:	00112623          	sw	ra,12(sp)
+800015fc:	07448593          	addi	a1,s1,116
+80001600:	29c000ef          	jal	ra,8000189c <_malloc_r>
+80001604:	00050413          	mv	s0,a0
+80001608:	02050063          	beqz	a0,80001628 <__sfmoreglue+0x50>
+8000160c:	00052023          	sw	zero,0(a0)
+80001610:	01252223          	sw	s2,4(a0)
+80001614:	00c50513          	addi	a0,a0,12
+80001618:	00a42423          	sw	a0,8(s0)
+8000161c:	06848613          	addi	a2,s1,104
+80001620:	00000593          	li	a1,0
+80001624:	e39ff0ef          	jal	ra,8000145c <memset>
+80001628:	00040513          	mv	a0,s0
+8000162c:	00c12083          	lw	ra,12(sp)
+80001630:	00812403          	lw	s0,8(sp)
+80001634:	00412483          	lw	s1,4(sp)
+80001638:	00012903          	lw	s2,0(sp)
+8000163c:	01010113          	addi	sp,sp,16
+80001640:	00008067          	ret
+
+80001644 <__sinit>:
+__sinit():
+80001644:	01852783          	lw	a5,24(a0)
+80001648:	0a079663          	bnez	a5,800016f4 <__sinit+0xb0>
+8000164c:	ff010113          	addi	sp,sp,-16
+80001650:	00112623          	sw	ra,12(sp)
+80001654:	00812423          	sw	s0,8(sp)
+80001658:	00000797          	auipc	a5,0x0
+8000165c:	f7478793          	addi	a5,a5,-140 # 800015cc <_cleanup_r>
+80001660:	02f52423          	sw	a5,40(a0)
+80001664:	00002797          	auipc	a5,0x2
+80001668:	acc78793          	addi	a5,a5,-1332 # 80003130 <_global_impure_ptr>
+8000166c:	0007a783          	lw	a5,0(a5)
+80001670:	04052423          	sw	zero,72(a0)
+80001674:	04052623          	sw	zero,76(a0)
+80001678:	04052823          	sw	zero,80(a0)
+8000167c:	00f51663          	bne	a0,a5,80001688 <__sinit+0x44>
+80001680:	00100793          	li	a5,1
+80001684:	00f52c23          	sw	a5,24(a0)
+80001688:	00050413          	mv	s0,a0
+8000168c:	06c000ef          	jal	ra,800016f8 <__sfp>
+80001690:	00a42223          	sw	a0,4(s0)
+80001694:	00040513          	mv	a0,s0
+80001698:	060000ef          	jal	ra,800016f8 <__sfp>
+8000169c:	00a42423          	sw	a0,8(s0)
+800016a0:	00040513          	mv	a0,s0
+800016a4:	054000ef          	jal	ra,800016f8 <__sfp>
+800016a8:	00a42623          	sw	a0,12(s0)
+800016ac:	00442503          	lw	a0,4(s0)
+800016b0:	00000613          	li	a2,0
+800016b4:	00400593          	li	a1,4
+800016b8:	e8dff0ef          	jal	ra,80001544 <std>
+800016bc:	00842503          	lw	a0,8(s0)
+800016c0:	00100613          	li	a2,1
+800016c4:	00900593          	li	a1,9
+800016c8:	e7dff0ef          	jal	ra,80001544 <std>
+800016cc:	00c42503          	lw	a0,12(s0)
+800016d0:	00200613          	li	a2,2
+800016d4:	01200593          	li	a1,18
+800016d8:	e6dff0ef          	jal	ra,80001544 <std>
+800016dc:	00100793          	li	a5,1
+800016e0:	00f42c23          	sw	a5,24(s0)
+800016e4:	00c12083          	lw	ra,12(sp)
+800016e8:	00812403          	lw	s0,8(sp)
+800016ec:	01010113          	addi	sp,sp,16
+800016f0:	00008067          	ret
+800016f4:	00008067          	ret
+
+800016f8 <__sfp>:
+__sfp():
+800016f8:	ff010113          	addi	sp,sp,-16
+800016fc:	00002797          	auipc	a5,0x2
+80001700:	a3478793          	addi	a5,a5,-1484 # 80003130 <_global_impure_ptr>
+80001704:	00912223          	sw	s1,4(sp)
+80001708:	0007a483          	lw	s1,0(a5)
+8000170c:	01212023          	sw	s2,0(sp)
+80001710:	00112623          	sw	ra,12(sp)
+80001714:	0184a783          	lw	a5,24(s1)
+80001718:	00812423          	sw	s0,8(sp)
+8000171c:	00050913          	mv	s2,a0
+80001720:	00079663          	bnez	a5,8000172c <__sfp+0x34>
+80001724:	00048513          	mv	a0,s1
+80001728:	f1dff0ef          	jal	ra,80001644 <__sinit>
+8000172c:	04848493          	addi	s1,s1,72
+80001730:	0084a403          	lw	s0,8(s1)
+80001734:	0044a783          	lw	a5,4(s1)
+80001738:	fff78793          	addi	a5,a5,-1
+8000173c:	0007da63          	bgez	a5,80001750 <__sfp+0x58>
+80001740:	0004a783          	lw	a5,0(s1)
+80001744:	08078063          	beqz	a5,800017c4 <__sfp+0xcc>
+80001748:	0004a483          	lw	s1,0(s1)
+8000174c:	fe5ff06f          	j	80001730 <__sfp+0x38>
+80001750:	00c41703          	lh	a4,12(s0)
+80001754:	06071463          	bnez	a4,800017bc <__sfp+0xc4>
+80001758:	ffff07b7          	lui	a5,0xffff0
+8000175c:	00178793          	addi	a5,a5,1 # ffff0001 <__global_pointer$+0x7ffeb801>
+80001760:	06042223          	sw	zero,100(s0)
+80001764:	00042023          	sw	zero,0(s0)
+80001768:	00042223          	sw	zero,4(s0)
+8000176c:	00042423          	sw	zero,8(s0)
+80001770:	00f42623          	sw	a5,12(s0)
+80001774:	00042823          	sw	zero,16(s0)
+80001778:	00042a23          	sw	zero,20(s0)
+8000177c:	00042c23          	sw	zero,24(s0)
+80001780:	00800613          	li	a2,8
+80001784:	00000593          	li	a1,0
+80001788:	05c40513          	addi	a0,s0,92
+8000178c:	cd1ff0ef          	jal	ra,8000145c <memset>
+80001790:	02042a23          	sw	zero,52(s0)
+80001794:	02042c23          	sw	zero,56(s0)
+80001798:	04042423          	sw	zero,72(s0)
+8000179c:	04042623          	sw	zero,76(s0)
+800017a0:	00040513          	mv	a0,s0
+800017a4:	00c12083          	lw	ra,12(sp)
+800017a8:	00812403          	lw	s0,8(sp)
+800017ac:	00412483          	lw	s1,4(sp)
+800017b0:	00012903          	lw	s2,0(sp)
+800017b4:	01010113          	addi	sp,sp,16
+800017b8:	00008067          	ret
+800017bc:	06840413          	addi	s0,s0,104
+800017c0:	f79ff06f          	j	80001738 <__sfp+0x40>
+800017c4:	00400593          	li	a1,4
+800017c8:	00090513          	mv	a0,s2
+800017cc:	e0dff0ef          	jal	ra,800015d8 <__sfmoreglue>
+800017d0:	00a4a023          	sw	a0,0(s1)
+800017d4:	00050413          	mv	s0,a0
+800017d8:	f60518e3          	bnez	a0,80001748 <__sfp+0x50>
+800017dc:	00c00793          	li	a5,12
+800017e0:	00f92023          	sw	a5,0(s2)
+800017e4:	fbdff06f          	j	800017a0 <__sfp+0xa8>
+
+800017e8 <_fwalk_reent>:
+_fwalk_reent():
+800017e8:	fd010113          	addi	sp,sp,-48
+800017ec:	02812423          	sw	s0,40(sp)
+800017f0:	03212023          	sw	s2,32(sp)
+800017f4:	01412c23          	sw	s4,24(sp)
+800017f8:	01512a23          	sw	s5,20(sp)
+800017fc:	01612823          	sw	s6,16(sp)
+80001800:	01712623          	sw	s7,12(sp)
+80001804:	02112623          	sw	ra,44(sp)
+80001808:	02912223          	sw	s1,36(sp)
+8000180c:	01312e23          	sw	s3,28(sp)
+80001810:	00050a13          	mv	s4,a0
+80001814:	00058a93          	mv	s5,a1
+80001818:	04850413          	addi	s0,a0,72
+8000181c:	00000913          	li	s2,0
+80001820:	00100b13          	li	s6,1
+80001824:	fff00b93          	li	s7,-1
+80001828:	02041a63          	bnez	s0,8000185c <_fwalk_reent+0x74>
+8000182c:	02c12083          	lw	ra,44(sp)
+80001830:	02812403          	lw	s0,40(sp)
+80001834:	00090513          	mv	a0,s2
+80001838:	02412483          	lw	s1,36(sp)
+8000183c:	02012903          	lw	s2,32(sp)
+80001840:	01c12983          	lw	s3,28(sp)
+80001844:	01812a03          	lw	s4,24(sp)
+80001848:	01412a83          	lw	s5,20(sp)
+8000184c:	01012b03          	lw	s6,16(sp)
+80001850:	00c12b83          	lw	s7,12(sp)
+80001854:	03010113          	addi	sp,sp,48
+80001858:	00008067          	ret
+8000185c:	00842483          	lw	s1,8(s0)
+80001860:	00442983          	lw	s3,4(s0)
+80001864:	fff98993          	addi	s3,s3,-1
+80001868:	0009d663          	bgez	s3,80001874 <_fwalk_reent+0x8c>
+8000186c:	00042403          	lw	s0,0(s0)
+80001870:	fb9ff06f          	j	80001828 <_fwalk_reent+0x40>
+80001874:	00c4d783          	lhu	a5,12(s1)
+80001878:	00fb7e63          	bgeu	s6,a5,80001894 <_fwalk_reent+0xac>
+8000187c:	00e49783          	lh	a5,14(s1)
+80001880:	01778a63          	beq	a5,s7,80001894 <_fwalk_reent+0xac>
+80001884:	00048593          	mv	a1,s1
+80001888:	000a0513          	mv	a0,s4
+8000188c:	000a80e7          	jalr	s5
+80001890:	00a96933          	or	s2,s2,a0
+80001894:	06848493          	addi	s1,s1,104
+80001898:	fcdff06f          	j	80001864 <_fwalk_reent+0x7c>
+
+8000189c <_malloc_r>:
+_malloc_r():
+8000189c:	fe010113          	addi	sp,sp,-32
+800018a0:	00912a23          	sw	s1,20(sp)
+800018a4:	00358493          	addi	s1,a1,3
+800018a8:	ffc4f493          	andi	s1,s1,-4
+800018ac:	00112e23          	sw	ra,28(sp)
+800018b0:	00812c23          	sw	s0,24(sp)
+800018b4:	01212823          	sw	s2,16(sp)
+800018b8:	01312623          	sw	s3,12(sp)
+800018bc:	00848493          	addi	s1,s1,8
+800018c0:	00c00793          	li	a5,12
+800018c4:	06f4f463          	bgeu	s1,a5,8000192c <_malloc_r+0x90>
+800018c8:	00c00493          	li	s1,12
+800018cc:	06b4e263          	bltu	s1,a1,80001930 <_malloc_r+0x94>
+800018d0:	00050913          	mv	s2,a0
+800018d4:	3f4010ef          	jal	ra,80002cc8 <__malloc_lock>
+800018d8:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+800018dc:	0007a703          	lw	a4,0(a5)
+800018e0:	00070413          	mv	s0,a4
+800018e4:	06041a63          	bnez	s0,80001958 <_malloc_r+0xbc>
+800018e8:	89018793          	addi	a5,gp,-1904 # 80004090 <__malloc_sbrk_start>
+800018ec:	0007a783          	lw	a5,0(a5)
+800018f0:	00079a63          	bnez	a5,80001904 <_malloc_r+0x68>
+800018f4:	00000593          	li	a1,0
+800018f8:	00090513          	mv	a0,s2
+800018fc:	2e1000ef          	jal	ra,800023dc <_sbrk_r>
+80001900:	88a1a823          	sw	a0,-1904(gp) # 80004090 <__malloc_sbrk_start>
+80001904:	00048593          	mv	a1,s1
+80001908:	00090513          	mv	a0,s2
+8000190c:	2d1000ef          	jal	ra,800023dc <_sbrk_r>
+80001910:	fff00993          	li	s3,-1
+80001914:	0b351a63          	bne	a0,s3,800019c8 <_malloc_r+0x12c>
+80001918:	00c00793          	li	a5,12
+8000191c:	00f92023          	sw	a5,0(s2)
+80001920:	00090513          	mv	a0,s2
+80001924:	3a8010ef          	jal	ra,80002ccc <__malloc_unlock>
+80001928:	0100006f          	j	80001938 <_malloc_r+0x9c>
+8000192c:	fa04d0e3          	bgez	s1,800018cc <_malloc_r+0x30>
+80001930:	00c00793          	li	a5,12
+80001934:	00f52023          	sw	a5,0(a0)
+80001938:	00000513          	li	a0,0
+8000193c:	01c12083          	lw	ra,28(sp)
+80001940:	01812403          	lw	s0,24(sp)
+80001944:	01412483          	lw	s1,20(sp)
+80001948:	01012903          	lw	s2,16(sp)
+8000194c:	00c12983          	lw	s3,12(sp)
+80001950:	02010113          	addi	sp,sp,32
+80001954:	00008067          	ret
+80001958:	00042783          	lw	a5,0(s0)
+8000195c:	409787b3          	sub	a5,a5,s1
+80001960:	0407ce63          	bltz	a5,800019bc <_malloc_r+0x120>
+80001964:	00b00693          	li	a3,11
+80001968:	00f6fa63          	bgeu	a3,a5,8000197c <_malloc_r+0xe0>
+8000196c:	00f42023          	sw	a5,0(s0)
+80001970:	00f40433          	add	s0,s0,a5
+80001974:	00942023          	sw	s1,0(s0)
+80001978:	0100006f          	j	80001988 <_malloc_r+0xec>
+8000197c:	00442783          	lw	a5,4(s0)
+80001980:	02871a63          	bne	a4,s0,800019b4 <_malloc_r+0x118>
+80001984:	88f1a623          	sw	a5,-1908(gp) # 8000408c <__malloc_free_list>
+80001988:	00090513          	mv	a0,s2
+8000198c:	340010ef          	jal	ra,80002ccc <__malloc_unlock>
+80001990:	00b40513          	addi	a0,s0,11
+80001994:	00440793          	addi	a5,s0,4
+80001998:	ff857513          	andi	a0,a0,-8
+8000199c:	40f50733          	sub	a4,a0,a5
+800019a0:	f8070ee3          	beqz	a4,8000193c <_malloc_r+0xa0>
+800019a4:	00e40433          	add	s0,s0,a4
+800019a8:	40a787b3          	sub	a5,a5,a0
+800019ac:	00f42023          	sw	a5,0(s0)
+800019b0:	f8dff06f          	j	8000193c <_malloc_r+0xa0>
+800019b4:	00f72223          	sw	a5,4(a4)
+800019b8:	fd1ff06f          	j	80001988 <_malloc_r+0xec>
+800019bc:	00040713          	mv	a4,s0
+800019c0:	00442403          	lw	s0,4(s0)
+800019c4:	f21ff06f          	j	800018e4 <_malloc_r+0x48>
+800019c8:	00350413          	addi	s0,a0,3
+800019cc:	ffc47413          	andi	s0,s0,-4
+800019d0:	fa8502e3          	beq	a0,s0,80001974 <_malloc_r+0xd8>
+800019d4:	40a405b3          	sub	a1,s0,a0
+800019d8:	00090513          	mv	a0,s2
+800019dc:	201000ef          	jal	ra,800023dc <_sbrk_r>
+800019e0:	f9351ae3          	bne	a0,s3,80001974 <_malloc_r+0xd8>
+800019e4:	f35ff06f          	j	80001918 <_malloc_r+0x7c>
+
+800019e8 <__sfputc_r>:
+__sfputc_r():
+800019e8:	00862783          	lw	a5,8(a2)
+800019ec:	fff78793          	addi	a5,a5,-1
+800019f0:	00f62423          	sw	a5,8(a2)
+800019f4:	0007dc63          	bgez	a5,80001a0c <__sfputc_r+0x24>
+800019f8:	01862703          	lw	a4,24(a2)
+800019fc:	00e7c663          	blt	a5,a4,80001a08 <__sfputc_r+0x20>
+80001a00:	00a00793          	li	a5,10
+80001a04:	00f59463          	bne	a1,a5,80001a0c <__sfputc_r+0x24>
+80001a08:	34d0006f          	j	80002554 <__swbuf_r>
+80001a0c:	00062783          	lw	a5,0(a2)
+80001a10:	00058513          	mv	a0,a1
+80001a14:	00178713          	addi	a4,a5,1
+80001a18:	00e62023          	sw	a4,0(a2)
+80001a1c:	00b78023          	sb	a1,0(a5)
+80001a20:	00008067          	ret
+
+80001a24 <__sfputs_r>:
+__sfputs_r():
+80001a24:	fe010113          	addi	sp,sp,-32
+80001a28:	00812c23          	sw	s0,24(sp)
+80001a2c:	00912a23          	sw	s1,20(sp)
+80001a30:	01212823          	sw	s2,16(sp)
+80001a34:	01312623          	sw	s3,12(sp)
+80001a38:	01412423          	sw	s4,8(sp)
+80001a3c:	00112e23          	sw	ra,28(sp)
+80001a40:	00050913          	mv	s2,a0
+80001a44:	00058993          	mv	s3,a1
+80001a48:	00060413          	mv	s0,a2
+80001a4c:	00d604b3          	add	s1,a2,a3
+80001a50:	fff00a13          	li	s4,-1
+80001a54:	00941663          	bne	s0,s1,80001a60 <__sfputs_r+0x3c>
+80001a58:	00000513          	li	a0,0
+80001a5c:	01c0006f          	j	80001a78 <__sfputs_r+0x54>
+80001a60:	00044583          	lbu	a1,0(s0)
+80001a64:	00098613          	mv	a2,s3
+80001a68:	00090513          	mv	a0,s2
+80001a6c:	f7dff0ef          	jal	ra,800019e8 <__sfputc_r>
+80001a70:	00140413          	addi	s0,s0,1
+80001a74:	ff4510e3          	bne	a0,s4,80001a54 <__sfputs_r+0x30>
+80001a78:	01c12083          	lw	ra,28(sp)
+80001a7c:	01812403          	lw	s0,24(sp)
+80001a80:	01412483          	lw	s1,20(sp)
+80001a84:	01012903          	lw	s2,16(sp)
+80001a88:	00c12983          	lw	s3,12(sp)
+80001a8c:	00812a03          	lw	s4,8(sp)
+80001a90:	02010113          	addi	sp,sp,32
+80001a94:	00008067          	ret
+
+80001a98 <_vfiprintf_r>:
+_vfiprintf_r():
+80001a98:	f6010113          	addi	sp,sp,-160
+80001a9c:	08812c23          	sw	s0,152(sp)
+80001aa0:	08912a23          	sw	s1,148(sp)
+80001aa4:	09212823          	sw	s2,144(sp)
+80001aa8:	09312623          	sw	s3,140(sp)
+80001aac:	08112e23          	sw	ra,156(sp)
+80001ab0:	09412423          	sw	s4,136(sp)
+80001ab4:	09512223          	sw	s5,132(sp)
+80001ab8:	09612023          	sw	s6,128(sp)
+80001abc:	07712e23          	sw	s7,124(sp)
+80001ac0:	07812c23          	sw	s8,120(sp)
+80001ac4:	07912a23          	sw	s9,116(sp)
+80001ac8:	00050993          	mv	s3,a0
+80001acc:	00058493          	mv	s1,a1
+80001ad0:	00060913          	mv	s2,a2
+80001ad4:	00068413          	mv	s0,a3
+80001ad8:	00050863          	beqz	a0,80001ae8 <_vfiprintf_r+0x50>
+80001adc:	01852783          	lw	a5,24(a0)
+80001ae0:	00079463          	bnez	a5,80001ae8 <_vfiprintf_r+0x50>
+80001ae4:	b61ff0ef          	jal	ra,80001644 <__sinit>
+80001ae8:	00001797          	auipc	a5,0x1
+80001aec:	5c478793          	addi	a5,a5,1476 # 800030ac <__sf_fake_stdin>
+80001af0:	12f49263          	bne	s1,a5,80001c14 <_vfiprintf_r+0x17c>
+80001af4:	0049a483          	lw	s1,4(s3)
+80001af8:	00c4d783          	lhu	a5,12(s1)
+80001afc:	0087f793          	andi	a5,a5,8
+80001b00:	12078e63          	beqz	a5,80001c3c <_vfiprintf_r+0x1a4>
+80001b04:	0104a783          	lw	a5,16(s1)
+80001b08:	12078a63          	beqz	a5,80001c3c <_vfiprintf_r+0x1a4>
+80001b0c:	02000793          	li	a5,32
+80001b10:	02f104a3          	sb	a5,41(sp)
+80001b14:	03000793          	li	a5,48
+80001b18:	02012223          	sw	zero,36(sp)
+80001b1c:	02f10523          	sb	a5,42(sp)
+80001b20:	00812623          	sw	s0,12(sp)
+80001b24:	02500b93          	li	s7,37
+80001b28:	00001a97          	auipc	s5,0x1
+80001b2c:	5c4a8a93          	addi	s5,s5,1476 # 800030ec <__sf_fake_stdout+0x20>
+80001b30:	00100c13          	li	s8,1
+80001b34:	00a00b13          	li	s6,10
+80001b38:	00090413          	mv	s0,s2
+80001b3c:	00044783          	lbu	a5,0(s0)
+80001b40:	00078463          	beqz	a5,80001b48 <_vfiprintf_r+0xb0>
+80001b44:	15779063          	bne	a5,s7,80001c84 <_vfiprintf_r+0x1ec>
+80001b48:	41240cb3          	sub	s9,s0,s2
+80001b4c:	020c8663          	beqz	s9,80001b78 <_vfiprintf_r+0xe0>
+80001b50:	000c8693          	mv	a3,s9
+80001b54:	00090613          	mv	a2,s2
+80001b58:	00048593          	mv	a1,s1
+80001b5c:	00098513          	mv	a0,s3
+80001b60:	ec5ff0ef          	jal	ra,80001a24 <__sfputs_r>
+80001b64:	fff00793          	li	a5,-1
+80001b68:	2cf50263          	beq	a0,a5,80001e2c <_vfiprintf_r+0x394>
+80001b6c:	02412683          	lw	a3,36(sp)
+80001b70:	019686b3          	add	a3,a3,s9
+80001b74:	02d12223          	sw	a3,36(sp)
+80001b78:	00044783          	lbu	a5,0(s0)
+80001b7c:	2a078863          	beqz	a5,80001e2c <_vfiprintf_r+0x394>
+80001b80:	fff00793          	li	a5,-1
+80001b84:	00140913          	addi	s2,s0,1
+80001b88:	00012823          	sw	zero,16(sp)
+80001b8c:	00012e23          	sw	zero,28(sp)
+80001b90:	00f12a23          	sw	a5,20(sp)
+80001b94:	00012c23          	sw	zero,24(sp)
+80001b98:	040109a3          	sb	zero,83(sp)
+80001b9c:	06012423          	sw	zero,104(sp)
+80001ba0:	00094583          	lbu	a1,0(s2)
+80001ba4:	00500613          	li	a2,5
+80001ba8:	000a8513          	mv	a0,s5
+80001bac:	0f8010ef          	jal	ra,80002ca4 <memchr>
+80001bb0:	00190413          	addi	s0,s2,1
+80001bb4:	01012783          	lw	a5,16(sp)
+80001bb8:	0c051a63          	bnez	a0,80001c8c <_vfiprintf_r+0x1f4>
+80001bbc:	0107f713          	andi	a4,a5,16
+80001bc0:	00070663          	beqz	a4,80001bcc <_vfiprintf_r+0x134>
+80001bc4:	02000713          	li	a4,32
+80001bc8:	04e109a3          	sb	a4,83(sp)
+80001bcc:	0087f713          	andi	a4,a5,8
+80001bd0:	00070663          	beqz	a4,80001bdc <_vfiprintf_r+0x144>
+80001bd4:	02b00713          	li	a4,43
+80001bd8:	04e109a3          	sb	a4,83(sp)
+80001bdc:	00094683          	lbu	a3,0(s2)
+80001be0:	02a00713          	li	a4,42
+80001be4:	0ce68063          	beq	a3,a4,80001ca4 <_vfiprintf_r+0x20c>
+80001be8:	01c12783          	lw	a5,28(sp)
+80001bec:	00090413          	mv	s0,s2
+80001bf0:	00000693          	li	a3,0
+80001bf4:	00900613          	li	a2,9
+80001bf8:	00044703          	lbu	a4,0(s0)
+80001bfc:	00140593          	addi	a1,s0,1
+80001c00:	fd070713          	addi	a4,a4,-48
+80001c04:	10e67263          	bgeu	a2,a4,80001d08 <_vfiprintf_r+0x270>
+80001c08:	0a068a63          	beqz	a3,80001cbc <_vfiprintf_r+0x224>
+80001c0c:	00f12e23          	sw	a5,28(sp)
+80001c10:	0ac0006f          	j	80001cbc <_vfiprintf_r+0x224>
+80001c14:	00001797          	auipc	a5,0x1
+80001c18:	4b878793          	addi	a5,a5,1208 # 800030cc <__sf_fake_stdout>
+80001c1c:	00f49663          	bne	s1,a5,80001c28 <_vfiprintf_r+0x190>
+80001c20:	0089a483          	lw	s1,8(s3)
+80001c24:	ed5ff06f          	j	80001af8 <_vfiprintf_r+0x60>
+80001c28:	00001797          	auipc	a5,0x1
+80001c2c:	46478793          	addi	a5,a5,1124 # 8000308c <__sf_fake_stderr>
+80001c30:	ecf494e3          	bne	s1,a5,80001af8 <_vfiprintf_r+0x60>
+80001c34:	00c9a483          	lw	s1,12(s3)
+80001c38:	ec1ff06f          	j	80001af8 <_vfiprintf_r+0x60>
+80001c3c:	00048593          	mv	a1,s1
+80001c40:	00098513          	mv	a0,s3
+80001c44:	249000ef          	jal	ra,8000268c <__swsetup_r>
+80001c48:	ec0502e3          	beqz	a0,80001b0c <_vfiprintf_r+0x74>
+80001c4c:	fff00513          	li	a0,-1
+80001c50:	09c12083          	lw	ra,156(sp)
+80001c54:	09812403          	lw	s0,152(sp)
+80001c58:	09412483          	lw	s1,148(sp)
+80001c5c:	09012903          	lw	s2,144(sp)
+80001c60:	08c12983          	lw	s3,140(sp)
+80001c64:	08812a03          	lw	s4,136(sp)
+80001c68:	08412a83          	lw	s5,132(sp)
+80001c6c:	08012b03          	lw	s6,128(sp)
+80001c70:	07c12b83          	lw	s7,124(sp)
+80001c74:	07812c03          	lw	s8,120(sp)
+80001c78:	07412c83          	lw	s9,116(sp)
+80001c7c:	0a010113          	addi	sp,sp,160
+80001c80:	00008067          	ret
+80001c84:	00140413          	addi	s0,s0,1
+80001c88:	eb5ff06f          	j	80001b3c <_vfiprintf_r+0xa4>
+80001c8c:	41550533          	sub	a0,a0,s5
+80001c90:	00ac1533          	sll	a0,s8,a0
+80001c94:	00a7e7b3          	or	a5,a5,a0
+80001c98:	00f12823          	sw	a5,16(sp)
+80001c9c:	00040913          	mv	s2,s0
+80001ca0:	f01ff06f          	j	80001ba0 <_vfiprintf_r+0x108>
+80001ca4:	00c12703          	lw	a4,12(sp)
+80001ca8:	00470693          	addi	a3,a4,4
+80001cac:	00072703          	lw	a4,0(a4)
+80001cb0:	00d12623          	sw	a3,12(sp)
+80001cb4:	04074063          	bltz	a4,80001cf4 <_vfiprintf_r+0x25c>
+80001cb8:	00e12e23          	sw	a4,28(sp)
+80001cbc:	00044703          	lbu	a4,0(s0)
+80001cc0:	02e00793          	li	a5,46
+80001cc4:	08f71463          	bne	a4,a5,80001d4c <_vfiprintf_r+0x2b4>
+80001cc8:	00144703          	lbu	a4,1(s0)
+80001ccc:	02a00793          	li	a5,42
+80001cd0:	04f71a63          	bne	a4,a5,80001d24 <_vfiprintf_r+0x28c>
+80001cd4:	00c12783          	lw	a5,12(sp)
+80001cd8:	00240413          	addi	s0,s0,2
+80001cdc:	00478713          	addi	a4,a5,4
+80001ce0:	0007a783          	lw	a5,0(a5)
+80001ce4:	00e12623          	sw	a4,12(sp)
+80001ce8:	0207ca63          	bltz	a5,80001d1c <_vfiprintf_r+0x284>
+80001cec:	00f12a23          	sw	a5,20(sp)
+80001cf0:	05c0006f          	j	80001d4c <_vfiprintf_r+0x2b4>
+80001cf4:	40e00733          	neg	a4,a4
+80001cf8:	0027e793          	ori	a5,a5,2
+80001cfc:	00e12e23          	sw	a4,28(sp)
+80001d00:	00f12823          	sw	a5,16(sp)
+80001d04:	fb9ff06f          	j	80001cbc <_vfiprintf_r+0x224>
+80001d08:	036787b3          	mul	a5,a5,s6
+80001d0c:	00100693          	li	a3,1
+80001d10:	00058413          	mv	s0,a1
+80001d14:	00e787b3          	add	a5,a5,a4
+80001d18:	ee1ff06f          	j	80001bf8 <_vfiprintf_r+0x160>
+80001d1c:	fff00793          	li	a5,-1
+80001d20:	fcdff06f          	j	80001cec <_vfiprintf_r+0x254>
+80001d24:	00140413          	addi	s0,s0,1
+80001d28:	00012a23          	sw	zero,20(sp)
+80001d2c:	00000693          	li	a3,0
+80001d30:	00000793          	li	a5,0
+80001d34:	00900613          	li	a2,9
+80001d38:	00044703          	lbu	a4,0(s0)
+80001d3c:	00140593          	addi	a1,s0,1
+80001d40:	fd070713          	addi	a4,a4,-48
+80001d44:	08e67c63          	bgeu	a2,a4,80001ddc <_vfiprintf_r+0x344>
+80001d48:	fa0692e3          	bnez	a3,80001cec <_vfiprintf_r+0x254>
+80001d4c:	00044583          	lbu	a1,0(s0)
+80001d50:	00300613          	li	a2,3
+80001d54:	00001517          	auipc	a0,0x1
+80001d58:	3a050513          	addi	a0,a0,928 # 800030f4 <__sf_fake_stdout+0x28>
+80001d5c:	749000ef          	jal	ra,80002ca4 <memchr>
+80001d60:	02050463          	beqz	a0,80001d88 <_vfiprintf_r+0x2f0>
+80001d64:	00001797          	auipc	a5,0x1
+80001d68:	39078793          	addi	a5,a5,912 # 800030f4 <__sf_fake_stdout+0x28>
+80001d6c:	40f50533          	sub	a0,a0,a5
+80001d70:	04000793          	li	a5,64
+80001d74:	00a797b3          	sll	a5,a5,a0
+80001d78:	01012503          	lw	a0,16(sp)
+80001d7c:	00140413          	addi	s0,s0,1
+80001d80:	00f56533          	or	a0,a0,a5
+80001d84:	00a12823          	sw	a0,16(sp)
+80001d88:	00044583          	lbu	a1,0(s0)
+80001d8c:	00600613          	li	a2,6
+80001d90:	00001517          	auipc	a0,0x1
+80001d94:	36850513          	addi	a0,a0,872 # 800030f8 <__sf_fake_stdout+0x2c>
+80001d98:	00140913          	addi	s2,s0,1
+80001d9c:	02b10423          	sb	a1,40(sp)
+80001da0:	705000ef          	jal	ra,80002ca4 <memchr>
+80001da4:	08050e63          	beqz	a0,80001e40 <_vfiprintf_r+0x3a8>
+80001da8:	7fffe797          	auipc	a5,0x7fffe
+80001dac:	25878793          	addi	a5,a5,600 # 0 <__global_pointer$+0x7fffb800>
+80001db0:	04079863          	bnez	a5,80001e00 <_vfiprintf_r+0x368>
+80001db4:	01012703          	lw	a4,16(sp)
+80001db8:	00c12783          	lw	a5,12(sp)
+80001dbc:	10077713          	andi	a4,a4,256
+80001dc0:	02070863          	beqz	a4,80001df0 <_vfiprintf_r+0x358>
+80001dc4:	00478793          	addi	a5,a5,4
+80001dc8:	00f12623          	sw	a5,12(sp)
+80001dcc:	02412783          	lw	a5,36(sp)
+80001dd0:	014787b3          	add	a5,a5,s4
+80001dd4:	02f12223          	sw	a5,36(sp)
+80001dd8:	d61ff06f          	j	80001b38 <_vfiprintf_r+0xa0>
+80001ddc:	036787b3          	mul	a5,a5,s6
+80001de0:	00100693          	li	a3,1
+80001de4:	00058413          	mv	s0,a1
+80001de8:	00e787b3          	add	a5,a5,a4
+80001dec:	f4dff06f          	j	80001d38 <_vfiprintf_r+0x2a0>
+80001df0:	00778793          	addi	a5,a5,7
+80001df4:	ff87f793          	andi	a5,a5,-8
+80001df8:	00878793          	addi	a5,a5,8
+80001dfc:	fcdff06f          	j	80001dc8 <_vfiprintf_r+0x330>
+80001e00:	00c10713          	addi	a4,sp,12
+80001e04:	00000697          	auipc	a3,0x0
+80001e08:	c2068693          	addi	a3,a3,-992 # 80001a24 <__sfputs_r>
+80001e0c:	00048613          	mv	a2,s1
+80001e10:	01010593          	addi	a1,sp,16
+80001e14:	00098513          	mv	a0,s3
+80001e18:	00000097          	auipc	ra,0x0
+80001e1c:	000000e7          	jalr	zero # 0 <HEAP_SIZE>
+80001e20:	fff00793          	li	a5,-1
+80001e24:	00050a13          	mv	s4,a0
+80001e28:	faf512e3          	bne	a0,a5,80001dcc <_vfiprintf_r+0x334>
+80001e2c:	00c4d783          	lhu	a5,12(s1)
+80001e30:	0407f793          	andi	a5,a5,64
+80001e34:	e0079ce3          	bnez	a5,80001c4c <_vfiprintf_r+0x1b4>
+80001e38:	02412503          	lw	a0,36(sp)
+80001e3c:	e15ff06f          	j	80001c50 <_vfiprintf_r+0x1b8>
+80001e40:	00c10713          	addi	a4,sp,12
+80001e44:	00000697          	auipc	a3,0x0
+80001e48:	be068693          	addi	a3,a3,-1056 # 80001a24 <__sfputs_r>
+80001e4c:	00048613          	mv	a2,s1
+80001e50:	01010593          	addi	a1,sp,16
+80001e54:	00098513          	mv	a0,s3
+80001e58:	1b8000ef          	jal	ra,80002010 <_printf_i>
+80001e5c:	fc5ff06f          	j	80001e20 <_vfiprintf_r+0x388>
+
+80001e60 <_printf_common>:
+_printf_common():
+80001e60:	fd010113          	addi	sp,sp,-48
+80001e64:	01512a23          	sw	s5,20(sp)
+80001e68:	0105a783          	lw	a5,16(a1)
+80001e6c:	00070a93          	mv	s5,a4
+80001e70:	0085a703          	lw	a4,8(a1)
+80001e74:	02812423          	sw	s0,40(sp)
+80001e78:	02912223          	sw	s1,36(sp)
+80001e7c:	01312e23          	sw	s3,28(sp)
+80001e80:	01412c23          	sw	s4,24(sp)
+80001e84:	02112623          	sw	ra,44(sp)
+80001e88:	03212023          	sw	s2,32(sp)
+80001e8c:	01612823          	sw	s6,16(sp)
+80001e90:	01712623          	sw	s7,12(sp)
+80001e94:	00050993          	mv	s3,a0
+80001e98:	00058413          	mv	s0,a1
+80001e9c:	00060493          	mv	s1,a2
+80001ea0:	00068a13          	mv	s4,a3
+80001ea4:	00e7d463          	bge	a5,a4,80001eac <_printf_common+0x4c>
+80001ea8:	00070793          	mv	a5,a4
+80001eac:	00f4a023          	sw	a5,0(s1)
+80001eb0:	04344703          	lbu	a4,67(s0)
+80001eb4:	00070663          	beqz	a4,80001ec0 <_printf_common+0x60>
+80001eb8:	00178793          	addi	a5,a5,1
+80001ebc:	00f4a023          	sw	a5,0(s1)
+80001ec0:	00042783          	lw	a5,0(s0)
+80001ec4:	0207f793          	andi	a5,a5,32
+80001ec8:	00078863          	beqz	a5,80001ed8 <_printf_common+0x78>
+80001ecc:	0004a783          	lw	a5,0(s1)
+80001ed0:	00278793          	addi	a5,a5,2
+80001ed4:	00f4a023          	sw	a5,0(s1)
+80001ed8:	00042903          	lw	s2,0(s0)
+80001edc:	00697913          	andi	s2,s2,6
+80001ee0:	00091e63          	bnez	s2,80001efc <_printf_common+0x9c>
+80001ee4:	01940b13          	addi	s6,s0,25
+80001ee8:	fff00b93          	li	s7,-1
+80001eec:	00c42783          	lw	a5,12(s0)
+80001ef0:	0004a703          	lw	a4,0(s1)
+80001ef4:	40e787b3          	sub	a5,a5,a4
+80001ef8:	08f94263          	blt	s2,a5,80001f7c <_printf_common+0x11c>
+80001efc:	00042783          	lw	a5,0(s0)
+80001f00:	04344683          	lbu	a3,67(s0)
+80001f04:	0207f793          	andi	a5,a5,32
+80001f08:	00d036b3          	snez	a3,a3
+80001f0c:	0c079063          	bnez	a5,80001fcc <_printf_common+0x16c>
+80001f10:	04340613          	addi	a2,s0,67
+80001f14:	000a0593          	mv	a1,s4
+80001f18:	00098513          	mv	a0,s3
+80001f1c:	000a80e7          	jalr	s5
+80001f20:	fff00793          	li	a5,-1
+80001f24:	06f50863          	beq	a0,a5,80001f94 <_printf_common+0x134>
+80001f28:	00042783          	lw	a5,0(s0)
+80001f2c:	00400613          	li	a2,4
+80001f30:	0004a703          	lw	a4,0(s1)
+80001f34:	0067f793          	andi	a5,a5,6
+80001f38:	00c42683          	lw	a3,12(s0)
+80001f3c:	00000493          	li	s1,0
+80001f40:	00c79863          	bne	a5,a2,80001f50 <_printf_common+0xf0>
+80001f44:	40e684b3          	sub	s1,a3,a4
+80001f48:	0004d463          	bgez	s1,80001f50 <_printf_common+0xf0>
+80001f4c:	00000493          	li	s1,0
+80001f50:	00842783          	lw	a5,8(s0)
+80001f54:	01042703          	lw	a4,16(s0)
+80001f58:	00f75663          	bge	a4,a5,80001f64 <_printf_common+0x104>
+80001f5c:	40e787b3          	sub	a5,a5,a4
+80001f60:	00f484b3          	add	s1,s1,a5
+80001f64:	00000913          	li	s2,0
+80001f68:	01a40413          	addi	s0,s0,26
+80001f6c:	fff00b13          	li	s6,-1
+80001f70:	09249063          	bne	s1,s2,80001ff0 <_printf_common+0x190>
+80001f74:	00000513          	li	a0,0
+80001f78:	0200006f          	j	80001f98 <_printf_common+0x138>
+80001f7c:	00100693          	li	a3,1
+80001f80:	000b0613          	mv	a2,s6
+80001f84:	000a0593          	mv	a1,s4
+80001f88:	00098513          	mv	a0,s3
+80001f8c:	000a80e7          	jalr	s5
+80001f90:	03751a63          	bne	a0,s7,80001fc4 <_printf_common+0x164>
+80001f94:	fff00513          	li	a0,-1
+80001f98:	02c12083          	lw	ra,44(sp)
+80001f9c:	02812403          	lw	s0,40(sp)
+80001fa0:	02412483          	lw	s1,36(sp)
+80001fa4:	02012903          	lw	s2,32(sp)
+80001fa8:	01c12983          	lw	s3,28(sp)
+80001fac:	01812a03          	lw	s4,24(sp)
+80001fb0:	01412a83          	lw	s5,20(sp)
+80001fb4:	01012b03          	lw	s6,16(sp)
+80001fb8:	00c12b83          	lw	s7,12(sp)
+80001fbc:	03010113          	addi	sp,sp,48
+80001fc0:	00008067          	ret
+80001fc4:	00190913          	addi	s2,s2,1
+80001fc8:	f25ff06f          	j	80001eec <_printf_common+0x8c>
+80001fcc:	00d40733          	add	a4,s0,a3
+80001fd0:	03000613          	li	a2,48
+80001fd4:	04c701a3          	sb	a2,67(a4)
+80001fd8:	04544703          	lbu	a4,69(s0)
+80001fdc:	00168793          	addi	a5,a3,1
+80001fe0:	00f407b3          	add	a5,s0,a5
+80001fe4:	00268693          	addi	a3,a3,2
+80001fe8:	04e781a3          	sb	a4,67(a5)
+80001fec:	f25ff06f          	j	80001f10 <_printf_common+0xb0>
+80001ff0:	00100693          	li	a3,1
+80001ff4:	00040613          	mv	a2,s0
+80001ff8:	000a0593          	mv	a1,s4
+80001ffc:	00098513          	mv	a0,s3
+80002000:	000a80e7          	jalr	s5
+80002004:	f96508e3          	beq	a0,s6,80001f94 <_printf_common+0x134>
+80002008:	00190913          	addi	s2,s2,1
+8000200c:	f65ff06f          	j	80001f70 <_printf_common+0x110>
+
+80002010 <_printf_i>:
+_printf_i():
+80002010:	fd010113          	addi	sp,sp,-48
+80002014:	02812423          	sw	s0,40(sp)
+80002018:	02912223          	sw	s1,36(sp)
+8000201c:	03212023          	sw	s2,32(sp)
+80002020:	01312e23          	sw	s3,28(sp)
+80002024:	02112623          	sw	ra,44(sp)
+80002028:	01412c23          	sw	s4,24(sp)
+8000202c:	01512a23          	sw	s5,20(sp)
+80002030:	01612823          	sw	s6,16(sp)
+80002034:	00068993          	mv	s3,a3
+80002038:	0185c683          	lbu	a3,24(a1)
+8000203c:	06e00793          	li	a5,110
+80002040:	00060913          	mv	s2,a2
+80002044:	00050493          	mv	s1,a0
+80002048:	00058413          	mv	s0,a1
+8000204c:	04358613          	addi	a2,a1,67
+80002050:	28f68863          	beq	a3,a5,800022e0 <_printf_i+0x2d0>
+80002054:	06d7ea63          	bltu	a5,a3,800020c8 <_printf_i+0xb8>
+80002058:	06300793          	li	a5,99
+8000205c:	0af68e63          	beq	a3,a5,80002118 <_printf_i+0x108>
+80002060:	00d7ee63          	bltu	a5,a3,8000207c <_printf_i+0x6c>
+80002064:	2a068c63          	beqz	a3,8000231c <_printf_i+0x30c>
+80002068:	05800793          	li	a5,88
+8000206c:	1ef68a63          	beq	a3,a5,80002260 <_printf_i+0x250>
+80002070:	04240a93          	addi	s5,s0,66
+80002074:	04d40123          	sb	a3,66(s0)
+80002078:	0b80006f          	j	80002130 <_printf_i+0x120>
+8000207c:	06400793          	li	a5,100
+80002080:	00f68663          	beq	a3,a5,8000208c <_printf_i+0x7c>
+80002084:	06900793          	li	a5,105
+80002088:	fef694e3          	bne	a3,a5,80002070 <_printf_i+0x60>
+8000208c:	00042783          	lw	a5,0(s0)
+80002090:	00072503          	lw	a0,0(a4)
+80002094:	0807f693          	andi	a3,a5,128
+80002098:	00450593          	addi	a1,a0,4
+8000209c:	08068e63          	beqz	a3,80002138 <_printf_i+0x128>
+800020a0:	00052783          	lw	a5,0(a0)
+800020a4:	00b72023          	sw	a1,0(a4)
+800020a8:	0007d863          	bgez	a5,800020b8 <_printf_i+0xa8>
+800020ac:	02d00713          	li	a4,45
+800020b0:	40f007b3          	neg	a5,a5
+800020b4:	04e401a3          	sb	a4,67(s0)
+800020b8:	00001697          	auipc	a3,0x1
+800020bc:	04868693          	addi	a3,a3,72 # 80003100 <__sf_fake_stdout+0x34>
+800020c0:	00a00713          	li	a4,10
+800020c4:	0d80006f          	j	8000219c <_printf_i+0x18c>
+800020c8:	07300793          	li	a5,115
+800020cc:	24f68e63          	beq	a3,a5,80002328 <_printf_i+0x318>
+800020d0:	02d7e263          	bltu	a5,a3,800020f4 <_printf_i+0xe4>
+800020d4:	06f00793          	li	a5,111
+800020d8:	06f68e63          	beq	a3,a5,80002154 <_printf_i+0x144>
+800020dc:	07000793          	li	a5,112
+800020e0:	f8f698e3          	bne	a3,a5,80002070 <_printf_i+0x60>
+800020e4:	0005a783          	lw	a5,0(a1)
+800020e8:	0207e793          	ori	a5,a5,32
+800020ec:	00f5a023          	sw	a5,0(a1)
+800020f0:	0140006f          	j	80002104 <_printf_i+0xf4>
+800020f4:	07500793          	li	a5,117
+800020f8:	04f68e63          	beq	a3,a5,80002154 <_printf_i+0x144>
+800020fc:	07800793          	li	a5,120
+80002100:	f6f698e3          	bne	a3,a5,80002070 <_printf_i+0x60>
+80002104:	07800793          	li	a5,120
+80002108:	04f402a3          	sb	a5,69(s0)
+8000210c:	00001697          	auipc	a3,0x1
+80002110:	00868693          	addi	a3,a3,8 # 80003114 <__sf_fake_stdout+0x48>
+80002114:	1580006f          	j	8000226c <_printf_i+0x25c>
+80002118:	00072783          	lw	a5,0(a4)
+8000211c:	04258a93          	addi	s5,a1,66
+80002120:	00478693          	addi	a3,a5,4
+80002124:	0007a783          	lw	a5,0(a5)
+80002128:	00d72023          	sw	a3,0(a4)
+8000212c:	04f58123          	sb	a5,66(a1)
+80002130:	00100793          	li	a5,1
+80002134:	2240006f          	j	80002358 <_printf_i+0x348>
+80002138:	0407f693          	andi	a3,a5,64
+8000213c:	00052783          	lw	a5,0(a0)
+80002140:	00b72023          	sw	a1,0(a4)
+80002144:	f60682e3          	beqz	a3,800020a8 <_printf_i+0x98>
+80002148:	01079793          	slli	a5,a5,0x10
+8000214c:	4107d793          	srai	a5,a5,0x10
+80002150:	f59ff06f          	j	800020a8 <_printf_i+0x98>
+80002154:	00042583          	lw	a1,0(s0)
+80002158:	00072783          	lw	a5,0(a4)
+8000215c:	0805f813          	andi	a6,a1,128
+80002160:	00478513          	addi	a0,a5,4
+80002164:	00080863          	beqz	a6,80002174 <_printf_i+0x164>
+80002168:	00a72023          	sw	a0,0(a4)
+8000216c:	0007a783          	lw	a5,0(a5)
+80002170:	0140006f          	j	80002184 <_printf_i+0x174>
+80002174:	0405f593          	andi	a1,a1,64
+80002178:	00a72023          	sw	a0,0(a4)
+8000217c:	fe0588e3          	beqz	a1,8000216c <_printf_i+0x15c>
+80002180:	0007d783          	lhu	a5,0(a5)
+80002184:	06f00713          	li	a4,111
+80002188:	14e68063          	beq	a3,a4,800022c8 <_printf_i+0x2b8>
+8000218c:	00001697          	auipc	a3,0x1
+80002190:	f7468693          	addi	a3,a3,-140 # 80003100 <__sf_fake_stdout+0x34>
+80002194:	00a00713          	li	a4,10
+80002198:	040401a3          	sb	zero,67(s0)
+8000219c:	00442583          	lw	a1,4(s0)
+800021a0:	00b42423          	sw	a1,8(s0)
+800021a4:	0005c863          	bltz	a1,800021b4 <_printf_i+0x1a4>
+800021a8:	00042503          	lw	a0,0(s0)
+800021ac:	ffb57513          	andi	a0,a0,-5
+800021b0:	00a42023          	sw	a0,0(s0)
+800021b4:	00079663          	bnez	a5,800021c0 <_printf_i+0x1b0>
+800021b8:	00060a93          	mv	s5,a2
+800021bc:	02058263          	beqz	a1,800021e0 <_printf_i+0x1d0>
+800021c0:	00060a93          	mv	s5,a2
+800021c4:	02e7f5b3          	remu	a1,a5,a4
+800021c8:	fffa8a93          	addi	s5,s5,-1
+800021cc:	00b685b3          	add	a1,a3,a1
+800021d0:	0005c583          	lbu	a1,0(a1)
+800021d4:	00ba8023          	sb	a1,0(s5)
+800021d8:	02e7d5b3          	divu	a1,a5,a4
+800021dc:	0ee7fe63          	bgeu	a5,a4,800022d8 <_printf_i+0x2c8>
+800021e0:	00800793          	li	a5,8
+800021e4:	02f71463          	bne	a4,a5,8000220c <_printf_i+0x1fc>
+800021e8:	00042783          	lw	a5,0(s0)
+800021ec:	0017f793          	andi	a5,a5,1
+800021f0:	00078e63          	beqz	a5,8000220c <_printf_i+0x1fc>
+800021f4:	00442703          	lw	a4,4(s0)
+800021f8:	01042783          	lw	a5,16(s0)
+800021fc:	00e7c863          	blt	a5,a4,8000220c <_printf_i+0x1fc>
+80002200:	03000793          	li	a5,48
+80002204:	fefa8fa3          	sb	a5,-1(s5)
+80002208:	fffa8a93          	addi	s5,s5,-1
+8000220c:	41560633          	sub	a2,a2,s5
+80002210:	00c42823          	sw	a2,16(s0)
+80002214:	00098713          	mv	a4,s3
+80002218:	00090693          	mv	a3,s2
+8000221c:	00c10613          	addi	a2,sp,12
+80002220:	00040593          	mv	a1,s0
+80002224:	00048513          	mv	a0,s1
+80002228:	c39ff0ef          	jal	ra,80001e60 <_printf_common>
+8000222c:	fff00a13          	li	s4,-1
+80002230:	13451a63          	bne	a0,s4,80002364 <_printf_i+0x354>
+80002234:	fff00513          	li	a0,-1
+80002238:	02c12083          	lw	ra,44(sp)
+8000223c:	02812403          	lw	s0,40(sp)
+80002240:	02412483          	lw	s1,36(sp)
+80002244:	02012903          	lw	s2,32(sp)
+80002248:	01c12983          	lw	s3,28(sp)
+8000224c:	01812a03          	lw	s4,24(sp)
+80002250:	01412a83          	lw	s5,20(sp)
+80002254:	01012b03          	lw	s6,16(sp)
+80002258:	03010113          	addi	sp,sp,48
+8000225c:	00008067          	ret
+80002260:	04d582a3          	sb	a3,69(a1)
+80002264:	00001697          	auipc	a3,0x1
+80002268:	e9c68693          	addi	a3,a3,-356 # 80003100 <__sf_fake_stdout+0x34>
+8000226c:	00042583          	lw	a1,0(s0)
+80002270:	00072503          	lw	a0,0(a4)
+80002274:	0805f813          	andi	a6,a1,128
+80002278:	00052783          	lw	a5,0(a0)
+8000227c:	00450513          	addi	a0,a0,4
+80002280:	02080863          	beqz	a6,800022b0 <_printf_i+0x2a0>
+80002284:	00a72023          	sw	a0,0(a4)
+80002288:	0015f713          	andi	a4,a1,1
+8000228c:	00070663          	beqz	a4,80002298 <_printf_i+0x288>
+80002290:	0205e593          	ori	a1,a1,32
+80002294:	00b42023          	sw	a1,0(s0)
+80002298:	01000713          	li	a4,16
+8000229c:	ee079ee3          	bnez	a5,80002198 <_printf_i+0x188>
+800022a0:	00042583          	lw	a1,0(s0)
+800022a4:	fdf5f593          	andi	a1,a1,-33
+800022a8:	00b42023          	sw	a1,0(s0)
+800022ac:	eedff06f          	j	80002198 <_printf_i+0x188>
+800022b0:	0405f813          	andi	a6,a1,64
+800022b4:	00a72023          	sw	a0,0(a4)
+800022b8:	fc0808e3          	beqz	a6,80002288 <_printf_i+0x278>
+800022bc:	01079793          	slli	a5,a5,0x10
+800022c0:	0107d793          	srli	a5,a5,0x10
+800022c4:	fc5ff06f          	j	80002288 <_printf_i+0x278>
+800022c8:	00001697          	auipc	a3,0x1
+800022cc:	e3868693          	addi	a3,a3,-456 # 80003100 <__sf_fake_stdout+0x34>
+800022d0:	00800713          	li	a4,8
+800022d4:	ec5ff06f          	j	80002198 <_printf_i+0x188>
+800022d8:	00058793          	mv	a5,a1
+800022dc:	ee9ff06f          	j	800021c4 <_printf_i+0x1b4>
+800022e0:	0005a683          	lw	a3,0(a1)
+800022e4:	00072783          	lw	a5,0(a4)
+800022e8:	0145a583          	lw	a1,20(a1)
+800022ec:	0806f813          	andi	a6,a3,128
+800022f0:	00478513          	addi	a0,a5,4
+800022f4:	00080a63          	beqz	a6,80002308 <_printf_i+0x2f8>
+800022f8:	00a72023          	sw	a0,0(a4)
+800022fc:	0007a783          	lw	a5,0(a5)
+80002300:	00b7a023          	sw	a1,0(a5)
+80002304:	0180006f          	j	8000231c <_printf_i+0x30c>
+80002308:	00a72023          	sw	a0,0(a4)
+8000230c:	0406f693          	andi	a3,a3,64
+80002310:	0007a783          	lw	a5,0(a5)
+80002314:	fe0686e3          	beqz	a3,80002300 <_printf_i+0x2f0>
+80002318:	00b79023          	sh	a1,0(a5)
+8000231c:	00042823          	sw	zero,16(s0)
+80002320:	00060a93          	mv	s5,a2
+80002324:	ef1ff06f          	j	80002214 <_printf_i+0x204>
+80002328:	00072783          	lw	a5,0(a4)
+8000232c:	0045a603          	lw	a2,4(a1)
+80002330:	00000593          	li	a1,0
+80002334:	00478693          	addi	a3,a5,4
+80002338:	00d72023          	sw	a3,0(a4)
+8000233c:	0007aa83          	lw	s5,0(a5)
+80002340:	000a8513          	mv	a0,s5
+80002344:	161000ef          	jal	ra,80002ca4 <memchr>
+80002348:	00050663          	beqz	a0,80002354 <_printf_i+0x344>
+8000234c:	41550533          	sub	a0,a0,s5
+80002350:	00a42223          	sw	a0,4(s0)
+80002354:	00442783          	lw	a5,4(s0)
+80002358:	00f42823          	sw	a5,16(s0)
+8000235c:	040401a3          	sb	zero,67(s0)
+80002360:	eb5ff06f          	j	80002214 <_printf_i+0x204>
+80002364:	01042683          	lw	a3,16(s0)
+80002368:	000a8613          	mv	a2,s5
+8000236c:	00090593          	mv	a1,s2
+80002370:	00048513          	mv	a0,s1
+80002374:	000980e7          	jalr	s3
+80002378:	eb450ee3          	beq	a0,s4,80002234 <_printf_i+0x224>
+8000237c:	00042783          	lw	a5,0(s0)
+80002380:	0027f793          	andi	a5,a5,2
+80002384:	04079463          	bnez	a5,800023cc <_printf_i+0x3bc>
+80002388:	00c12783          	lw	a5,12(sp)
+8000238c:	00c42503          	lw	a0,12(s0)
+80002390:	eaf554e3          	bge	a0,a5,80002238 <_printf_i+0x228>
+80002394:	00078513          	mv	a0,a5
+80002398:	ea1ff06f          	j	80002238 <_printf_i+0x228>
+8000239c:	00100693          	li	a3,1
+800023a0:	000a8613          	mv	a2,s5
+800023a4:	00090593          	mv	a1,s2
+800023a8:	00048513          	mv	a0,s1
+800023ac:	000980e7          	jalr	s3
+800023b0:	e96502e3          	beq	a0,s6,80002234 <_printf_i+0x224>
+800023b4:	001a0a13          	addi	s4,s4,1
+800023b8:	00c42783          	lw	a5,12(s0)
+800023bc:	00c12703          	lw	a4,12(sp)
+800023c0:	40e787b3          	sub	a5,a5,a4
+800023c4:	fcfa4ce3          	blt	s4,a5,8000239c <_printf_i+0x38c>
+800023c8:	fc1ff06f          	j	80002388 <_printf_i+0x378>
+800023cc:	00000a13          	li	s4,0
+800023d0:	01940a93          	addi	s5,s0,25
+800023d4:	fff00b13          	li	s6,-1
+800023d8:	fe1ff06f          	j	800023b8 <_printf_i+0x3a8>
+
+800023dc <_sbrk_r>:
+_sbrk_r():
+800023dc:	ff010113          	addi	sp,sp,-16
+800023e0:	00812423          	sw	s0,8(sp)
+800023e4:	00050413          	mv	s0,a0
+800023e8:	00058513          	mv	a0,a1
+800023ec:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+800023f0:	00112623          	sw	ra,12(sp)
+800023f4:	9f9fe0ef          	jal	ra,80000dec <_sbrk>
+800023f8:	fff00793          	li	a5,-1
+800023fc:	00f51a63          	bne	a0,a5,80002410 <_sbrk_r+0x34>
+80002400:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002404:	0007a783          	lw	a5,0(a5)
+80002408:	00078463          	beqz	a5,80002410 <_sbrk_r+0x34>
+8000240c:	00f42023          	sw	a5,0(s0)
+80002410:	00c12083          	lw	ra,12(sp)
+80002414:	00812403          	lw	s0,8(sp)
+80002418:	01010113          	addi	sp,sp,16
+8000241c:	00008067          	ret
+
+80002420 <__sread>:
+__sread():
+80002420:	ff010113          	addi	sp,sp,-16
+80002424:	00812423          	sw	s0,8(sp)
+80002428:	00058413          	mv	s0,a1
+8000242c:	00e59583          	lh	a1,14(a1)
+80002430:	00112623          	sw	ra,12(sp)
+80002434:	1a1000ef          	jal	ra,80002dd4 <_read_r>
+80002438:	02054063          	bltz	a0,80002458 <__sread+0x38>
+8000243c:	05442783          	lw	a5,84(s0)
+80002440:	00a787b3          	add	a5,a5,a0
+80002444:	04f42a23          	sw	a5,84(s0)
+80002448:	00c12083          	lw	ra,12(sp)
+8000244c:	00812403          	lw	s0,8(sp)
+80002450:	01010113          	addi	sp,sp,16
+80002454:	00008067          	ret
+80002458:	00c45783          	lhu	a5,12(s0)
+8000245c:	fffff737          	lui	a4,0xfffff
+80002460:	fff70713          	addi	a4,a4,-1 # ffffefff <__global_pointer$+0x7fffa7ff>
+80002464:	00e7f7b3          	and	a5,a5,a4
+80002468:	00f41623          	sh	a5,12(s0)
+8000246c:	fddff06f          	j	80002448 <__sread+0x28>
+
+80002470 <__swrite>:
+__swrite():
+80002470:	00c5d783          	lhu	a5,12(a1)
+80002474:	fe010113          	addi	sp,sp,-32
+80002478:	00812c23          	sw	s0,24(sp)
+8000247c:	00912a23          	sw	s1,20(sp)
+80002480:	01212823          	sw	s2,16(sp)
+80002484:	01312623          	sw	s3,12(sp)
+80002488:	00112e23          	sw	ra,28(sp)
+8000248c:	1007f793          	andi	a5,a5,256
+80002490:	00050493          	mv	s1,a0
+80002494:	00058413          	mv	s0,a1
+80002498:	00060913          	mv	s2,a2
+8000249c:	00068993          	mv	s3,a3
+800024a0:	00078a63          	beqz	a5,800024b4 <__swrite+0x44>
+800024a4:	00e59583          	lh	a1,14(a1)
+800024a8:	00200693          	li	a3,2
+800024ac:	00000613          	li	a2,0
+800024b0:	62c000ef          	jal	ra,80002adc <_lseek_r>
+800024b4:	00c45783          	lhu	a5,12(s0)
+800024b8:	fffff737          	lui	a4,0xfffff
+800024bc:	fff70713          	addi	a4,a4,-1 # ffffefff <__global_pointer$+0x7fffa7ff>
+800024c0:	00e7f7b3          	and	a5,a5,a4
+800024c4:	00f41623          	sh	a5,12(s0)
+800024c8:	00e41583          	lh	a1,14(s0)
+800024cc:	01812403          	lw	s0,24(sp)
+800024d0:	01c12083          	lw	ra,28(sp)
+800024d4:	00098693          	mv	a3,s3
+800024d8:	00090613          	mv	a2,s2
+800024dc:	00c12983          	lw	s3,12(sp)
+800024e0:	01012903          	lw	s2,16(sp)
+800024e4:	00048513          	mv	a0,s1
+800024e8:	01412483          	lw	s1,20(sp)
+800024ec:	02010113          	addi	sp,sp,32
+800024f0:	808ff06f          	j	800014f8 <_write_r>
+
+800024f4 <__sseek>:
+__sseek():
+800024f4:	ff010113          	addi	sp,sp,-16
+800024f8:	00812423          	sw	s0,8(sp)
+800024fc:	00058413          	mv	s0,a1
+80002500:	00e59583          	lh	a1,14(a1)
+80002504:	00112623          	sw	ra,12(sp)
+80002508:	5d4000ef          	jal	ra,80002adc <_lseek_r>
+8000250c:	fff00793          	li	a5,-1
+80002510:	00c45703          	lhu	a4,12(s0)
+80002514:	02f51263          	bne	a0,a5,80002538 <__sseek+0x44>
+80002518:	fffff7b7          	lui	a5,0xfffff
+8000251c:	fff78793          	addi	a5,a5,-1 # ffffefff <__global_pointer$+0x7fffa7ff>
+80002520:	00e7f7b3          	and	a5,a5,a4
+80002524:	00f41623          	sh	a5,12(s0)
+80002528:	00c12083          	lw	ra,12(sp)
+8000252c:	00812403          	lw	s0,8(sp)
+80002530:	01010113          	addi	sp,sp,16
+80002534:	00008067          	ret
+80002538:	000017b7          	lui	a5,0x1
+8000253c:	00f767b3          	or	a5,a4,a5
+80002540:	00f41623          	sh	a5,12(s0)
+80002544:	04a42a23          	sw	a0,84(s0)
+80002548:	fe1ff06f          	j	80002528 <__sseek+0x34>
+
+8000254c <__sclose>:
+__sclose():
+8000254c:	00e59583          	lh	a1,14(a1)
+80002550:	2bc0006f          	j	8000280c <_close_r>
+
+80002554 <__swbuf_r>:
+__swbuf_r():
+80002554:	fe010113          	addi	sp,sp,-32
+80002558:	00812c23          	sw	s0,24(sp)
+8000255c:	00912a23          	sw	s1,20(sp)
+80002560:	01212823          	sw	s2,16(sp)
+80002564:	00112e23          	sw	ra,28(sp)
+80002568:	01312623          	sw	s3,12(sp)
+8000256c:	00050493          	mv	s1,a0
+80002570:	00058913          	mv	s2,a1
+80002574:	00060413          	mv	s0,a2
+80002578:	00050863          	beqz	a0,80002588 <__swbuf_r+0x34>
+8000257c:	01852783          	lw	a5,24(a0)
+80002580:	00079463          	bnez	a5,80002588 <__swbuf_r+0x34>
+80002584:	8c0ff0ef          	jal	ra,80001644 <__sinit>
+80002588:	00001797          	auipc	a5,0x1
+8000258c:	b2478793          	addi	a5,a5,-1244 # 800030ac <__sf_fake_stdin>
+80002590:	0af41e63          	bne	s0,a5,8000264c <__swbuf_r+0xf8>
+80002594:	0044a403          	lw	s0,4(s1)
+80002598:	01842783          	lw	a5,24(s0)
+8000259c:	00f42423          	sw	a5,8(s0)
+800025a0:	00c45783          	lhu	a5,12(s0)
+800025a4:	0087f793          	andi	a5,a5,8
+800025a8:	0c078663          	beqz	a5,80002674 <__swbuf_r+0x120>
+800025ac:	01042783          	lw	a5,16(s0)
+800025b0:	0c078263          	beqz	a5,80002674 <__swbuf_r+0x120>
+800025b4:	01042783          	lw	a5,16(s0)
+800025b8:	00042503          	lw	a0,0(s0)
+800025bc:	0ff97993          	andi	s3,s2,255
+800025c0:	0ff97913          	andi	s2,s2,255
+800025c4:	40f50533          	sub	a0,a0,a5
+800025c8:	01442783          	lw	a5,20(s0)
+800025cc:	00f54a63          	blt	a0,a5,800025e0 <__swbuf_r+0x8c>
+800025d0:	00040593          	mv	a1,s0
+800025d4:	00048513          	mv	a0,s1
+800025d8:	464000ef          	jal	ra,80002a3c <_fflush_r>
+800025dc:	0a051463          	bnez	a0,80002684 <__swbuf_r+0x130>
+800025e0:	00842783          	lw	a5,8(s0)
+800025e4:	00150513          	addi	a0,a0,1
+800025e8:	fff78793          	addi	a5,a5,-1
+800025ec:	00f42423          	sw	a5,8(s0)
+800025f0:	00042783          	lw	a5,0(s0)
+800025f4:	00178713          	addi	a4,a5,1
+800025f8:	00e42023          	sw	a4,0(s0)
+800025fc:	01378023          	sb	s3,0(a5)
+80002600:	01442783          	lw	a5,20(s0)
+80002604:	00a78c63          	beq	a5,a0,8000261c <__swbuf_r+0xc8>
+80002608:	00c45783          	lhu	a5,12(s0)
+8000260c:	0017f793          	andi	a5,a5,1
+80002610:	00078e63          	beqz	a5,8000262c <__swbuf_r+0xd8>
+80002614:	00a00793          	li	a5,10
+80002618:	00f91a63          	bne	s2,a5,8000262c <__swbuf_r+0xd8>
+8000261c:	00040593          	mv	a1,s0
+80002620:	00048513          	mv	a0,s1
+80002624:	418000ef          	jal	ra,80002a3c <_fflush_r>
+80002628:	04051e63          	bnez	a0,80002684 <__swbuf_r+0x130>
+8000262c:	01c12083          	lw	ra,28(sp)
+80002630:	01812403          	lw	s0,24(sp)
+80002634:	00090513          	mv	a0,s2
+80002638:	01412483          	lw	s1,20(sp)
+8000263c:	01012903          	lw	s2,16(sp)
+80002640:	00c12983          	lw	s3,12(sp)
+80002644:	02010113          	addi	sp,sp,32
+80002648:	00008067          	ret
+8000264c:	00001797          	auipc	a5,0x1
+80002650:	a8078793          	addi	a5,a5,-1408 # 800030cc <__sf_fake_stdout>
+80002654:	00f41663          	bne	s0,a5,80002660 <__swbuf_r+0x10c>
+80002658:	0084a403          	lw	s0,8(s1)
+8000265c:	f3dff06f          	j	80002598 <__swbuf_r+0x44>
+80002660:	00001797          	auipc	a5,0x1
+80002664:	a2c78793          	addi	a5,a5,-1492 # 8000308c <__sf_fake_stderr>
+80002668:	f2f418e3          	bne	s0,a5,80002598 <__swbuf_r+0x44>
+8000266c:	00c4a403          	lw	s0,12(s1)
+80002670:	f29ff06f          	j	80002598 <__swbuf_r+0x44>
+80002674:	00040593          	mv	a1,s0
+80002678:	00048513          	mv	a0,s1
+8000267c:	010000ef          	jal	ra,8000268c <__swsetup_r>
+80002680:	f2050ae3          	beqz	a0,800025b4 <__swbuf_r+0x60>
+80002684:	fff00913          	li	s2,-1
+80002688:	fa5ff06f          	j	8000262c <__swbuf_r+0xd8>
+
+8000268c <__swsetup_r>:
+__swsetup_r():
+8000268c:	ff010113          	addi	sp,sp,-16
+80002690:	00002797          	auipc	a5,0x2
+80002694:	97878793          	addi	a5,a5,-1672 # 80004008 <_impure_ptr>
+80002698:	00912223          	sw	s1,4(sp)
+8000269c:	0007a483          	lw	s1,0(a5)
+800026a0:	00812423          	sw	s0,8(sp)
+800026a4:	01212023          	sw	s2,0(sp)
+800026a8:	00112623          	sw	ra,12(sp)
+800026ac:	00050913          	mv	s2,a0
+800026b0:	00058413          	mv	s0,a1
+800026b4:	00048a63          	beqz	s1,800026c8 <__swsetup_r+0x3c>
+800026b8:	0184a783          	lw	a5,24(s1)
+800026bc:	00079663          	bnez	a5,800026c8 <__swsetup_r+0x3c>
+800026c0:	00048513          	mv	a0,s1
+800026c4:	f81fe0ef          	jal	ra,80001644 <__sinit>
+800026c8:	00001797          	auipc	a5,0x1
+800026cc:	9e478793          	addi	a5,a5,-1564 # 800030ac <__sf_fake_stdin>
+800026d0:	04f41863          	bne	s0,a5,80002720 <__swsetup_r+0x94>
+800026d4:	0044a403          	lw	s0,4(s1)
+800026d8:	00c41703          	lh	a4,12(s0)
+800026dc:	01071793          	slli	a5,a4,0x10
+800026e0:	0107d793          	srli	a5,a5,0x10
+800026e4:	0087f693          	andi	a3,a5,8
+800026e8:	0a069463          	bnez	a3,80002790 <__swsetup_r+0x104>
+800026ec:	0107f693          	andi	a3,a5,16
+800026f0:	04069c63          	bnez	a3,80002748 <__swsetup_r+0xbc>
+800026f4:	00900793          	li	a5,9
+800026f8:	00f92023          	sw	a5,0(s2)
+800026fc:	04076713          	ori	a4,a4,64
+80002700:	00e41623          	sh	a4,12(s0)
+80002704:	fff00513          	li	a0,-1
+80002708:	00c12083          	lw	ra,12(sp)
+8000270c:	00812403          	lw	s0,8(sp)
+80002710:	00412483          	lw	s1,4(sp)
+80002714:	00012903          	lw	s2,0(sp)
+80002718:	01010113          	addi	sp,sp,16
+8000271c:	00008067          	ret
+80002720:	00001797          	auipc	a5,0x1
+80002724:	9ac78793          	addi	a5,a5,-1620 # 800030cc <__sf_fake_stdout>
+80002728:	00f41663          	bne	s0,a5,80002734 <__swsetup_r+0xa8>
+8000272c:	0084a403          	lw	s0,8(s1)
+80002730:	fa9ff06f          	j	800026d8 <__swsetup_r+0x4c>
+80002734:	00001797          	auipc	a5,0x1
+80002738:	95878793          	addi	a5,a5,-1704 # 8000308c <__sf_fake_stderr>
+8000273c:	f8f41ee3          	bne	s0,a5,800026d8 <__swsetup_r+0x4c>
+80002740:	00c4a403          	lw	s0,12(s1)
+80002744:	f95ff06f          	j	800026d8 <__swsetup_r+0x4c>
+80002748:	0047f793          	andi	a5,a5,4
+8000274c:	02078c63          	beqz	a5,80002784 <__swsetup_r+0xf8>
+80002750:	03442583          	lw	a1,52(s0)
+80002754:	00058c63          	beqz	a1,8000276c <__swsetup_r+0xe0>
+80002758:	04440793          	addi	a5,s0,68
+8000275c:	00f58663          	beq	a1,a5,80002768 <__swsetup_r+0xdc>
+80002760:	00090513          	mv	a0,s2
+80002764:	56c000ef          	jal	ra,80002cd0 <_free_r>
+80002768:	02042a23          	sw	zero,52(s0)
+8000276c:	00c45783          	lhu	a5,12(s0)
+80002770:	00042223          	sw	zero,4(s0)
+80002774:	fdb7f793          	andi	a5,a5,-37
+80002778:	00f41623          	sh	a5,12(s0)
+8000277c:	01042783          	lw	a5,16(s0)
+80002780:	00f42023          	sw	a5,0(s0)
+80002784:	00c45783          	lhu	a5,12(s0)
+80002788:	0087e793          	ori	a5,a5,8
+8000278c:	00f41623          	sh	a5,12(s0)
+80002790:	01042783          	lw	a5,16(s0)
+80002794:	02079063          	bnez	a5,800027b4 <__swsetup_r+0x128>
+80002798:	00c45783          	lhu	a5,12(s0)
+8000279c:	20000713          	li	a4,512
+800027a0:	2807f793          	andi	a5,a5,640
+800027a4:	00e78863          	beq	a5,a4,800027b4 <__swsetup_r+0x128>
+800027a8:	00040593          	mv	a1,s0
+800027ac:	00090513          	mv	a0,s2
+800027b0:	404000ef          	jal	ra,80002bb4 <__smakebuf_r>
+800027b4:	00c45783          	lhu	a5,12(s0)
+800027b8:	0017f713          	andi	a4,a5,1
+800027bc:	02070c63          	beqz	a4,800027f4 <__swsetup_r+0x168>
+800027c0:	01442783          	lw	a5,20(s0)
+800027c4:	00042423          	sw	zero,8(s0)
+800027c8:	40f007b3          	neg	a5,a5
+800027cc:	00f42c23          	sw	a5,24(s0)
+800027d0:	01042783          	lw	a5,16(s0)
+800027d4:	00000513          	li	a0,0
+800027d8:	f20798e3          	bnez	a5,80002708 <__swsetup_r+0x7c>
+800027dc:	00c41783          	lh	a5,12(s0)
+800027e0:	0807f713          	andi	a4,a5,128
+800027e4:	f20702e3          	beqz	a4,80002708 <__swsetup_r+0x7c>
+800027e8:	0407e793          	ori	a5,a5,64
+800027ec:	00f41623          	sh	a5,12(s0)
+800027f0:	f15ff06f          	j	80002704 <__swsetup_r+0x78>
+800027f4:	0027f793          	andi	a5,a5,2
+800027f8:	00000713          	li	a4,0
+800027fc:	00079463          	bnez	a5,80002804 <__swsetup_r+0x178>
+80002800:	01442703          	lw	a4,20(s0)
+80002804:	00e42423          	sw	a4,8(s0)
+80002808:	fc9ff06f          	j	800027d0 <__swsetup_r+0x144>
+
+8000280c <_close_r>:
+_close_r():
+8000280c:	ff010113          	addi	sp,sp,-16
+80002810:	00812423          	sw	s0,8(sp)
+80002814:	00050413          	mv	s0,a0
+80002818:	00058513          	mv	a0,a1
+8000281c:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80002820:	00112623          	sw	ra,12(sp)
+80002824:	e08fe0ef          	jal	ra,80000e2c <_close>
+80002828:	fff00793          	li	a5,-1
+8000282c:	00f51a63          	bne	a0,a5,80002840 <_close_r+0x34>
+80002830:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002834:	0007a783          	lw	a5,0(a5)
+80002838:	00078463          	beqz	a5,80002840 <_close_r+0x34>
+8000283c:	00f42023          	sw	a5,0(s0)
+80002840:	00c12083          	lw	ra,12(sp)
+80002844:	00812403          	lw	s0,8(sp)
+80002848:	01010113          	addi	sp,sp,16
+8000284c:	00008067          	ret
+
+80002850 <__sflush_r>:
+__sflush_r():
+80002850:	00c5d783          	lhu	a5,12(a1)
+80002854:	fe010113          	addi	sp,sp,-32
+80002858:	00812c23          	sw	s0,24(sp)
+8000285c:	00912a23          	sw	s1,20(sp)
+80002860:	00112e23          	sw	ra,28(sp)
+80002864:	01212823          	sw	s2,16(sp)
+80002868:	01312623          	sw	s3,12(sp)
+8000286c:	0087f713          	andi	a4,a5,8
+80002870:	00050493          	mv	s1,a0
+80002874:	00058413          	mv	s0,a1
+80002878:	14071e63          	bnez	a4,800029d4 <__sflush_r+0x184>
+8000287c:	0045a703          	lw	a4,4(a1)
+80002880:	00e04a63          	bgtz	a4,80002894 <__sflush_r+0x44>
+80002884:	0405a703          	lw	a4,64(a1)
+80002888:	00e04663          	bgtz	a4,80002894 <__sflush_r+0x44>
+8000288c:	00000513          	li	a0,0
+80002890:	11c0006f          	j	800029ac <__sflush_r+0x15c>
+80002894:	02c42703          	lw	a4,44(s0)
+80002898:	fe070ae3          	beqz	a4,8000288c <__sflush_r+0x3c>
+8000289c:	0004a903          	lw	s2,0(s1)
+800028a0:	01379693          	slli	a3,a5,0x13
+800028a4:	0004a023          	sw	zero,0(s1)
+800028a8:	0a06de63          	bgez	a3,80002964 <__sflush_r+0x114>
+800028ac:	05442503          	lw	a0,84(s0)
+800028b0:	00c45783          	lhu	a5,12(s0)
+800028b4:	0047f793          	andi	a5,a5,4
+800028b8:	00078e63          	beqz	a5,800028d4 <__sflush_r+0x84>
+800028bc:	00442783          	lw	a5,4(s0)
+800028c0:	40f50533          	sub	a0,a0,a5
+800028c4:	03442783          	lw	a5,52(s0)
+800028c8:	00078663          	beqz	a5,800028d4 <__sflush_r+0x84>
+800028cc:	04042783          	lw	a5,64(s0)
+800028d0:	40f50533          	sub	a0,a0,a5
+800028d4:	02c42783          	lw	a5,44(s0)
+800028d8:	02042583          	lw	a1,32(s0)
+800028dc:	00050613          	mv	a2,a0
+800028e0:	00000693          	li	a3,0
+800028e4:	00048513          	mv	a0,s1
+800028e8:	000780e7          	jalr	a5
+800028ec:	fff00793          	li	a5,-1
+800028f0:	00c45703          	lhu	a4,12(s0)
+800028f4:	02f51263          	bne	a0,a5,80002918 <__sflush_r+0xc8>
+800028f8:	0004a683          	lw	a3,0(s1)
+800028fc:	01d00793          	li	a5,29
+80002900:	0cd7e463          	bltu	a5,a3,800029c8 <__sflush_r+0x178>
+80002904:	204007b7          	lui	a5,0x20400
+80002908:	00178793          	addi	a5,a5,1 # 20400001 <STACK_SIZE+0x203ffc01>
+8000290c:	00d7d7b3          	srl	a5,a5,a3
+80002910:	0017f793          	andi	a5,a5,1
+80002914:	0a078a63          	beqz	a5,800029c8 <__sflush_r+0x178>
+80002918:	01042783          	lw	a5,16(s0)
+8000291c:	00042223          	sw	zero,4(s0)
+80002920:	00f42023          	sw	a5,0(s0)
+80002924:	01371793          	slli	a5,a4,0x13
+80002928:	0007dc63          	bgez	a5,80002940 <__sflush_r+0xf0>
+8000292c:	fff00793          	li	a5,-1
+80002930:	00f51663          	bne	a0,a5,8000293c <__sflush_r+0xec>
+80002934:	0004a783          	lw	a5,0(s1)
+80002938:	00079463          	bnez	a5,80002940 <__sflush_r+0xf0>
+8000293c:	04a42a23          	sw	a0,84(s0)
+80002940:	03442583          	lw	a1,52(s0)
+80002944:	0124a023          	sw	s2,0(s1)
+80002948:	f40582e3          	beqz	a1,8000288c <__sflush_r+0x3c>
+8000294c:	04440793          	addi	a5,s0,68
+80002950:	00f58663          	beq	a1,a5,8000295c <__sflush_r+0x10c>
+80002954:	00048513          	mv	a0,s1
+80002958:	378000ef          	jal	ra,80002cd0 <_free_r>
+8000295c:	02042a23          	sw	zero,52(s0)
+80002960:	f2dff06f          	j	8000288c <__sflush_r+0x3c>
+80002964:	02042583          	lw	a1,32(s0)
+80002968:	00100693          	li	a3,1
+8000296c:	00000613          	li	a2,0
+80002970:	00048513          	mv	a0,s1
+80002974:	000700e7          	jalr	a4
+80002978:	fff00793          	li	a5,-1
+8000297c:	f2f51ae3          	bne	a0,a5,800028b0 <__sflush_r+0x60>
+80002980:	0004a783          	lw	a5,0(s1)
+80002984:	f20786e3          	beqz	a5,800028b0 <__sflush_r+0x60>
+80002988:	01d00713          	li	a4,29
+8000298c:	00e78663          	beq	a5,a4,80002998 <__sflush_r+0x148>
+80002990:	01600713          	li	a4,22
+80002994:	00e79663          	bne	a5,a4,800029a0 <__sflush_r+0x150>
+80002998:	0124a023          	sw	s2,0(s1)
+8000299c:	ef1ff06f          	j	8000288c <__sflush_r+0x3c>
+800029a0:	00c45783          	lhu	a5,12(s0)
+800029a4:	0407e793          	ori	a5,a5,64
+800029a8:	00f41623          	sh	a5,12(s0)
+800029ac:	01c12083          	lw	ra,28(sp)
+800029b0:	01812403          	lw	s0,24(sp)
+800029b4:	01412483          	lw	s1,20(sp)
+800029b8:	01012903          	lw	s2,16(sp)
+800029bc:	00c12983          	lw	s3,12(sp)
+800029c0:	02010113          	addi	sp,sp,32
+800029c4:	00008067          	ret
+800029c8:	04076713          	ori	a4,a4,64
+800029cc:	00e41623          	sh	a4,12(s0)
+800029d0:	fddff06f          	j	800029ac <__sflush_r+0x15c>
+800029d4:	0105a983          	lw	s3,16(a1)
+800029d8:	ea098ae3          	beqz	s3,8000288c <__sflush_r+0x3c>
+800029dc:	0005a903          	lw	s2,0(a1)
+800029e0:	0037f793          	andi	a5,a5,3
+800029e4:	0135a023          	sw	s3,0(a1)
+800029e8:	41390933          	sub	s2,s2,s3
+800029ec:	00000713          	li	a4,0
+800029f0:	00079463          	bnez	a5,800029f8 <__sflush_r+0x1a8>
+800029f4:	0145a703          	lw	a4,20(a1)
+800029f8:	00e42423          	sw	a4,8(s0)
+800029fc:	e92058e3          	blez	s2,8000288c <__sflush_r+0x3c>
+80002a00:	02842783          	lw	a5,40(s0)
+80002a04:	02042583          	lw	a1,32(s0)
+80002a08:	00090693          	mv	a3,s2
+80002a0c:	00098613          	mv	a2,s3
+80002a10:	00048513          	mv	a0,s1
+80002a14:	000780e7          	jalr	a5
+80002a18:	00a04c63          	bgtz	a0,80002a30 <__sflush_r+0x1e0>
+80002a1c:	00c45783          	lhu	a5,12(s0)
+80002a20:	fff00513          	li	a0,-1
+80002a24:	0407e793          	ori	a5,a5,64
+80002a28:	00f41623          	sh	a5,12(s0)
+80002a2c:	f81ff06f          	j	800029ac <__sflush_r+0x15c>
+80002a30:	00a989b3          	add	s3,s3,a0
+80002a34:	40a90933          	sub	s2,s2,a0
+80002a38:	fc5ff06f          	j	800029fc <__sflush_r+0x1ac>
+
+80002a3c <_fflush_r>:
+_fflush_r():
+80002a3c:	0105a783          	lw	a5,16(a1)
+80002a40:	08078a63          	beqz	a5,80002ad4 <_fflush_r+0x98>
+80002a44:	fe010113          	addi	sp,sp,-32
+80002a48:	00812c23          	sw	s0,24(sp)
+80002a4c:	00112e23          	sw	ra,28(sp)
+80002a50:	00050413          	mv	s0,a0
+80002a54:	00050c63          	beqz	a0,80002a6c <_fflush_r+0x30>
+80002a58:	01852783          	lw	a5,24(a0)
+80002a5c:	00079863          	bnez	a5,80002a6c <_fflush_r+0x30>
+80002a60:	00b12623          	sw	a1,12(sp)
+80002a64:	be1fe0ef          	jal	ra,80001644 <__sinit>
+80002a68:	00c12583          	lw	a1,12(sp)
+80002a6c:	00000797          	auipc	a5,0x0
+80002a70:	64078793          	addi	a5,a5,1600 # 800030ac <__sf_fake_stdin>
+80002a74:	02f59263          	bne	a1,a5,80002a98 <_fflush_r+0x5c>
+80002a78:	00442583          	lw	a1,4(s0)
+80002a7c:	00c59783          	lh	a5,12(a1)
+80002a80:	04078063          	beqz	a5,80002ac0 <_fflush_r+0x84>
+80002a84:	00040513          	mv	a0,s0
+80002a88:	01812403          	lw	s0,24(sp)
+80002a8c:	01c12083          	lw	ra,28(sp)
+80002a90:	02010113          	addi	sp,sp,32
+80002a94:	dbdff06f          	j	80002850 <__sflush_r>
+80002a98:	00000797          	auipc	a5,0x0
+80002a9c:	63478793          	addi	a5,a5,1588 # 800030cc <__sf_fake_stdout>
+80002aa0:	00f59663          	bne	a1,a5,80002aac <_fflush_r+0x70>
+80002aa4:	00842583          	lw	a1,8(s0)
+80002aa8:	fd5ff06f          	j	80002a7c <_fflush_r+0x40>
+80002aac:	00000797          	auipc	a5,0x0
+80002ab0:	5e078793          	addi	a5,a5,1504 # 8000308c <__sf_fake_stderr>
+80002ab4:	fcf594e3          	bne	a1,a5,80002a7c <_fflush_r+0x40>
+80002ab8:	00c42583          	lw	a1,12(s0)
+80002abc:	fc1ff06f          	j	80002a7c <_fflush_r+0x40>
+80002ac0:	01c12083          	lw	ra,28(sp)
+80002ac4:	01812403          	lw	s0,24(sp)
+80002ac8:	00000513          	li	a0,0
+80002acc:	02010113          	addi	sp,sp,32
+80002ad0:	00008067          	ret
+80002ad4:	00000513          	li	a0,0
+80002ad8:	00008067          	ret
+
+80002adc <_lseek_r>:
+_lseek_r():
+80002adc:	ff010113          	addi	sp,sp,-16
+80002ae0:	00812423          	sw	s0,8(sp)
+80002ae4:	00050413          	mv	s0,a0
+80002ae8:	00058513          	mv	a0,a1
+80002aec:	00060593          	mv	a1,a2
+80002af0:	00068613          	mv	a2,a3
+80002af4:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80002af8:	00112623          	sw	ra,12(sp)
+80002afc:	b70fe0ef          	jal	ra,80000e6c <_lseek>
+80002b00:	fff00793          	li	a5,-1
+80002b04:	00f51a63          	bne	a0,a5,80002b18 <_lseek_r+0x3c>
+80002b08:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002b0c:	0007a783          	lw	a5,0(a5)
+80002b10:	00078463          	beqz	a5,80002b18 <_lseek_r+0x3c>
+80002b14:	00f42023          	sw	a5,0(s0)
+80002b18:	00c12083          	lw	ra,12(sp)
+80002b1c:	00812403          	lw	s0,8(sp)
+80002b20:	01010113          	addi	sp,sp,16
+80002b24:	00008067          	ret
+
+80002b28 <__swhatbuf_r>:
+__swhatbuf_r():
+80002b28:	f8010113          	addi	sp,sp,-128
+80002b2c:	06912a23          	sw	s1,116(sp)
+80002b30:	00058493          	mv	s1,a1
+80002b34:	00e59583          	lh	a1,14(a1)
+80002b38:	06812c23          	sw	s0,120(sp)
+80002b3c:	06112e23          	sw	ra,124(sp)
+80002b40:	00060413          	mv	s0,a2
+80002b44:	0005de63          	bgez	a1,80002b60 <__swhatbuf_r+0x38>
+80002b48:	00c4d783          	lhu	a5,12(s1)
+80002b4c:	0006a023          	sw	zero,0(a3)
+80002b50:	0807f793          	andi	a5,a5,128
+80002b54:	04079063          	bnez	a5,80002b94 <__swhatbuf_r+0x6c>
+80002b58:	40000793          	li	a5,1024
+80002b5c:	03c0006f          	j	80002b98 <__swhatbuf_r+0x70>
+80002b60:	01810613          	addi	a2,sp,24
+80002b64:	00d12623          	sw	a3,12(sp)
+80002b68:	2b8000ef          	jal	ra,80002e20 <_fstat_r>
+80002b6c:	00c12683          	lw	a3,12(sp)
+80002b70:	fc054ce3          	bltz	a0,80002b48 <__swhatbuf_r+0x20>
+80002b74:	01c12703          	lw	a4,28(sp)
+80002b78:	0000f7b7          	lui	a5,0xf
+80002b7c:	00e7f7b3          	and	a5,a5,a4
+80002b80:	ffffe737          	lui	a4,0xffffe
+80002b84:	00e787b3          	add	a5,a5,a4
+80002b88:	0017b793          	seqz	a5,a5
+80002b8c:	00f6a023          	sw	a5,0(a3)
+80002b90:	fc9ff06f          	j	80002b58 <__swhatbuf_r+0x30>
+80002b94:	04000793          	li	a5,64
+80002b98:	00f42023          	sw	a5,0(s0)
+80002b9c:	07c12083          	lw	ra,124(sp)
+80002ba0:	07812403          	lw	s0,120(sp)
+80002ba4:	07412483          	lw	s1,116(sp)
+80002ba8:	00000513          	li	a0,0
+80002bac:	08010113          	addi	sp,sp,128
+80002bb0:	00008067          	ret
+
+80002bb4 <__smakebuf_r>:
+__smakebuf_r():
+80002bb4:	00c5d783          	lhu	a5,12(a1)
+80002bb8:	fe010113          	addi	sp,sp,-32
+80002bbc:	00812c23          	sw	s0,24(sp)
+80002bc0:	00112e23          	sw	ra,28(sp)
+80002bc4:	00912a23          	sw	s1,20(sp)
+80002bc8:	01212823          	sw	s2,16(sp)
+80002bcc:	0027f793          	andi	a5,a5,2
+80002bd0:	00058413          	mv	s0,a1
+80002bd4:	02078863          	beqz	a5,80002c04 <__smakebuf_r+0x50>
+80002bd8:	04740793          	addi	a5,s0,71
+80002bdc:	00f42023          	sw	a5,0(s0)
+80002be0:	00f42823          	sw	a5,16(s0)
+80002be4:	00100793          	li	a5,1
+80002be8:	00f42a23          	sw	a5,20(s0)
+80002bec:	01c12083          	lw	ra,28(sp)
+80002bf0:	01812403          	lw	s0,24(sp)
+80002bf4:	01412483          	lw	s1,20(sp)
+80002bf8:	01012903          	lw	s2,16(sp)
+80002bfc:	02010113          	addi	sp,sp,32
+80002c00:	00008067          	ret
+80002c04:	00c10693          	addi	a3,sp,12
+80002c08:	00810613          	addi	a2,sp,8
+80002c0c:	00050493          	mv	s1,a0
+80002c10:	f19ff0ef          	jal	ra,80002b28 <__swhatbuf_r>
+80002c14:	00812583          	lw	a1,8(sp)
+80002c18:	00050913          	mv	s2,a0
+80002c1c:	00048513          	mv	a0,s1
+80002c20:	c7dfe0ef          	jal	ra,8000189c <_malloc_r>
+80002c24:	02051063          	bnez	a0,80002c44 <__smakebuf_r+0x90>
+80002c28:	00c41783          	lh	a5,12(s0)
+80002c2c:	2007f713          	andi	a4,a5,512
+80002c30:	fa071ee3          	bnez	a4,80002bec <__smakebuf_r+0x38>
+80002c34:	ffc7f793          	andi	a5,a5,-4
+80002c38:	0027e793          	ori	a5,a5,2
+80002c3c:	00f41623          	sh	a5,12(s0)
+80002c40:	f99ff06f          	j	80002bd8 <__smakebuf_r+0x24>
+80002c44:	fffff797          	auipc	a5,0xfffff
+80002c48:	98878793          	addi	a5,a5,-1656 # 800015cc <_cleanup_r>
+80002c4c:	02f4a423          	sw	a5,40(s1)
+80002c50:	00c45783          	lhu	a5,12(s0)
+80002c54:	00a42023          	sw	a0,0(s0)
+80002c58:	00a42823          	sw	a0,16(s0)
+80002c5c:	0807e793          	ori	a5,a5,128
+80002c60:	00f41623          	sh	a5,12(s0)
+80002c64:	00812783          	lw	a5,8(sp)
+80002c68:	00f42a23          	sw	a5,20(s0)
+80002c6c:	00c12783          	lw	a5,12(sp)
+80002c70:	02078263          	beqz	a5,80002c94 <__smakebuf_r+0xe0>
+80002c74:	00e41583          	lh	a1,14(s0)
+80002c78:	00048513          	mv	a0,s1
+80002c7c:	1ec000ef          	jal	ra,80002e68 <_isatty_r>
+80002c80:	00050a63          	beqz	a0,80002c94 <__smakebuf_r+0xe0>
+80002c84:	00c45783          	lhu	a5,12(s0)
+80002c88:	ffc7f793          	andi	a5,a5,-4
+80002c8c:	0017e793          	ori	a5,a5,1
+80002c90:	00f41623          	sh	a5,12(s0)
+80002c94:	00c45783          	lhu	a5,12(s0)
+80002c98:	00f96933          	or	s2,s2,a5
+80002c9c:	01241623          	sh	s2,12(s0)
+80002ca0:	f4dff06f          	j	80002bec <__smakebuf_r+0x38>
+
+80002ca4 <memchr>:
+memchr():
+80002ca4:	0ff5f593          	andi	a1,a1,255
+80002ca8:	00c50633          	add	a2,a0,a2
+80002cac:	00c51663          	bne	a0,a2,80002cb8 <memchr+0x14>
+80002cb0:	00000513          	li	a0,0
+80002cb4:	00008067          	ret
+80002cb8:	00054783          	lbu	a5,0(a0)
+80002cbc:	feb78ce3          	beq	a5,a1,80002cb4 <memchr+0x10>
+80002cc0:	00150513          	addi	a0,a0,1
+80002cc4:	fe9ff06f          	j	80002cac <memchr+0x8>
+
+80002cc8 <__malloc_lock>:
+__malloc_lock():
+80002cc8:	00008067          	ret
+
+80002ccc <__malloc_unlock>:
+__malloc_unlock():
+80002ccc:	00008067          	ret
+
+80002cd0 <_free_r>:
+_free_r():
+80002cd0:	10058063          	beqz	a1,80002dd0 <_free_r+0x100>
+80002cd4:	ffc5a783          	lw	a5,-4(a1)
+80002cd8:	ff010113          	addi	sp,sp,-16
+80002cdc:	00812423          	sw	s0,8(sp)
+80002ce0:	00112623          	sw	ra,12(sp)
+80002ce4:	00912223          	sw	s1,4(sp)
+80002ce8:	ffc58413          	addi	s0,a1,-4
+80002cec:	0007d463          	bgez	a5,80002cf4 <_free_r+0x24>
+80002cf0:	00f40433          	add	s0,s0,a5
+80002cf4:	00050493          	mv	s1,a0
+80002cf8:	fd1ff0ef          	jal	ra,80002cc8 <__malloc_lock>
+80002cfc:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+80002d00:	0007a783          	lw	a5,0(a5)
+80002d04:	02079263          	bnez	a5,80002d28 <_free_r+0x58>
+80002d08:	00042223          	sw	zero,4(s0)
+80002d0c:	8881a623          	sw	s0,-1908(gp) # 8000408c <__malloc_free_list>
+80002d10:	00812403          	lw	s0,8(sp)
+80002d14:	00c12083          	lw	ra,12(sp)
+80002d18:	00048513          	mv	a0,s1
+80002d1c:	00412483          	lw	s1,4(sp)
+80002d20:	01010113          	addi	sp,sp,16
+80002d24:	fa9ff06f          	j	80002ccc <__malloc_unlock>
+80002d28:	02f47663          	bgeu	s0,a5,80002d54 <_free_r+0x84>
+80002d2c:	00042683          	lw	a3,0(s0)
+80002d30:	00d40733          	add	a4,s0,a3
+80002d34:	00e79a63          	bne	a5,a4,80002d48 <_free_r+0x78>
+80002d38:	0007a703          	lw	a4,0(a5)
+80002d3c:	0047a783          	lw	a5,4(a5)
+80002d40:	00d70733          	add	a4,a4,a3
+80002d44:	00e42023          	sw	a4,0(s0)
+80002d48:	00f42223          	sw	a5,4(s0)
+80002d4c:	fc1ff06f          	j	80002d0c <_free_r+0x3c>
+80002d50:	00070793          	mv	a5,a4
+80002d54:	0047a703          	lw	a4,4(a5)
+80002d58:	00070463          	beqz	a4,80002d60 <_free_r+0x90>
+80002d5c:	fee47ae3          	bgeu	s0,a4,80002d50 <_free_r+0x80>
+80002d60:	0007a683          	lw	a3,0(a5)
+80002d64:	00d78633          	add	a2,a5,a3
+80002d68:	02861863          	bne	a2,s0,80002d98 <_free_r+0xc8>
+80002d6c:	00042603          	lw	a2,0(s0)
+80002d70:	00c686b3          	add	a3,a3,a2
+80002d74:	00d7a023          	sw	a3,0(a5)
+80002d78:	00d78633          	add	a2,a5,a3
+80002d7c:	f8c71ae3          	bne	a4,a2,80002d10 <_free_r+0x40>
+80002d80:	00072603          	lw	a2,0(a4) # ffffe000 <__global_pointer$+0x7fff9800>
+80002d84:	00472703          	lw	a4,4(a4)
+80002d88:	00d606b3          	add	a3,a2,a3
+80002d8c:	00d7a023          	sw	a3,0(a5)
+80002d90:	00e7a223          	sw	a4,4(a5)
+80002d94:	f7dff06f          	j	80002d10 <_free_r+0x40>
+80002d98:	00c47863          	bgeu	s0,a2,80002da8 <_free_r+0xd8>
+80002d9c:	00c00793          	li	a5,12
+80002da0:	00f4a023          	sw	a5,0(s1)
+80002da4:	f6dff06f          	j	80002d10 <_free_r+0x40>
+80002da8:	00042603          	lw	a2,0(s0)
+80002dac:	00c406b3          	add	a3,s0,a2
+80002db0:	00d71a63          	bne	a4,a3,80002dc4 <_free_r+0xf4>
+80002db4:	00072683          	lw	a3,0(a4)
+80002db8:	00472703          	lw	a4,4(a4)
+80002dbc:	00c686b3          	add	a3,a3,a2
+80002dc0:	00d42023          	sw	a3,0(s0)
+80002dc4:	00e42223          	sw	a4,4(s0)
+80002dc8:	0087a223          	sw	s0,4(a5)
+80002dcc:	f45ff06f          	j	80002d10 <_free_r+0x40>
+80002dd0:	00008067          	ret
+
+80002dd4 <_read_r>:
+_read_r():
+80002dd4:	ff010113          	addi	sp,sp,-16
+80002dd8:	00812423          	sw	s0,8(sp)
+80002ddc:	00050413          	mv	s0,a0
+80002de0:	00058513          	mv	a0,a1
+80002de4:	00060593          	mv	a1,a2
+80002de8:	00068613          	mv	a2,a3
+80002dec:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80002df0:	00112623          	sw	ra,12(sp)
+80002df4:	884fe0ef          	jal	ra,80000e78 <_read>
+80002df8:	fff00793          	li	a5,-1
+80002dfc:	00f51a63          	bne	a0,a5,80002e10 <_read_r+0x3c>
+80002e00:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002e04:	0007a783          	lw	a5,0(a5)
+80002e08:	00078463          	beqz	a5,80002e10 <_read_r+0x3c>
+80002e0c:	00f42023          	sw	a5,0(s0)
+80002e10:	00c12083          	lw	ra,12(sp)
+80002e14:	00812403          	lw	s0,8(sp)
+80002e18:	01010113          	addi	sp,sp,16
+80002e1c:	00008067          	ret
+
+80002e20 <_fstat_r>:
+_fstat_r():
+80002e20:	ff010113          	addi	sp,sp,-16
+80002e24:	00812423          	sw	s0,8(sp)
+80002e28:	00050413          	mv	s0,a0
+80002e2c:	00058513          	mv	a0,a1
+80002e30:	00060593          	mv	a1,a2
+80002e34:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80002e38:	00112623          	sw	ra,12(sp)
+80002e3c:	ff9fd0ef          	jal	ra,80000e34 <_fstat>
+80002e40:	fff00793          	li	a5,-1
+80002e44:	00f51a63          	bne	a0,a5,80002e58 <_fstat_r+0x38>
+80002e48:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002e4c:	0007a783          	lw	a5,0(a5)
+80002e50:	00078463          	beqz	a5,80002e58 <_fstat_r+0x38>
+80002e54:	00f42023          	sw	a5,0(s0)
+80002e58:	00c12083          	lw	ra,12(sp)
+80002e5c:	00812403          	lw	s0,8(sp)
+80002e60:	01010113          	addi	sp,sp,16
+80002e64:	00008067          	ret
+
+80002e68 <_isatty_r>:
+_isatty_r():
+80002e68:	ff010113          	addi	sp,sp,-16
+80002e6c:	00812423          	sw	s0,8(sp)
+80002e70:	00050413          	mv	s0,a0
+80002e74:	00058513          	mv	a0,a1
+80002e78:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80002e7c:	00112623          	sw	ra,12(sp)
+80002e80:	fa5fd0ef          	jal	ra,80000e24 <_isatty>
+80002e84:	fff00793          	li	a5,-1
+80002e88:	00f51a63          	bne	a0,a5,80002e9c <_isatty_r+0x34>
+80002e8c:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80002e90:	0007a783          	lw	a5,0(a5)
+80002e94:	00078463          	beqz	a5,80002e9c <_isatty_r+0x34>
+80002e98:	00f42023          	sw	a5,0(s0)
+80002e9c:	00c12083          	lw	ra,12(sp)
+80002ea0:	00812403          	lw	s0,8(sp)
+80002ea4:	01010113          	addi	sp,sp,16
+80002ea8:	00008067          	ret
+80002eac:	0000                	unimp
+	...
+
+80002eb0 <local_irq_handler_table>:
+80002eb0:	0db8 8000 0db4 8000 0dbc 8000 0de4 8000     ................
+80002ec0:	0dd8 8000 0dd8 8000 0dd8 8000 0dd8 8000     ................
+80002ed0:	0dc0 8000 0dc4 8000 0dc8 8000 0dcc 8000     ................
+80002ee0:	0dd0 8000 0dd4 8000 0ddc 8000 0de0 8000     ................
+80002ef0:	0a0d 6e49 6574 6e72 6c61 5320 7379 6574     ..Internal Syste
+80002f00:	206d 6954 656d 2072 6e49 6574 7272 7075     m Timer Interrup
+80002f10:	2074 6f43 6e75 6574 2072 203d 6425 0000     t Counter = %d..
+80002f20:	0a0d 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ..**************
+80002f30:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002f40:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002f50:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002f60:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002f70:	0a0d 2a0a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ...*************
+80002f80:	2a2a 2a2a 2a2a 202a 2020 4d20 2d69 2056     *******    Mi-V 
+80002f90:	7953 7473 6d65 5420 6d69 7265 4220 696c     System Timer Bli
+80002fa0:	6b6e 2079 7845 6d61 6c70 2065 2020 2a20     nky Example    *
+80002fb0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002fc0:	2a2a 2a2a 2a2a 0a0d 2a0a 2a2a 2a2a 2a2a     ******...*******
+80002fd0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002fe0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80002ff0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80003000:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80003010:	2a2a 2a2a 2a2a 0d2a 0d0a 4f0a 7362 7265     *******....Obser
+80003020:	6576 7420 6568 4c20 4445 2073 6c62 6e69     ve the LEDs blin
+80003030:	696b 676e 6f20 206e 6874 2065 6f62 7261     king on the boar
+80003040:	2e64 5420 6568 4c20 4445 7020 7461 6574     d. The LED patte
+80003050:	6e72 6320 6168 676e 7365 6520 6576 7972     rn changes every
+80003060:	7420 6d69 2065 2061 7973 7473 6d65 7420      time a system t
+80003070:	6d69 7265 6920 746e 7265 7572 7470 6f20     imer interrupt o
+80003080:	6363 7275 2e73 0a0d 0000 0000               ccurs.......
+
+8000308c <__sf_fake_stderr>:
+	...
+
+800030ac <__sf_fake_stdin>:
+	...
+
+800030cc <__sf_fake_stdout>:
+	...
+800030ec:	2d23 2b30 0020 0000 6c68 004c 6665 4567     #-0+ ...hlL.efgE
+800030fc:	4746 0000 3130 3332 3534 3736 3938 4241     FG..0123456789AB
+8000310c:	4443 4645 0000 0000 3130 3332 3534 3736     CDEF....01234567
+8000311c:	3938 6261 6463 6665 0000 0000 0000 0000     89abcdef........
+8000312c:	0000 0000                                   ....
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.hex
new file mode 100644
index 0000000..2ce9d61
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.hex
@@ -0,0 +1,462 @@
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.lst
new file mode 100644
index 0000000..e8507be
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32-coretimer-timer_interrupt.lst
@@ -0,0 +1,3747 @@
+
+miv-rv32-coretimer-timer_interrupt.elf:     file format elf32-littleriscv
+miv-rv32-coretimer-timer_interrupt.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00001cc0 memsz 0x00002500 flags rwx
+
+Sections:
+Idx Name              Size      VMA       LMA       File off  Algn  Flags
+  0 .entry            000009a0  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text             00001260  800009a0  800009a0  000019a0  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata            00000000  80001c00  80001c00  00002cc0  2**4  CONTENTS
+  3 .data             000000c0  80001c00  80001c00  00002c00  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .sbss             00000020  80001cc0  80001cc0  00002cc0  2**4  ALLOC
+  5 .bss              00000020  80001ce0  80001ce0  00002cc0  2**4  ALLOC
+  6 .heap             00000000  80001d00  80001d00  00002cc0  2**4  CONTENTS
+  7 .stack            00000800  80001d00  80001d00  00002cc0  2**4  ALLOC
+  8 .riscv.attributes 0000001c  00000000  00000000  00002cc0  2**0  CONTENTS, READONLY
+  9 .comment          00000051  00000000  00000000  00002cdc  2**0  CONTENTS, READONLY
+ 10 .debug_line       00004687  00000000  00000000  00002d2d  2**0  CONTENTS, READONLY, DEBUGGING
+ 11 .debug_info       00002e5a  00000000  00000000  000073b4  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_abbrev     00000cc2  00000000  00000000  0000a20e  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_aranges    00000398  00000000  00000000  0000aed0  2**3  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_str        0000c434  00000000  00000000  0000b268  2**0  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_ranges     000002e0  00000000  00000000  000176a0  2**3  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_macro      00003488  00000000  00000000  00017980  2**0  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_frame      00000ce8  00000000  00000000  0001ae08  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+800009a0 l    d  .text	00000000 .text
+80001c00 l    d  .sdata	00000000 .sdata
+80001c00 l    d  .data	00000000 .data
+80001cc0 l    d  .sbss	00000000 .sbss
+80001ce0 l    d  .bss	00000000 .bss
+80001d00 l    d  .heap	00000000 .heap
+80001d00 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_macro	00000000 .debug_macro
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+800009a0 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+80000120 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+800001a8 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+80000230 l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800002b8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000340 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+80000890 l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+800006f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+800003c8 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+80000450 l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800004d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000560 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+800005e8 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+80000670 l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+80000780 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000808 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000918 l       .entry	00000000 generic_restore
+800009f0 l       .text	00000000 ima_cores_setup
+80000a38 l       .text	00000000 vector_address_not_matching
+800009fc l       .text	00000000 generic_reset_handling
+80000ab8 l       .text	00000000 block_copy
+80000a3c l       .text	00000000 initializations
+80000a98 l       .text	00000000 zeroize_block
+80000ae0 l       .text	00000000 block_copy_error
+80000aa8 l       .text	00000000 zeroize_loop
+80000ac8 l       .text	00000000 block_copy_loop
+80000ae4 l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000ae8 l     F .text	00000030 MRV_clear_soft_irq
+80001cc0 l     O .sbss	00000008 g_systick_increment
+80001cc8 l     O .sbss	00000008 g_systick_cmp_value
+80001cd0 l     O .sbss	00000004 d_tick.2196
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+00000000 l    df *ABS*	00000000 hal_irq.c
+80001068 l     F .text	00000024 MRV_enable_interrupts
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_timer.c
+80001cd4 l     O .sbss	00000004 NULL_timer_instance
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80001ab0 l     F .text	0000002c MRV_enable_local_irq
+80001cd8 l     O .sbss	00000004 gpio_pins_state
+80001ce0 g     O .bss	00000008 g_gpio
+00000800 g       *ABS*	00000000 STACK_SIZE
+80002400 g       .sdata	00000000 __global_pointer$
+80001c00 g       *ABS*	00000000 __data_load
+80000ed0  w    F .text	0000001c SysTick_Handler
+8000117c g       .text	00000000 HW_get_8bit_reg_field
+80001cc0 g       .sbss	00000000 __sbss_start
+80000c90 g     F .text	00000088 handle_local_ei_interrupts
+800010b4 g       .text	00000000 HW_set_32bit_reg
+80001c00 g       .sdata	00000000 __sdata_start
+80000fb0  w    F .text	0000001c MSYS_EI4_IRQHandler
+80001154 g       .text	00000000 HW_set_8bit_reg_field
+80000f40  w    F .text	0000001c SUBSYS_IRQHandler
+80000d18 g     F .text	0000015c handle_trap
+00008000 g       *ABS*	00000000 RAM_SIZE
+80001ce8 g     O .bss	00000004 g_core_timer_0
+80001000  w    F .text	0000001c MSYS_EI6_IRQHandler
+800015b0 g     F .text	0000005c TMR_enable_int
+80001038  w    F .text	0000001c SUBSYSR_IRQHandler
+80000f08  w    F .text	0000001c MGECI_IRQHandler
+80001d00 g       .heap	00000000 _heap_end
+80001bc0 g     O .text	00000040 local_irq_handler_table
+8000101c  w    F .text	0000001c MSYS_EI7_IRQHandler
+80001d00 g       .bss	00000000 __bss_end
+80000e74 g     F .text	00000028 _init
+80001144 g       .text	00000000 HW_set_8bit_reg
+8000114c g       .text	00000000 HW_get_8bit_reg
+80000f5c  w    F .text	0000001c MSYS_EI1_IRQHandler
+80001ce0 g       .sbss	00000000 __sbss_end
+800010c4 g       .text	00000000 HW_set_32bit_reg_field
+80002500 g       .stack	00000000 __stack_top
+8000142c g     F .text	00000128 TMR_init
+80001cec g     O .bss	00000008 g_core_uart_0
+80001364 g     F .text	000000c8 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001c00 g     O .data	000000c0 g_message
+800017d4 g     F .text	00000164 GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+80000b18 g     F .text	0000014c handle_m_timer_interrupt
+80001c00 g       *ABS*	00000000 __sdata_load
+80001cc0 g       .data	00000000 __data_end
+800010ec g       .text	00000000 HW_get_32bit_reg_field
+80001660 g     F .text	00000174 GPIO_init
+80000000 g       *ABS*	00000000 RAM_START_ADDRESS
+80001938 g     F .text	00000178 GPIO_get_outputs
+80001ce0 g       .bss	00000000 __bss_start
+8000108c g     F .text	00000028 HAL_enable_interrupts
+80001b34 g     F .text	0000008c main
+80000fcc  w    F .text	0000001c MSYS_EI5_IRQHandler
+80000f24  w    F .text	0000001c MGEUI_IRQHandler
+80001104 g       .text	00000000 HW_get_16bit_reg
+80001c00 g       .sdata	00000000 __sdata_end
+80001d00 g       .heap	00000000 __heap_end
+80000e9c g     F .text	0000001c _fini
+8000110c g       .text	00000000 HW_set_16bit_reg_field
+80000f78  w    F .text	0000001c MSYS_EI2_IRQHandler
+80001d00 g       .stack	00000000 __stack_bottom
+80000eb8  w    F .text	00000018 Software_IRQHandler
+80001554 g     F .text	0000005c TMR_start
+80001d00 g       .heap	00000000 __heap_start
+80001d00 g       .bss	00000000 _end
+80000fe8  w    F .text	00000018 Reserved_IRQHandler
+8000118c g     F .text	000001d8 UART_init
+800010bc g       .text	00000000 HW_get_32bit_reg
+80001054 g     F .text	00000014 _exit
+800010fc g       .text	00000000 HW_set_16bit_reg
+80000f94  w    F .text	0000001c MSYS_EI3_IRQHandler
+80000eec  w    F .text	0000001c External_IRQHandler
+80001c00 g       .data	00000000 __data_start
+80000c64 g     F .text	0000002c handle_m_soft_interrupt
+80001134 g       .text	00000000 HW_get_16bit_reg_field
+80001adc g     F .text	00000058 MSYS_EI0_IRQHandler
+8000160c g     F .text	00000054 TMR_clear_int
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:113
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	1a10006f          	j	800009a0 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:124
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:130
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	1100006f          	j	80000120 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:139
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	1880006f          	j	800001a8 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:148
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	2000006f          	j	80000230 <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:159
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	2740006f          	j	800002b8 <vector_MGEUI_trap_handler>
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:165
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	2f80006f          	j	80000340 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:177
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	0350006f          	j	80000890 <vector_SUBSYSR_IRQHandler>
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:184
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	6980006f          	j	800006f8 <vector_SUBSYS_IRQHandler>
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:191
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	3640006f          	j	800003c8 <vector_MSYS_EI0_trap_handler>
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:197
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	3e80006f          	j	80000450 <vector_MSYS_EI1_trap_handler>
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:203
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	46c0006f          	j	800004d8 <vector_MSYS_EI2_trap_handler>
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:209
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	4f00006f          	j	80000560 <vector_MSYS_EI3_trap_handler>
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:215
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	5740006f          	j	800005e8 <vector_MSYS_EI4_trap_handler>
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:221
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	5f80006f          	j	80000670 <vector_MSYS_EI5_trap_handler>
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:228
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	7040006f          	j	80000780 <vector_MSYS_EI6_trap_handler>
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:238
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	7880006f          	j	80000808 <vector_MSYS_EI7_trap_handler>
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:247
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	f8010113          	addi	sp,sp,-128
+80000094:	00112023          	sw	ra,0(sp)
+80000098:	00212223          	sw	sp,4(sp)
+8000009c:	00312423          	sw	gp,8(sp)
+800000a0:	00412623          	sw	tp,12(sp)
+800000a4:	00512823          	sw	t0,16(sp)
+800000a8:	00612a23          	sw	t1,20(sp)
+800000ac:	00712c23          	sw	t2,24(sp)
+800000b0:	00812e23          	sw	s0,28(sp)
+800000b4:	02912023          	sw	s1,32(sp)
+800000b8:	02a12223          	sw	a0,36(sp)
+800000bc:	02b12423          	sw	a1,40(sp)
+800000c0:	02c12623          	sw	a2,44(sp)
+800000c4:	02d12823          	sw	a3,48(sp)
+800000c8:	02e12a23          	sw	a4,52(sp)
+800000cc:	02f12c23          	sw	a5,56(sp)
+800000d0:	03012e23          	sw	a6,60(sp)
+800000d4:	05112023          	sw	a7,64(sp)
+800000d8:	05212223          	sw	s2,68(sp)
+800000dc:	05312423          	sw	s3,72(sp)
+800000e0:	05412623          	sw	s4,76(sp)
+800000e4:	05512823          	sw	s5,80(sp)
+800000e8:	05612a23          	sw	s6,84(sp)
+800000ec:	05712c23          	sw	s7,88(sp)
+800000f0:	05812e23          	sw	s8,92(sp)
+800000f4:	07912023          	sw	s9,96(sp)
+800000f8:	07a12223          	sw	s10,100(sp)
+800000fc:	07b12423          	sw	s11,104(sp)
+80000100:	07c12623          	sw	t3,108(sp)
+80000104:	07d12823          	sw	t4,112(sp)
+80000108:	07e12a23          	sw	t5,116(sp)
+8000010c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+  csrr a0, mcause
+80000110:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a1, mepc
+80000114:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  jal handle_trap
+80000118:	401000ef          	jal	ra,80000d18 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  j generic_restore
+8000011c:	7fc0006f          	j	80000918 <generic_restore>
+
+80000120 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:254
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+80000120:	f8010113          	addi	sp,sp,-128
+80000124:	00112023          	sw	ra,0(sp)
+80000128:	00212223          	sw	sp,4(sp)
+8000012c:	00312423          	sw	gp,8(sp)
+80000130:	00412623          	sw	tp,12(sp)
+80000134:	00512823          	sw	t0,16(sp)
+80000138:	00612a23          	sw	t1,20(sp)
+8000013c:	00712c23          	sw	t2,24(sp)
+80000140:	00812e23          	sw	s0,28(sp)
+80000144:	02912023          	sw	s1,32(sp)
+80000148:	02a12223          	sw	a0,36(sp)
+8000014c:	02b12423          	sw	a1,40(sp)
+80000150:	02c12623          	sw	a2,44(sp)
+80000154:	02d12823          	sw	a3,48(sp)
+80000158:	02e12a23          	sw	a4,52(sp)
+8000015c:	02f12c23          	sw	a5,56(sp)
+80000160:	03012e23          	sw	a6,60(sp)
+80000164:	05112023          	sw	a7,64(sp)
+80000168:	05212223          	sw	s2,68(sp)
+8000016c:	05312423          	sw	s3,72(sp)
+80000170:	05412623          	sw	s4,76(sp)
+80000174:	05512823          	sw	s5,80(sp)
+80000178:	05612a23          	sw	s6,84(sp)
+8000017c:	05712c23          	sw	s7,88(sp)
+80000180:	05812e23          	sw	s8,92(sp)
+80000184:	07912023          	sw	s9,96(sp)
+80000188:	07a12223          	sw	s10,100(sp)
+8000018c:	07b12423          	sw	s11,104(sp)
+80000190:	07c12623          	sw	t3,108(sp)
+80000194:	07d12823          	sw	t4,112(sp)
+80000198:	07e12a23          	sw	t5,116(sp)
+8000019c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+  jal handle_m_soft_interrupt
+800001a0:	2c5000ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  j generic_restore
+800001a4:	7740006f          	j	80000918 <generic_restore>
+
+800001a8 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:259
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+800001a8:	f8010113          	addi	sp,sp,-128
+800001ac:	00112023          	sw	ra,0(sp)
+800001b0:	00212223          	sw	sp,4(sp)
+800001b4:	00312423          	sw	gp,8(sp)
+800001b8:	00412623          	sw	tp,12(sp)
+800001bc:	00512823          	sw	t0,16(sp)
+800001c0:	00612a23          	sw	t1,20(sp)
+800001c4:	00712c23          	sw	t2,24(sp)
+800001c8:	00812e23          	sw	s0,28(sp)
+800001cc:	02912023          	sw	s1,32(sp)
+800001d0:	02a12223          	sw	a0,36(sp)
+800001d4:	02b12423          	sw	a1,40(sp)
+800001d8:	02c12623          	sw	a2,44(sp)
+800001dc:	02d12823          	sw	a3,48(sp)
+800001e0:	02e12a23          	sw	a4,52(sp)
+800001e4:	02f12c23          	sw	a5,56(sp)
+800001e8:	03012e23          	sw	a6,60(sp)
+800001ec:	05112023          	sw	a7,64(sp)
+800001f0:	05212223          	sw	s2,68(sp)
+800001f4:	05312423          	sw	s3,72(sp)
+800001f8:	05412623          	sw	s4,76(sp)
+800001fc:	05512823          	sw	s5,80(sp)
+80000200:	05612a23          	sw	s6,84(sp)
+80000204:	05712c23          	sw	s7,88(sp)
+80000208:	05812e23          	sw	s8,92(sp)
+8000020c:	07912023          	sw	s9,96(sp)
+80000210:	07a12223          	sw	s10,100(sp)
+80000214:	07b12423          	sw	s11,104(sp)
+80000218:	07c12623          	sw	t3,108(sp)
+8000021c:	07d12823          	sw	t4,112(sp)
+80000220:	07e12a23          	sw	t5,116(sp)
+80000224:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+  jal handle_m_timer_interrupt
+80000228:	0f1000ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  j generic_restore
+8000022c:	6ec0006f          	j	80000918 <generic_restore>
+
+80000230 <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:264
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+80000230:	f8010113          	addi	sp,sp,-128
+80000234:	00112023          	sw	ra,0(sp)
+80000238:	00212223          	sw	sp,4(sp)
+8000023c:	00312423          	sw	gp,8(sp)
+80000240:	00412623          	sw	tp,12(sp)
+80000244:	00512823          	sw	t0,16(sp)
+80000248:	00612a23          	sw	t1,20(sp)
+8000024c:	00712c23          	sw	t2,24(sp)
+80000250:	00812e23          	sw	s0,28(sp)
+80000254:	02912023          	sw	s1,32(sp)
+80000258:	02a12223          	sw	a0,36(sp)
+8000025c:	02b12423          	sw	a1,40(sp)
+80000260:	02c12623          	sw	a2,44(sp)
+80000264:	02d12823          	sw	a3,48(sp)
+80000268:	02e12a23          	sw	a4,52(sp)
+8000026c:	02f12c23          	sw	a5,56(sp)
+80000270:	03012e23          	sw	a6,60(sp)
+80000274:	05112023          	sw	a7,64(sp)
+80000278:	05212223          	sw	s2,68(sp)
+8000027c:	05312423          	sw	s3,72(sp)
+80000280:	05412623          	sw	s4,76(sp)
+80000284:	05512823          	sw	s5,80(sp)
+80000288:	05612a23          	sw	s6,84(sp)
+8000028c:	05712c23          	sw	s7,88(sp)
+80000290:	05812e23          	sw	s8,92(sp)
+80000294:	07912023          	sw	s9,96(sp)
+80000298:	07a12223          	sw	s10,100(sp)
+8000029c:	07b12423          	sw	s11,104(sp)
+800002a0:	07c12623          	sw	t3,108(sp)
+800002a4:	07d12823          	sw	t4,112(sp)
+800002a8:	07e12a23          	sw	t5,116(sp)
+800002ac:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:268
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800002b0:	43d000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:270
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800002b4:	6640006f          	j	80000918 <generic_restore>
+
+800002b8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:274
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800002b8:	f8010113          	addi	sp,sp,-128
+800002bc:	00112023          	sw	ra,0(sp)
+800002c0:	00212223          	sw	sp,4(sp)
+800002c4:	00312423          	sw	gp,8(sp)
+800002c8:	00412623          	sw	tp,12(sp)
+800002cc:	00512823          	sw	t0,16(sp)
+800002d0:	00612a23          	sw	t1,20(sp)
+800002d4:	00712c23          	sw	t2,24(sp)
+800002d8:	00812e23          	sw	s0,28(sp)
+800002dc:	02912023          	sw	s1,32(sp)
+800002e0:	02a12223          	sw	a0,36(sp)
+800002e4:	02b12423          	sw	a1,40(sp)
+800002e8:	02c12623          	sw	a2,44(sp)
+800002ec:	02d12823          	sw	a3,48(sp)
+800002f0:	02e12a23          	sw	a4,52(sp)
+800002f4:	02f12c23          	sw	a5,56(sp)
+800002f8:	03012e23          	sw	a6,60(sp)
+800002fc:	05112023          	sw	a7,64(sp)
+80000300:	05212223          	sw	s2,68(sp)
+80000304:	05312423          	sw	s3,72(sp)
+80000308:	05412623          	sw	s4,76(sp)
+8000030c:	05512823          	sw	s5,80(sp)
+80000310:	05612a23          	sw	s6,84(sp)
+80000314:	05712c23          	sw	s7,88(sp)
+80000318:	05812e23          	sw	s8,92(sp)
+8000031c:	07912023          	sw	s9,96(sp)
+80000320:	07a12223          	sw	s10,100(sp)
+80000324:	07b12423          	sw	s11,104(sp)
+80000328:	07c12623          	sw	t3,108(sp)
+8000032c:	07d12823          	sw	t4,112(sp)
+80000330:	07e12a23          	sw	t5,116(sp)
+80000334:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+  jal MGEUI_IRQHandler
+80000338:	3ed000ef          	jal	ra,80000f24 <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  j generic_restore
+8000033c:	5dc0006f          	j	80000918 <generic_restore>
+
+80000340 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:279
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000340:	f8010113          	addi	sp,sp,-128
+80000344:	00112023          	sw	ra,0(sp)
+80000348:	00212223          	sw	sp,4(sp)
+8000034c:	00312423          	sw	gp,8(sp)
+80000350:	00412623          	sw	tp,12(sp)
+80000354:	00512823          	sw	t0,16(sp)
+80000358:	00612a23          	sw	t1,20(sp)
+8000035c:	00712c23          	sw	t2,24(sp)
+80000360:	00812e23          	sw	s0,28(sp)
+80000364:	02912023          	sw	s1,32(sp)
+80000368:	02a12223          	sw	a0,36(sp)
+8000036c:	02b12423          	sw	a1,40(sp)
+80000370:	02c12623          	sw	a2,44(sp)
+80000374:	02d12823          	sw	a3,48(sp)
+80000378:	02e12a23          	sw	a4,52(sp)
+8000037c:	02f12c23          	sw	a5,56(sp)
+80000380:	03012e23          	sw	a6,60(sp)
+80000384:	05112023          	sw	a7,64(sp)
+80000388:	05212223          	sw	s2,68(sp)
+8000038c:	05312423          	sw	s3,72(sp)
+80000390:	05412623          	sw	s4,76(sp)
+80000394:	05512823          	sw	s5,80(sp)
+80000398:	05612a23          	sw	s6,84(sp)
+8000039c:	05712c23          	sw	s7,88(sp)
+800003a0:	05812e23          	sw	s8,92(sp)
+800003a4:	07912023          	sw	s9,96(sp)
+800003a8:	07a12223          	sw	s10,100(sp)
+800003ac:	07b12423          	sw	s11,104(sp)
+800003b0:	07c12623          	sw	t3,108(sp)
+800003b4:	07d12823          	sw	t4,112(sp)
+800003b8:	07e12a23          	sw	t5,116(sp)
+800003bc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+  jal MGECI_IRQHandler
+800003c0:	349000ef          	jal	ra,80000f08 <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  j generic_restore
+800003c4:	5540006f          	j	80000918 <generic_restore>
+
+800003c8 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:284
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+800003c8:	f8010113          	addi	sp,sp,-128
+800003cc:	00112023          	sw	ra,0(sp)
+800003d0:	00212223          	sw	sp,4(sp)
+800003d4:	00312423          	sw	gp,8(sp)
+800003d8:	00412623          	sw	tp,12(sp)
+800003dc:	00512823          	sw	t0,16(sp)
+800003e0:	00612a23          	sw	t1,20(sp)
+800003e4:	00712c23          	sw	t2,24(sp)
+800003e8:	00812e23          	sw	s0,28(sp)
+800003ec:	02912023          	sw	s1,32(sp)
+800003f0:	02a12223          	sw	a0,36(sp)
+800003f4:	02b12423          	sw	a1,40(sp)
+800003f8:	02c12623          	sw	a2,44(sp)
+800003fc:	02d12823          	sw	a3,48(sp)
+80000400:	02e12a23          	sw	a4,52(sp)
+80000404:	02f12c23          	sw	a5,56(sp)
+80000408:	03012e23          	sw	a6,60(sp)
+8000040c:	05112023          	sw	a7,64(sp)
+80000410:	05212223          	sw	s2,68(sp)
+80000414:	05312423          	sw	s3,72(sp)
+80000418:	05412623          	sw	s4,76(sp)
+8000041c:	05512823          	sw	s5,80(sp)
+80000420:	05612a23          	sw	s6,84(sp)
+80000424:	05712c23          	sw	s7,88(sp)
+80000428:	05812e23          	sw	s8,92(sp)
+8000042c:	07912023          	sw	s9,96(sp)
+80000430:	07a12223          	sw	s10,100(sp)
+80000434:	07b12423          	sw	s11,104(sp)
+80000438:	07c12623          	sw	t3,108(sp)
+8000043c:	07d12823          	sw	t4,112(sp)
+80000440:	07e12a23          	sw	t5,116(sp)
+80000444:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+  jal MSYS_EI0_IRQHandler
+80000448:	694010ef          	jal	ra,80001adc <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  j generic_restore
+8000044c:	4cc0006f          	j	80000918 <generic_restore>
+
+80000450 <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:289
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+80000450:	f8010113          	addi	sp,sp,-128
+80000454:	00112023          	sw	ra,0(sp)
+80000458:	00212223          	sw	sp,4(sp)
+8000045c:	00312423          	sw	gp,8(sp)
+80000460:	00412623          	sw	tp,12(sp)
+80000464:	00512823          	sw	t0,16(sp)
+80000468:	00612a23          	sw	t1,20(sp)
+8000046c:	00712c23          	sw	t2,24(sp)
+80000470:	00812e23          	sw	s0,28(sp)
+80000474:	02912023          	sw	s1,32(sp)
+80000478:	02a12223          	sw	a0,36(sp)
+8000047c:	02b12423          	sw	a1,40(sp)
+80000480:	02c12623          	sw	a2,44(sp)
+80000484:	02d12823          	sw	a3,48(sp)
+80000488:	02e12a23          	sw	a4,52(sp)
+8000048c:	02f12c23          	sw	a5,56(sp)
+80000490:	03012e23          	sw	a6,60(sp)
+80000494:	05112023          	sw	a7,64(sp)
+80000498:	05212223          	sw	s2,68(sp)
+8000049c:	05312423          	sw	s3,72(sp)
+800004a0:	05412623          	sw	s4,76(sp)
+800004a4:	05512823          	sw	s5,80(sp)
+800004a8:	05612a23          	sw	s6,84(sp)
+800004ac:	05712c23          	sw	s7,88(sp)
+800004b0:	05812e23          	sw	s8,92(sp)
+800004b4:	07912023          	sw	s9,96(sp)
+800004b8:	07a12223          	sw	s10,100(sp)
+800004bc:	07b12423          	sw	s11,104(sp)
+800004c0:	07c12623          	sw	t3,108(sp)
+800004c4:	07d12823          	sw	t4,112(sp)
+800004c8:	07e12a23          	sw	t5,116(sp)
+800004cc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+  jal MSYS_EI1_IRQHandler
+800004d0:	28d000ef          	jal	ra,80000f5c <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  j generic_restore
+800004d4:	4440006f          	j	80000918 <generic_restore>
+
+800004d8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:294
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800004d8:	f8010113          	addi	sp,sp,-128
+800004dc:	00112023          	sw	ra,0(sp)
+800004e0:	00212223          	sw	sp,4(sp)
+800004e4:	00312423          	sw	gp,8(sp)
+800004e8:	00412623          	sw	tp,12(sp)
+800004ec:	00512823          	sw	t0,16(sp)
+800004f0:	00612a23          	sw	t1,20(sp)
+800004f4:	00712c23          	sw	t2,24(sp)
+800004f8:	00812e23          	sw	s0,28(sp)
+800004fc:	02912023          	sw	s1,32(sp)
+80000500:	02a12223          	sw	a0,36(sp)
+80000504:	02b12423          	sw	a1,40(sp)
+80000508:	02c12623          	sw	a2,44(sp)
+8000050c:	02d12823          	sw	a3,48(sp)
+80000510:	02e12a23          	sw	a4,52(sp)
+80000514:	02f12c23          	sw	a5,56(sp)
+80000518:	03012e23          	sw	a6,60(sp)
+8000051c:	05112023          	sw	a7,64(sp)
+80000520:	05212223          	sw	s2,68(sp)
+80000524:	05312423          	sw	s3,72(sp)
+80000528:	05412623          	sw	s4,76(sp)
+8000052c:	05512823          	sw	s5,80(sp)
+80000530:	05612a23          	sw	s6,84(sp)
+80000534:	05712c23          	sw	s7,88(sp)
+80000538:	05812e23          	sw	s8,92(sp)
+8000053c:	07912023          	sw	s9,96(sp)
+80000540:	07a12223          	sw	s10,100(sp)
+80000544:	07b12423          	sw	s11,104(sp)
+80000548:	07c12623          	sw	t3,108(sp)
+8000054c:	07d12823          	sw	t4,112(sp)
+80000550:	07e12a23          	sw	t5,116(sp)
+80000554:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+  jal MSYS_EI2_IRQHandler
+80000558:	221000ef          	jal	ra,80000f78 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  j generic_restore
+8000055c:	3bc0006f          	j	80000918 <generic_restore>
+
+80000560 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:299
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000560:	f8010113          	addi	sp,sp,-128
+80000564:	00112023          	sw	ra,0(sp)
+80000568:	00212223          	sw	sp,4(sp)
+8000056c:	00312423          	sw	gp,8(sp)
+80000570:	00412623          	sw	tp,12(sp)
+80000574:	00512823          	sw	t0,16(sp)
+80000578:	00612a23          	sw	t1,20(sp)
+8000057c:	00712c23          	sw	t2,24(sp)
+80000580:	00812e23          	sw	s0,28(sp)
+80000584:	02912023          	sw	s1,32(sp)
+80000588:	02a12223          	sw	a0,36(sp)
+8000058c:	02b12423          	sw	a1,40(sp)
+80000590:	02c12623          	sw	a2,44(sp)
+80000594:	02d12823          	sw	a3,48(sp)
+80000598:	02e12a23          	sw	a4,52(sp)
+8000059c:	02f12c23          	sw	a5,56(sp)
+800005a0:	03012e23          	sw	a6,60(sp)
+800005a4:	05112023          	sw	a7,64(sp)
+800005a8:	05212223          	sw	s2,68(sp)
+800005ac:	05312423          	sw	s3,72(sp)
+800005b0:	05412623          	sw	s4,76(sp)
+800005b4:	05512823          	sw	s5,80(sp)
+800005b8:	05612a23          	sw	s6,84(sp)
+800005bc:	05712c23          	sw	s7,88(sp)
+800005c0:	05812e23          	sw	s8,92(sp)
+800005c4:	07912023          	sw	s9,96(sp)
+800005c8:	07a12223          	sw	s10,100(sp)
+800005cc:	07b12423          	sw	s11,104(sp)
+800005d0:	07c12623          	sw	t3,108(sp)
+800005d4:	07d12823          	sw	t4,112(sp)
+800005d8:	07e12a23          	sw	t5,116(sp)
+800005dc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+  jal MSYS_EI3_IRQHandler
+800005e0:	1b5000ef          	jal	ra,80000f94 <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  j generic_restore
+800005e4:	3340006f          	j	80000918 <generic_restore>
+
+800005e8 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:304
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+800005e8:	f8010113          	addi	sp,sp,-128
+800005ec:	00112023          	sw	ra,0(sp)
+800005f0:	00212223          	sw	sp,4(sp)
+800005f4:	00312423          	sw	gp,8(sp)
+800005f8:	00412623          	sw	tp,12(sp)
+800005fc:	00512823          	sw	t0,16(sp)
+80000600:	00612a23          	sw	t1,20(sp)
+80000604:	00712c23          	sw	t2,24(sp)
+80000608:	00812e23          	sw	s0,28(sp)
+8000060c:	02912023          	sw	s1,32(sp)
+80000610:	02a12223          	sw	a0,36(sp)
+80000614:	02b12423          	sw	a1,40(sp)
+80000618:	02c12623          	sw	a2,44(sp)
+8000061c:	02d12823          	sw	a3,48(sp)
+80000620:	02e12a23          	sw	a4,52(sp)
+80000624:	02f12c23          	sw	a5,56(sp)
+80000628:	03012e23          	sw	a6,60(sp)
+8000062c:	05112023          	sw	a7,64(sp)
+80000630:	05212223          	sw	s2,68(sp)
+80000634:	05312423          	sw	s3,72(sp)
+80000638:	05412623          	sw	s4,76(sp)
+8000063c:	05512823          	sw	s5,80(sp)
+80000640:	05612a23          	sw	s6,84(sp)
+80000644:	05712c23          	sw	s7,88(sp)
+80000648:	05812e23          	sw	s8,92(sp)
+8000064c:	07912023          	sw	s9,96(sp)
+80000650:	07a12223          	sw	s10,100(sp)
+80000654:	07b12423          	sw	s11,104(sp)
+80000658:	07c12623          	sw	t3,108(sp)
+8000065c:	07d12823          	sw	t4,112(sp)
+80000660:	07e12a23          	sw	t5,116(sp)
+80000664:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+  jal MSYS_EI4_IRQHandler
+80000668:	149000ef          	jal	ra,80000fb0 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  j generic_restore
+8000066c:	2ac0006f          	j	80000918 <generic_restore>
+
+80000670 <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:309
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+80000670:	f8010113          	addi	sp,sp,-128
+80000674:	00112023          	sw	ra,0(sp)
+80000678:	00212223          	sw	sp,4(sp)
+8000067c:	00312423          	sw	gp,8(sp)
+80000680:	00412623          	sw	tp,12(sp)
+80000684:	00512823          	sw	t0,16(sp)
+80000688:	00612a23          	sw	t1,20(sp)
+8000068c:	00712c23          	sw	t2,24(sp)
+80000690:	00812e23          	sw	s0,28(sp)
+80000694:	02912023          	sw	s1,32(sp)
+80000698:	02a12223          	sw	a0,36(sp)
+8000069c:	02b12423          	sw	a1,40(sp)
+800006a0:	02c12623          	sw	a2,44(sp)
+800006a4:	02d12823          	sw	a3,48(sp)
+800006a8:	02e12a23          	sw	a4,52(sp)
+800006ac:	02f12c23          	sw	a5,56(sp)
+800006b0:	03012e23          	sw	a6,60(sp)
+800006b4:	05112023          	sw	a7,64(sp)
+800006b8:	05212223          	sw	s2,68(sp)
+800006bc:	05312423          	sw	s3,72(sp)
+800006c0:	05412623          	sw	s4,76(sp)
+800006c4:	05512823          	sw	s5,80(sp)
+800006c8:	05612a23          	sw	s6,84(sp)
+800006cc:	05712c23          	sw	s7,88(sp)
+800006d0:	05812e23          	sw	s8,92(sp)
+800006d4:	07912023          	sw	s9,96(sp)
+800006d8:	07a12223          	sw	s10,100(sp)
+800006dc:	07b12423          	sw	s11,104(sp)
+800006e0:	07c12623          	sw	t3,108(sp)
+800006e4:	07d12823          	sw	t4,112(sp)
+800006e8:	07e12a23          	sw	t5,116(sp)
+800006ec:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+  jal MSYS_EI5_IRQHandler
+800006f0:	0dd000ef          	jal	ra,80000fcc <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  j generic_restore
+800006f4:	2240006f          	j	80000918 <generic_restore>
+
+800006f8 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:314
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+800006f8:	f8010113          	addi	sp,sp,-128
+800006fc:	00112023          	sw	ra,0(sp)
+80000700:	00212223          	sw	sp,4(sp)
+80000704:	00312423          	sw	gp,8(sp)
+80000708:	00412623          	sw	tp,12(sp)
+8000070c:	00512823          	sw	t0,16(sp)
+80000710:	00612a23          	sw	t1,20(sp)
+80000714:	00712c23          	sw	t2,24(sp)
+80000718:	00812e23          	sw	s0,28(sp)
+8000071c:	02912023          	sw	s1,32(sp)
+80000720:	02a12223          	sw	a0,36(sp)
+80000724:	02b12423          	sw	a1,40(sp)
+80000728:	02c12623          	sw	a2,44(sp)
+8000072c:	02d12823          	sw	a3,48(sp)
+80000730:	02e12a23          	sw	a4,52(sp)
+80000734:	02f12c23          	sw	a5,56(sp)
+80000738:	03012e23          	sw	a6,60(sp)
+8000073c:	05112023          	sw	a7,64(sp)
+80000740:	05212223          	sw	s2,68(sp)
+80000744:	05312423          	sw	s3,72(sp)
+80000748:	05412623          	sw	s4,76(sp)
+8000074c:	05512823          	sw	s5,80(sp)
+80000750:	05612a23          	sw	s6,84(sp)
+80000754:	05712c23          	sw	s7,88(sp)
+80000758:	05812e23          	sw	s8,92(sp)
+8000075c:	07912023          	sw	s9,96(sp)
+80000760:	07a12223          	sw	s10,100(sp)
+80000764:	07b12423          	sw	s11,104(sp)
+80000768:	07c12623          	sw	t3,108(sp)
+8000076c:	07d12823          	sw	t4,112(sp)
+80000770:	07e12a23          	sw	t5,116(sp)
+80000774:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+  jal SUBSYS_IRQHandler
+80000778:	7c8000ef          	jal	ra,80000f40 <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  j generic_restore
+8000077c:	19c0006f          	j	80000918 <generic_restore>
+
+80000780 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:320
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+80000780:	f8010113          	addi	sp,sp,-128
+80000784:	00112023          	sw	ra,0(sp)
+80000788:	00212223          	sw	sp,4(sp)
+8000078c:	00312423          	sw	gp,8(sp)
+80000790:	00412623          	sw	tp,12(sp)
+80000794:	00512823          	sw	t0,16(sp)
+80000798:	00612a23          	sw	t1,20(sp)
+8000079c:	00712c23          	sw	t2,24(sp)
+800007a0:	00812e23          	sw	s0,28(sp)
+800007a4:	02912023          	sw	s1,32(sp)
+800007a8:	02a12223          	sw	a0,36(sp)
+800007ac:	02b12423          	sw	a1,40(sp)
+800007b0:	02c12623          	sw	a2,44(sp)
+800007b4:	02d12823          	sw	a3,48(sp)
+800007b8:	02e12a23          	sw	a4,52(sp)
+800007bc:	02f12c23          	sw	a5,56(sp)
+800007c0:	03012e23          	sw	a6,60(sp)
+800007c4:	05112023          	sw	a7,64(sp)
+800007c8:	05212223          	sw	s2,68(sp)
+800007cc:	05312423          	sw	s3,72(sp)
+800007d0:	05412623          	sw	s4,76(sp)
+800007d4:	05512823          	sw	s5,80(sp)
+800007d8:	05612a23          	sw	s6,84(sp)
+800007dc:	05712c23          	sw	s7,88(sp)
+800007e0:	05812e23          	sw	s8,92(sp)
+800007e4:	07912023          	sw	s9,96(sp)
+800007e8:	07a12223          	sw	s10,100(sp)
+800007ec:	07b12423          	sw	s11,104(sp)
+800007f0:	07c12623          	sw	t3,108(sp)
+800007f4:	07d12823          	sw	t4,112(sp)
+800007f8:	07e12a23          	sw	t5,116(sp)
+800007fc:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+  jal MSYS_EI6_IRQHandler
+80000800:	001000ef          	jal	ra,80001000 <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  j generic_restore
+80000804:	1140006f          	j	80000918 <generic_restore>
+
+80000808 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:325
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000808:	f8010113          	addi	sp,sp,-128
+8000080c:	00112023          	sw	ra,0(sp)
+80000810:	00212223          	sw	sp,4(sp)
+80000814:	00312423          	sw	gp,8(sp)
+80000818:	00412623          	sw	tp,12(sp)
+8000081c:	00512823          	sw	t0,16(sp)
+80000820:	00612a23          	sw	t1,20(sp)
+80000824:	00712c23          	sw	t2,24(sp)
+80000828:	00812e23          	sw	s0,28(sp)
+8000082c:	02912023          	sw	s1,32(sp)
+80000830:	02a12223          	sw	a0,36(sp)
+80000834:	02b12423          	sw	a1,40(sp)
+80000838:	02c12623          	sw	a2,44(sp)
+8000083c:	02d12823          	sw	a3,48(sp)
+80000840:	02e12a23          	sw	a4,52(sp)
+80000844:	02f12c23          	sw	a5,56(sp)
+80000848:	03012e23          	sw	a6,60(sp)
+8000084c:	05112023          	sw	a7,64(sp)
+80000850:	05212223          	sw	s2,68(sp)
+80000854:	05312423          	sw	s3,72(sp)
+80000858:	05412623          	sw	s4,76(sp)
+8000085c:	05512823          	sw	s5,80(sp)
+80000860:	05612a23          	sw	s6,84(sp)
+80000864:	05712c23          	sw	s7,88(sp)
+80000868:	05812e23          	sw	s8,92(sp)
+8000086c:	07912023          	sw	s9,96(sp)
+80000870:	07a12223          	sw	s10,100(sp)
+80000874:	07b12423          	sw	s11,104(sp)
+80000878:	07c12623          	sw	t3,108(sp)
+8000087c:	07d12823          	sw	t4,112(sp)
+80000880:	07e12a23          	sw	t5,116(sp)
+80000884:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+  jal MSYS_EI7_IRQHandler
+80000888:	794000ef          	jal	ra,8000101c <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  j generic_restore
+8000088c:	08c0006f          	j	80000918 <generic_restore>
+
+80000890 <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:331
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+80000890:	f8010113          	addi	sp,sp,-128
+80000894:	00112023          	sw	ra,0(sp)
+80000898:	00212223          	sw	sp,4(sp)
+8000089c:	00312423          	sw	gp,8(sp)
+800008a0:	00412623          	sw	tp,12(sp)
+800008a4:	00512823          	sw	t0,16(sp)
+800008a8:	00612a23          	sw	t1,20(sp)
+800008ac:	00712c23          	sw	t2,24(sp)
+800008b0:	00812e23          	sw	s0,28(sp)
+800008b4:	02912023          	sw	s1,32(sp)
+800008b8:	02a12223          	sw	a0,36(sp)
+800008bc:	02b12423          	sw	a1,40(sp)
+800008c0:	02c12623          	sw	a2,44(sp)
+800008c4:	02d12823          	sw	a3,48(sp)
+800008c8:	02e12a23          	sw	a4,52(sp)
+800008cc:	02f12c23          	sw	a5,56(sp)
+800008d0:	03012e23          	sw	a6,60(sp)
+800008d4:	05112023          	sw	a7,64(sp)
+800008d8:	05212223          	sw	s2,68(sp)
+800008dc:	05312423          	sw	s3,72(sp)
+800008e0:	05412623          	sw	s4,76(sp)
+800008e4:	05512823          	sw	s5,80(sp)
+800008e8:	05612a23          	sw	s6,84(sp)
+800008ec:	05712c23          	sw	s7,88(sp)
+800008f0:	05812e23          	sw	s8,92(sp)
+800008f4:	07912023          	sw	s9,96(sp)
+800008f8:	07a12223          	sw	s10,100(sp)
+800008fc:	07b12423          	sw	s11,104(sp)
+80000900:	07c12623          	sw	t3,108(sp)
+80000904:	07d12823          	sw	t4,112(sp)
+80000908:	07e12a23          	sw	t5,116(sp)
+8000090c:	07f12c23          	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+  jal SUBSYSR_IRQHandler
+80000910:	728000ef          	jal	ra,80001038 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  j generic_restore
+80000914:	0040006f          	j	80000918 <generic_restore>
+
+80000918 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:339
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000918:	00012083          	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+  LREG x2, 1 * REGBYTES(sp)
+8000091c:	00412103          	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x3, 2 * REGBYTES(sp)
+80000920:	00812183          	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x4, 3 * REGBYTES(sp)
+80000924:	00c12203          	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x5, 4 * REGBYTES(sp)
+80000928:	01012283          	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x6, 5 * REGBYTES(sp)
+8000092c:	01412303          	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x7, 6 * REGBYTES(sp)
+80000930:	01812383          	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x8, 7 * REGBYTES(sp)
+80000934:	01c12403          	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x9, 8 * REGBYTES(sp)
+80000938:	02012483          	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x10, 9 * REGBYTES(sp)
+8000093c:	02412503          	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x11, 10 * REGBYTES(sp)
+80000940:	02812583          	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x12, 11 * REGBYTES(sp)
+80000944:	02c12603          	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x13, 12 * REGBYTES(sp)
+80000948:	03012683          	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x14, 13 * REGBYTES(sp)
+8000094c:	03412703          	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x15, 14 * REGBYTES(sp)
+80000950:	03812783          	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x16, 15 * REGBYTES(sp)
+80000954:	03c12803          	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x17, 16 * REGBYTES(sp)
+80000958:	04012883          	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x18, 17 * REGBYTES(sp)
+8000095c:	04412903          	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x19, 18 * REGBYTES(sp)
+80000960:	04812983          	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x20, 19 * REGBYTES(sp)
+80000964:	04c12a03          	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x21, 20 * REGBYTES(sp)
+80000968:	05012a83          	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x22, 21 * REGBYTES(sp)
+8000096c:	05412b03          	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x23, 22 * REGBYTES(sp)
+80000970:	05812b83          	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x24, 23 * REGBYTES(sp)
+80000974:	05c12c03          	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x25, 24 * REGBYTES(sp)
+80000978:	06012c83          	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x26, 25 * REGBYTES(sp)
+8000097c:	06412d03          	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x27, 26 * REGBYTES(sp)
+80000980:	06812d83          	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x28, 27 * REGBYTES(sp)
+80000984:	06c12e03          	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x29, 28 * REGBYTES(sp)
+80000988:	07012e83          	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x30, 29 * REGBYTES(sp)
+8000098c:	07412f03          	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x31, 30 * REGBYTES(sp)
+80000990:	07812f83          	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:408
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+80000994:	08010113          	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  mret
+80000998:	30200073          	mret
+8000099c:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+800009a0 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:418
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+800009a0:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+  csrwi mie, 0
+800009a4:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  la ra, _start
+800009a8:	fffff097          	auipc	ra,0xfffff
+800009ac:	65808093          	addi	ra,ra,1624 # 80000000 <RAM_START_ADDRESS>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:424
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+800009b0:	0200c2b7          	lui	t0,0x200c
+800009b4:	ffc28293          	addi	t0,t0,-4 # 200bffc <RAM_SIZE+0x2003ffc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+  sw x0, 0(t0)
+800009b8:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:428
+#endif
+
+  csrr t0, misa
+800009bc:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+  andi t0, t0, A_EXTENSION_MASK
+800009c0:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+800009c4:	02029663          	bnez	t0,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:438
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+800009c8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+800009cc:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  li t1, MTVEC_VECTORED_MODE_VAL
+800009d0:	00100313          	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+800009d4:	00629e63          	bne	t0,t1,800009f0 <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:445
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+800009d8:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+  andi t0, t0, 0xFFFFFFFC
+800009dc:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  la t1, trap_entry
+800009e0:	fffff317          	auipc	t1,0xfffff
+800009e4:	62430313          	addi	t1,t1,1572 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  bne t0, t1, vector_address_not_matching
+800009e8:	04629863          	bne	t0,t1,80000a38 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  j generic_reset_handling
+800009ec:	0100006f          	j	800009fc <generic_reset_handling>
+
+800009f0 <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:476
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+800009f0:	fffff297          	auipc	t0,0xfffff
+800009f4:	61428293          	addi	t0,t0,1556 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:482
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+800009f8:	30529073          	csrw	mtvec,t0
+
+800009fc <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:487
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+800009fc:	00001717          	auipc	a4,0x1
+80000a00:	20470713          	addi	a4,a4,516 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+    la a5, __sdata_start
+80000a04:	00001797          	auipc	a5,0x1
+80000a08:	1fc78793          	addi	a5,a5,508 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a6, __sdata_end
+80000a0c:	00001817          	auipc	a6,0x1
+80000a10:	1f480813          	addi	a6,a6,500 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+80000a14:	00f70863          	beq	a4,a5,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+80000a18:	01078663          	beq	a5,a6,80000a24 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    call block_copy
+80000a1c:	00000097          	auipc	ra,0x0
+80000a20:	09c080e7          	jalr	156(ra) # 80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:496
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+80000a24:	00002197          	auipc	gp,0x2
+80000a28:	9dc18193          	addi	gp,gp,-1572 # 80002400 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:513
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+80000a2c:	010000ef          	jal	ra,80000a3c <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:515
+  /* Initialize stack pointer */
+  la sp, __stack_top
+80000a30:	10018113          	addi	sp,gp,256 # 80002500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:518
+
+  /* Jump into C code */
+  j _init
+80000a34:	4400006f          	j	80000e74 <_init>
+
+80000a38 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:523
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+80000a38:	00100073          	ebreak
+
+80000a3c <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:527
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+80000a3c:	00008293          	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+    la  a5, __bss_start
+80000a40:	8e018793          	addi	a5,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a6, __bss_end
+80000a44:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a48:	01078463          	beq	a5,a6,80000a50 <initializations+0x14>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    call zeroize_block
+80000a4c:	04c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:535
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000a50:	8c018793          	addi	a5,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+    la  a6, __sbss_end
+80000a54:	8e018813          	addi	a6,gp,-1824 # 80001ce0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a58:	01078c63          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    call zeroize_block
+80000a5c:	03c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:541
+
+/* Clear heap */
+    la  a5, __heap_start
+80000a60:	90018793          	addi	a5,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+    la  a6, __heap_end
+80000a64:	90018813          	addi	a6,gp,-1792 # 80001d00 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    beq a5, a6, 1f     /* Section start and end address are the same */
+80000a68:	01078463          	beq	a5,a6,80000a70 <initializations+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    call zeroize_block
+80000a6c:	02c000ef          	jal	ra,80000a98 <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:548
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000a70:	00001717          	auipc	a4,0x1
+80000a74:	19070713          	addi	a4,a4,400 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+    la  a5, __data_start
+80000a78:	00001797          	auipc	a5,0x1
+80000a7c:	18878793          	addi	a5,a5,392 # 80001c00 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a6, __data_end
+80000a80:	8c018813          	addi	a6,gp,-1856 # 80001cc0 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000a84:	00f70663          	beq	a4,a5,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000a88:	01078463          	beq	a5,a6,80000a90 <initializations+0x54>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    call block_copy
+80000a8c:	02c000ef          	jal	ra,80000ab8 <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:556
+
+1:
+    mv ra, t0           /* Retrieve ra */
+80000a90:	00028093          	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+    ret
+80000a94:	00008067          	ret
+
+80000a98 <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:560
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000a98:	04f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000a9c:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    andi a7, a7, 0x03u
+80000aa0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000aa4:	03104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000aa8 <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:565
+zeroize_loop:
+    sw x0, 0(a5)
+80000aa8:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+    add a5, a5, __SIZEOF_POINTER__
+80000aac:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    blt a5, a6, zeroize_loop
+80000ab0:	ff07cce3          	blt	a5,a6,80000aa8 <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    ret
+80000ab4:	00008067          	ret
+
+80000ab8 <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:571
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+80000ab8:	02f86463          	bltu	a6,a5,80000ae0 <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000abc:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    andi a7, a7, 0x03u
+80000ac0:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000ac4:	01104e63          	bgtz	a7,80000ae0 <block_copy_error>
+
+80000ac8 <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:576
+block_copy_loop:
+    lw a7, 0(a4)
+80000ac8:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+    sw a7, 0(a5)
+80000acc:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    addi a5, a5, 0x04
+80000ad0:	00478793          	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a4, a4, 0x04
+80000ad4:	00470713          	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    blt a5, a6, block_copy_loop
+80000ad8:	ff07c8e3          	blt	a5,a6,80000ac8 <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    j block_copy_exit
+80000adc:	0080006f          	j	80000ae4 <block_copy_exit>
+
+80000ae0 <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:584
+
+block_copy_error:
+    j block_copy_error
+80000ae0:	0000006f          	j	80000ae0 <block_copy_error>
+
+80000ae4 <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_entry.S:587
+
+block_copy_exit:
+    ret
+80000ae4:	00008067          	ret
+
+80000ae8 <MRV_clear_soft_irq>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:730
+
+  @return
+  This function does not return any value.
+ */
+static inline void MRV_clear_soft_irq(void)
+{
+80000ae8:	ff010113          	addi	sp,sp,-16
+80000aec:	00812623          	sw	s0,12(sp)
+80000af0:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000af4:	000067b7          	lui	a5,0x6
+80000af8:	0207a703          	lw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+80000afc:	000067b7          	lui	a5,0x6
+80000b00:	ffd77713          	andi	a4,a4,-3
+80000b04:	02e7a023          	sw	a4,32(a5) # 6020 <STACK_SIZE+0x5820>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.h:737
+#endif
+}
+80000b08:	00000013          	nop
+80000b0c:	00c12403          	lw	s0,12(sp)
+80000b10:	01010113          	addi	sp,sp,16
+80000b14:	00008067          	ret
+
+80000b18 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000b18:	fd010113          	addi	sp,sp,-48
+80000b1c:	02112623          	sw	ra,44(sp)
+80000b20:	02812423          	sw	s0,40(sp)
+80000b24:	03010413          	addi	s0,sp,48
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+80000b28:	08000793          	li	a5,128
+80000b2c:	3047b7f3          	csrrc	a5,mie,a5
+80000b30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MTIME;
+80000b34:	0200c7b7          	lui	a5,0x200c
+80000b38:	ff878793          	addi	a5,a5,-8 # 200bff8 <RAM_SIZE+0x2003ff8>
+80000b3c:	0007a783          	lw	a5,0(a5)
+80000b40:	fef42023          	sw	a5,-32(s0)
+80000b44:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000b48:	05c0006f          	j	80000ba4 <handle_m_timer_interrupt+0x8c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000b4c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b50:	0047a803          	lw	a6,4(a5)
+80000b54:	0007a783          	lw	a5,0(a5)
+80000b58:	8c018713          	addi	a4,gp,-1856 # 80001cc0 <__data_end>
+80000b5c:	00072583          	lw	a1,0(a4)
+80000b60:	00472603          	lw	a2,4(a4)
+80000b64:	00b786b3          	add	a3,a5,a1
+80000b68:	00068513          	mv	a0,a3
+80000b6c:	00f53533          	sltu	a0,a0,a5
+80000b70:	00c80733          	add	a4,a6,a2
+80000b74:	00e507b3          	add	a5,a0,a4
+80000b78:	00078713          	mv	a4,a5
+80000b7c:	00068793          	mv	a5,a3
+80000b80:	00070813          	mv	a6,a4
+80000b84:	8c818713          	addi	a4,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000b88:	00f72023          	sw	a5,0(a4)
+80000b8c:	01072223          	sw	a6,4(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:205
+
+#ifndef NDEBUG
+        d_tick += 1;
+80000b90:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000b94:	0007a783          	lw	a5,0(a5)
+80000b98:	00178713          	addi	a4,a5,1
+80000b9c:	8d018793          	addi	a5,gp,-1840 # 80001cd0 <d_tick.2196>
+80000ba0:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000ba4:	fe042783          	lw	a5,-32(s0)
+80000ba8:	fe442803          	lw	a6,-28(s0)
+80000bac:	00500593          	li	a1,5
+80000bb0:	00000613          	li	a2,0
+80000bb4:	00b786b3          	add	a3,a5,a1
+80000bb8:	00068513          	mv	a0,a3
+80000bbc:	00f53533          	sltu	a0,a0,a5
+80000bc0:	00c80733          	add	a4,a6,a2
+80000bc4:	00e507b3          	add	a5,a0,a4
+80000bc8:	00078713          	mv	a4,a5
+80000bcc:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000bd0:	0047a803          	lw	a6,4(a5)
+80000bd4:	0007a783          	lw	a5,0(a5)
+80000bd8:	00070593          	mv	a1,a4
+80000bdc:	00080613          	mv	a2,a6
+80000be0:	f6b666e3          	bltu	a2,a1,80000b4c <handle_m_timer_interrupt+0x34>
+80000be4:	00070593          	mv	a1,a4
+80000be8:	00080613          	mv	a2,a6
+80000bec:	00c59663          	bne	a1,a2,80000bf8 <handle_m_timer_interrupt+0xe0>
+80000bf0:	00068713          	mv	a4,a3
+80000bf4:	f4e7ece3          	bltu	a5,a4,80000b4c <handle_m_timer_interrupt+0x34>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+80000bf8:	020047b7          	lui	a5,0x2004
+80000bfc:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c00:	fff00713          	li	a4,-1
+80000c04:	00e7a023          	sw	a4,0(a5)
+80000c08:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c0c:	0047a803          	lw	a6,4(a5)
+80000c10:	0007a783          	lw	a5,0(a5)
+80000c14:	02004737          	lui	a4,0x2004
+80000c18:	00f72023          	sw	a5,0(a4) # 2004000 <RAM_SIZE+0x1ffc000>
+80000c1c:	8c818793          	addi	a5,gp,-1848 # 80001cc8 <g_systick_cmp_value>
+80000c20:	0047a803          	lw	a6,4(a5)
+80000c24:	0007a783          	lw	a5,0(a5)
+80000c28:	00085313          	srli	t1,a6,0x0
+80000c2c:	00000393          	li	t2,0
+80000c30:	020047b7          	lui	a5,0x2004
+80000c34:	00478793          	addi	a5,a5,4 # 2004004 <RAM_SIZE+0x1ffc004>
+80000c38:	00030713          	mv	a4,t1
+80000c3c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000c40:	290000ef          	jal	ra,80000ed0 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000c44:	08000793          	li	a5,128
+80000c48:	3047a7f3          	csrrs	a5,mie,a5
+80000c4c:	fcf42e23          	sw	a5,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+80000c50:	00000013          	nop
+80000c54:	02c12083          	lw	ra,44(sp)
+80000c58:	02812403          	lw	s0,40(sp)
+80000c5c:	03010113          	addi	sp,sp,48
+80000c60:	00008067          	ret
+
+80000c64 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+80000c64:	ff010113          	addi	sp,sp,-16
+80000c68:	00112623          	sw	ra,12(sp)
+80000c6c:	00812423          	sw	s0,8(sp)
+80000c70:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+80000c74:	244000ef          	jal	ra,80000eb8 <Software_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:233
+    MRV_clear_soft_irq();
+80000c78:	e71ff0ef          	jal	ra,80000ae8 <MRV_clear_soft_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+}
+80000c7c:	00000013          	nop
+80000c80:	00c12083          	lw	ra,12(sp)
+80000c84:	00812403          	lw	s0,8(sp)
+80000c88:	01010113          	addi	sp,sp,16
+80000c8c:	00008067          	ret
+
+80000c90 <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:305
+
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+80000c90:	fc010113          	addi	sp,sp,-64
+80000c94:	02112e23          	sw	ra,60(sp)
+80000c98:	02812c23          	sw	s0,56(sp)
+80000c9c:	04010413          	addi	s0,sp,64
+80000ca0:	00050793          	mv	a5,a0
+80000ca4:	fcf407a3          	sb	a5,-49(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+    uint64_t mhart_id = read_csr(mhartid);
+80000ca8:	f14027f3          	csrr	a5,mhartid
+80000cac:	fef42623          	sw	a5,-20(s0)
+80000cb0:	fec42783          	lw	a5,-20(s0)
+80000cb4:	fef42023          	sw	a5,-32(s0)
+80000cb8:	fe042223          	sw	zero,-28(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+80000cbc:	fcf44703          	lbu	a4,-49(s0)
+80000cc0:	01f00793          	li	a5,31
+80000cc4:	00e7f463          	bgeu	a5,a4,80000ccc <handle_local_ei_interrupts+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:307 (discriminator 1)
+80000cc8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+80000ccc:	fcf44703          	lbu	a4,-49(s0)
+80000cd0:	00f00793          	li	a5,15
+80000cd4:	00e7e463          	bltu	a5,a4,80000cdc <handle_local_ei_interrupts+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:308 (discriminator 1)
+80000cd8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+80000cdc:	fcf44783          	lbu	a5,-49(s0)
+80000ce0:	ff078793          	addi	a5,a5,-16
+80000ce4:	fcf40fa3          	sb	a5,-33(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+80000ce8:	fdf44783          	lbu	a5,-33(s0)
+80000cec:	00001717          	auipc	a4,0x1
+80000cf0:	ed470713          	addi	a4,a4,-300 # 80001bc0 <local_irq_handler_table>
+80000cf4:	00279793          	slli	a5,a5,0x2
+80000cf8:	00f707b3          	add	a5,a4,a5
+80000cfc:	0007a783          	lw	a5,0(a5)
+80000d00:	000780e7          	jalr	a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:312
+}
+80000d04:	00000013          	nop
+80000d08:	03c12083          	lw	ra,60(sp)
+80000d0c:	03812403          	lw	s0,56(sp)
+80000d10:	04010113          	addi	sp,sp,64
+80000d14:	00008067          	ret
+
+80000d18 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+
+/*------------------------------------------------------------------------------
+ * Trap handler. This function is invoked in the non-vectored mode.
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+80000d18:	fa010113          	addi	sp,sp,-96
+80000d1c:	04112e23          	sw	ra,92(sp)
+80000d20:	04812c23          	sw	s0,88(sp)
+80000d24:	06010413          	addi	s0,sp,96
+80000d28:	faa42623          	sw	a0,-84(s0)
+80000d2c:	fab42423          	sw	a1,-88(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:321
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+80000d30:	fac42703          	lw	a4,-84(s0)
+80000d34:	00070793          	mv	a5,a4
+80000d38:	00000813          	li	a6,0
+80000d3c:	80000737          	lui	a4,0x80000
+80000d40:	00e7f733          	and	a4,a5,a4
+80000d44:	fee42423          	sw	a4,-24(s0)
+80000d48:	00087793          	andi	a5,a6,0
+80000d4c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+
+    if (is_interrupt)
+80000d50:	fe842783          	lw	a5,-24(s0)
+80000d54:	fec42703          	lw	a4,-20(s0)
+80000d58:	00e7e7b3          	or	a5,a5,a4
+80000d5c:	0a078063          	beqz	a5,80000dfc <handle_trap+0xe4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+80000d60:	fac42703          	lw	a4,-84(s0)
+80000d64:	800007b7          	lui	a5,0x80000
+80000d68:	ff07c793          	xori	a5,a5,-16
+80000d6c:	00f777b3          	and	a5,a4,a5
+80000d70:	02078663          	beqz	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+80000d74:	fac42703          	lw	a4,-84(s0)
+80000d78:	800007b7          	lui	a5,0x80000
+80000d7c:	fe07c793          	xori	a5,a5,-32
+80000d80:	00f777b3          	and	a5,a4,a5
+80000d84:	00079c63          	bnez	a5,80000d9c <handle_trap+0x84>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000d88:	fac42783          	lw	a5,-84(s0)
+80000d8c:	0ff7f793          	andi	a5,a5,255
+80000d90:	00078513          	mv	a0,a5
+80000d94:	efdff0ef          	jal	ra,80000c90 <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+#endif  /* NDEBUG */
+    }
+}
+80000d98:	0c80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000d9c:	fac42703          	lw	a4,-84(s0)
+80000da0:	800007b7          	lui	a5,0x80000
+80000da4:	fff7c793          	not	a5,a5
+80000da8:	00f77733          	and	a4,a4,a5
+80000dac:	00b00793          	li	a5,11
+80000db0:	00f71663          	bne	a4,a5,80000dbc <handle_trap+0xa4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+            External_IRQHandler();
+80000db4:	138000ef          	jal	ra,80000eec <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000db8:	0a80006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000dbc:	fac42703          	lw	a4,-84(s0)
+80000dc0:	800007b7          	lui	a5,0x80000
+80000dc4:	fff7c793          	not	a5,a5
+80000dc8:	00f77733          	and	a4,a4,a5
+80000dcc:	00300793          	li	a5,3
+80000dd0:	00f71663          	bne	a4,a5,80000ddc <handle_trap+0xc4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+            handle_m_soft_interrupt();
+80000dd4:	e91ff0ef          	jal	ra,80000c64 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000dd8:	0880006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+80000ddc:	fac42703          	lw	a4,-84(s0)
+80000de0:	800007b7          	lui	a5,0x80000
+80000de4:	fff7c793          	not	a5,a5
+80000de8:	00f77733          	and	a4,a4,a5
+80000dec:	00700793          	li	a5,7
+80000df0:	06f71863          	bne	a4,a5,80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+            handle_m_timer_interrupt();
+80000df4:	d25ff0ef          	jal	ra,80000b18 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000df8:	0680006f          	j	80000e60 <handle_trap+0x148>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:382
+         uintptr_t mip      = read_csr(mip);
+80000dfc:	344027f3          	csrr	a5,mip
+80000e00:	fef42223          	sw	a5,-28(s0)
+80000e04:	fe442783          	lw	a5,-28(s0)
+80000e08:	fef42023          	sw	a5,-32(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:385
+         uintptr_t mtval = read_csr(mtval);
+80000e0c:	343027f3          	csrr	a5,mtval
+80000e10:	fcf42e23          	sw	a5,-36(s0)
+80000e14:	fdc42783          	lw	a5,-36(s0)
+80000e18:	fcf42c23          	sw	a5,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:388
+         uintptr_t mtvec    = read_csr(mtvec);
+80000e1c:	305027f3          	csrr	a5,mtvec
+80000e20:	fcf42a23          	sw	a5,-44(s0)
+80000e24:	fd442783          	lw	a5,-44(s0)
+80000e28:	fcf42823          	sw	a5,-48(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:391
+         uintptr_t mscratch = read_csr(mscratch);
+80000e2c:	340027f3          	csrr	a5,mscratch
+80000e30:	fcf42623          	sw	a5,-52(s0)
+80000e34:	fcc42783          	lw	a5,-52(s0)
+80000e38:	fcf42423          	sw	a5,-56(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:394
+         uintptr_t mstatus  = read_csr(mstatus);
+80000e3c:	300027f3          	csrr	a5,mstatus
+80000e40:	fcf42223          	sw	a5,-60(s0)
+80000e44:	fc442783          	lw	a5,-60(s0)
+80000e48:	fcf42023          	sw	a5,-64(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:397
+         uintptr_t mmepc  = read_csr(mepc);
+80000e4c:	341027f3          	csrr	a5,mepc
+80000e50:	faf42e23          	sw	a5,-68(s0)
+80000e54:	fbc42783          	lw	a5,-68(s0)
+80000e58:	faf42c23          	sw	a5,-72(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:400
+        __asm__("ebreak");
+80000e5c:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_hal.c:405
+}
+80000e60:	00000013          	nop
+80000e64:	05c12083          	lw	ra,92(sp)
+80000e68:	05812403          	lw	s0,88(sp)
+80000e6c:	06010113          	addi	sp,sp,96
+80000e70:	00008067          	ret
+
+80000e74 <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:21
+#endif
+
+extern void main(void);
+
+void _init(void)
+{
+80000e74:	ff010113          	addi	sp,sp,-16
+80000e78:	00112623          	sw	ra,12(sp)
+80000e7c:	00812423          	sw	s0,8(sp)
+80000e80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+80000e84:	4b1000ef          	jal	ra,80001b34 <main>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:28
+}
+80000e88:	00000013          	nop
+80000e8c:	00c12083          	lw	ra,12(sp)
+80000e90:	00812403          	lw	s0,8(sp)
+80000e94:	01010113          	addi	sp,sp,16
+80000e98:	00008067          	ret
+
+80000e9c <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:33
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+80000e9c:	ff010113          	addi	sp,sp,-16
+80000ea0:	00812623          	sw	s0,12(sp)
+80000ea4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+}
+80000ea8:	00000013          	nop
+80000eac:	00c12403          	lw	s0,12(sp)
+80000eb0:	01010113          	addi	sp,sp,16
+80000eb4:	00008067          	ret
+
+80000eb8 <Software_IRQHandler>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000eb8:	ff010113          	addi	sp,sp,-16
+80000ebc:	00112623          	sw	ra,12(sp)
+80000ec0:	00812423          	sw	s0,8(sp)
+80000ec4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000ec8:	00a00513          	li	a0,10
+80000ecc:	188000ef          	jal	ra,80001054 <_exit>
+
+80000ed0 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:28
+}
+
+__attribute__((weak)) void SysTick_Handler(void)
+{
+80000ed0:	ff010113          	addi	sp,sp,-16
+80000ed4:	00812623          	sw	s0,12(sp)
+80000ed8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:30
+    /* Default handler */
+}
+80000edc:	00000013          	nop
+80000ee0:	00c12403          	lw	s0,12(sp)
+80000ee4:	01010113          	addi	sp,sp,16
+80000ee8:	00008067          	ret
+
+80000eec <External_IRQHandler>:
+External_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:195
+    return(0U); /* Default handler */
+}
+
+#else
+__attribute__((weak)) void External_IRQHandler(void)
+{
+80000eec:	ff010113          	addi	sp,sp,-16
+80000ef0:	00812623          	sw	s0,12(sp)
+80000ef4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:196
+}
+80000ef8:	00000013          	nop
+80000efc:	00c12403          	lw	s0,12(sp)
+80000f00:	01010113          	addi	sp,sp,16
+80000f04:	00008067          	ret
+
+80000f08 <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:198
+__attribute__((weak)) void MGECI_IRQHandler(void)
+{
+80000f08:	ff010113          	addi	sp,sp,-16
+80000f0c:	00812623          	sw	s0,12(sp)
+80000f10:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:199
+}
+80000f14:	00000013          	nop
+80000f18:	00c12403          	lw	s0,12(sp)
+80000f1c:	01010113          	addi	sp,sp,16
+80000f20:	00008067          	ret
+
+80000f24 <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:201
+__attribute__((weak)) void MGEUI_IRQHandler(void)
+{
+80000f24:	ff010113          	addi	sp,sp,-16
+80000f28:	00812623          	sw	s0,12(sp)
+80000f2c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:202
+}
+80000f30:	00000013          	nop
+80000f34:	00c12403          	lw	s0,12(sp)
+80000f38:	01010113          	addi	sp,sp,16
+80000f3c:	00008067          	ret
+
+80000f40 <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:204
+__attribute__((weak)) void SUBSYS_IRQHandler(void)
+{
+80000f40:	ff010113          	addi	sp,sp,-16
+80000f44:	00812623          	sw	s0,12(sp)
+80000f48:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:205
+}
+80000f4c:	00000013          	nop
+80000f50:	00c12403          	lw	s0,12(sp)
+80000f54:	01010113          	addi	sp,sp,16
+80000f58:	00008067          	ret
+
+80000f5c <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:210
+__attribute__((weak)) void MSYS_EI0_IRQHandler(void)
+{
+}
+__attribute__((weak)) void MSYS_EI1_IRQHandler(void)
+{
+80000f5c:	ff010113          	addi	sp,sp,-16
+80000f60:	00812623          	sw	s0,12(sp)
+80000f64:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:211
+}
+80000f68:	00000013          	nop
+80000f6c:	00c12403          	lw	s0,12(sp)
+80000f70:	01010113          	addi	sp,sp,16
+80000f74:	00008067          	ret
+
+80000f78 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:213
+__attribute__((weak)) void MSYS_EI2_IRQHandler(void)
+{
+80000f78:	ff010113          	addi	sp,sp,-16
+80000f7c:	00812623          	sw	s0,12(sp)
+80000f80:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:214
+}
+80000f84:	00000013          	nop
+80000f88:	00c12403          	lw	s0,12(sp)
+80000f8c:	01010113          	addi	sp,sp,16
+80000f90:	00008067          	ret
+
+80000f94 <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:216
+__attribute__((weak)) void MSYS_EI3_IRQHandler(void)
+{
+80000f94:	ff010113          	addi	sp,sp,-16
+80000f98:	00812623          	sw	s0,12(sp)
+80000f9c:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:217
+}
+80000fa0:	00000013          	nop
+80000fa4:	00c12403          	lw	s0,12(sp)
+80000fa8:	01010113          	addi	sp,sp,16
+80000fac:	00008067          	ret
+
+80000fb0 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:219
+__attribute__((weak)) void MSYS_EI4_IRQHandler(void)
+{
+80000fb0:	ff010113          	addi	sp,sp,-16
+80000fb4:	00812623          	sw	s0,12(sp)
+80000fb8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:220
+}
+80000fbc:	00000013          	nop
+80000fc0:	00c12403          	lw	s0,12(sp)
+80000fc4:	01010113          	addi	sp,sp,16
+80000fc8:	00008067          	ret
+
+80000fcc <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:222
+__attribute__((weak)) void MSYS_EI5_IRQHandler(void)
+{
+80000fcc:	ff010113          	addi	sp,sp,-16
+80000fd0:	00812623          	sw	s0,12(sp)
+80000fd4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:223
+}
+80000fd8:	00000013          	nop
+80000fdc:	00c12403          	lw	s0,12(sp)
+80000fe0:	01010113          	addi	sp,sp,16
+80000fe4:	00008067          	ret
+
+80000fe8 <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:225
+__attribute__((weak)) void Reserved_IRQHandler(void)
+{
+80000fe8:	ff010113          	addi	sp,sp,-16
+80000fec:	00112623          	sw	ra,12(sp)
+80000ff0:	00812423          	sw	s0,8(sp)
+80000ff4:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:226
+    _exit(10);
+80000ff8:	00a00513          	li	a0,10
+80000ffc:	058000ef          	jal	ra,80001054 <_exit>
+
+80001000 <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:230
+}
+#ifndef MIV_RV32_V3_0 /* For MIV_RV32 v3.0 */
+__attribute__((weak)) void MSYS_EI6_IRQHandler(void)
+{
+80001000:	ff010113          	addi	sp,sp,-16
+80001004:	00812623          	sw	s0,12(sp)
+80001008:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:231
+}
+8000100c:	00000013          	nop
+80001010:	00c12403          	lw	s0,12(sp)
+80001014:	01010113          	addi	sp,sp,16
+80001018:	00008067          	ret
+
+8000101c <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:233
+__attribute__((weak)) void MSYS_EI7_IRQHandler(void)
+{
+8000101c:	ff010113          	addi	sp,sp,-16
+80001020:	00812623          	sw	s0,12(sp)
+80001024:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:234
+}
+80001028:	00000013          	nop
+8000102c:	00c12403          	lw	s0,12(sp)
+80001030:	01010113          	addi	sp,sp,16
+80001034:	00008067          	ret
+
+80001038 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:236
+__attribute__((weak)) void SUBSYSR_IRQHandler(void)
+{
+80001038:	ff010113          	addi	sp,sp,-16
+8000103c:	00812623          	sw	s0,12(sp)
+80001040:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:237
+}
+80001044:	00000013          	nop
+80001048:	00c12403          	lw	s0,12(sp)
+8000104c:	01010113          	addi	sp,sp,16
+80001050:	00008067          	ret
+
+80001054 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:142
+#ifdef GDB_TESTING
+void __attribute__((optimize("O0"))) _exit(int code)
+#else
+void _exit(int code)
+#endif
+{
+80001054:	fe010113          	addi	sp,sp,-32
+80001058:	00812e23          	sw	s0,28(sp)
+8000105c:	02010413          	addi	s0,sp,32
+80001060:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80001064:	0000006f          	j	80001064 <_exit+0x10>
+
+80001068 <MRV_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:616
+
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+80001068:	fe010113          	addi	sp,sp,-32
+8000106c:	00812e23          	sw	s0,28(sp)
+80001070:	02010413          	addi	s0,sp,32
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80001074:	300467f3          	csrrsi	a5,mstatus,8
+80001078:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:618
+}
+8000107c:	00000013          	nop
+80001080:	01c12403          	lw	s0,28(sp)
+80001084:	02010113          	addi	sp,sp,32
+80001088:	00008067          	ret
+
+8000108c <HAL_enable_interrupts>:
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:22
+#endif
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+8000108c:	ff010113          	addi	sp,sp,-16
+80001090:	00112623          	sw	ra,12(sp)
+80001094:	00812423          	sw	s0,8(sp)
+80001098:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:23
+    MRV_enable_interrupts();
+8000109c:	fcdff0ef          	jal	ra,80001068 <MRV_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hal_irq.c:24
+}
+800010a0:	00000013          	nop
+800010a4:	00c12083          	lw	ra,12(sp)
+800010a8:	00812403          	lw	s0,8(sp)
+800010ac:	01010113          	addi	sp,sp,16
+800010b0:	00008067          	ret
+
+800010b4 <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+800010b4:	00b52023          	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:40
+    ret
+800010b8:	00008067          	ret
+
+800010bc <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+800010bc:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:52
+    ret
+800010c0:	00008067          	ret
+
+800010c4 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+800010c4:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+800010c8:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+800010cc:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+800010d0:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+800010d4:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+800010d8:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+800010dc:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+800010e0:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+800010e4:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:73
+    ret
+800010e8:	00008067          	ret
+
+800010ec <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+800010ec:	00052503          	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+800010f0:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+800010f4:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:90
+    ret
+800010f8:	00008067          	ret
+
+800010fc <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+800010fc:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:101
+    ret
+80001100:	00008067          	ret
+
+80001104 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+80001104:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:113
+    ret
+80001108:	00008067          	ret
+
+8000110c <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+8000110c:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80001110:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80001114:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80001118:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+8000111c:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+80001120:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80001124:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80001128:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+8000112c:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:135
+    ret
+80001130:	00008067          	ret
+
+80001134 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80001134:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80001138:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+8000113c:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:152
+    ret
+80001140:	00008067          	ret
+
+80001144 <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+80001144:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:163
+    ret
+80001148:	00008067          	ret
+
+8000114c <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+8000114c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:175
+    ret
+80001150:	00008067          	ret
+
+80001154 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80001154:	00068e13          	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+80001158:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+8000115c:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80001160:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80001164:	00060393          	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80001168:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+8000116c:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80001170:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80001174:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:196
+    ret
+80001178:	00008067          	ret
+
+8000117c <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+8000117c:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+80001180:	00c57533          	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80001184:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/hal/hw_reg_access.S:213
+    ret
+80001188:	00008067          	ret
+
+8000118c <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+    UART_instance_t * this_uart,
+    addr_t base_addr,
+    uint16_t baud_value,
+    uint8_t line_config
+)
+{
+8000118c:	fd010113          	addi	sp,sp,-48
+80001190:	02112623          	sw	ra,44(sp)
+80001194:	02812423          	sw	s0,40(sp)
+80001198:	03010413          	addi	s0,sp,48
+8000119c:	fca42e23          	sw	a0,-36(s0)
+800011a0:	fcb42c23          	sw	a1,-40(s0)
+800011a4:	00060793          	mv	a5,a2
+800011a8:	00068713          	mv	a4,a3
+800011ac:	fcf41b23          	sh	a5,-42(s0)
+800011b0:	00070793          	mv	a5,a4
+800011b4:	fcf40aa3          	sb	a5,-43(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49
+    uint8_t rx_full;
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+800011b8:	fdc42783          	lw	a5,-36(s0)
+800011bc:	00079463          	bnez	a5,800011c4 <UART_init+0x38>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:49 (discriminator 1)
+800011c0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+800011c4:	fd544703          	lbu	a4,-43(s0)
+800011c8:	00700793          	li	a5,7
+800011cc:	00e7f463          	bgeu	a5,a4,800011d4 <UART_init+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:50 (discriminator 1)
+800011d0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+800011d4:	fd645703          	lhu	a4,-42(s0)
+800011d8:	000027b7          	lui	a5,0x2
+800011dc:	00f76463          	bltu	a4,a5,800011e4 <UART_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:51 (discriminator 1)
+800011e0:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+800011e4:	fdc42783          	lw	a5,-36(s0)
+800011e8:	16078463          	beqz	a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+800011ec:	fd544703          	lbu	a4,-43(s0)
+800011f0:	00700793          	li	a5,7
+800011f4:	14e7ee63          	bltu	a5,a4,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+800011f8:	fd645703          	lhu	a4,-42(s0)
+800011fc:	000027b7          	lui	a5,0x2
+80001200:	14f77863          	bgeu	a4,a5,80001350 <UART_init+0x1c4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80001204:	fd842783          	lw	a5,-40(s0)
+80001208:	00878713          	addi	a4,a5,8 # 2008 <STACK_SIZE+0x1808>
+8000120c:	fd645783          	lhu	a5,-42(s0)
+80001210:	0ff7f793          	andi	a5,a5,255
+80001214:	00078593          	mv	a1,a5
+80001218:	00070513          	mv	a0,a4
+8000121c:	f29ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80001220:	fd842783          	lw	a5,-40(s0)
+80001224:	00c78693          	addi	a3,a5,12
+80001228:	fd544703          	lbu	a4,-43(s0)
+8000122c:	fd645783          	lhu	a5,-42(s0)
+80001230:	4057d793          	srai	a5,a5,0x5
+80001234:	7f87f793          	andi	a5,a5,2040
+80001238:	00f767b3          	or	a5,a4,a5
+8000123c:	00078593          	mv	a1,a5
+80001240:	00068513          	mv	a0,a3
+80001244:	f01ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+                                           (uint_fast8_t)((baud_value &
+                                   BAUDVALUE_MSB) >> BAUDVALUE_SHIFT ) );
+    
+        this_uart->base_address = base_addr;
+80001248:	fdc42783          	lw	a5,-36(s0)
+8000124c:	fd842703          	lw	a4,-40(s0)
+80001250:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:77
+#ifndef NDEBUG
+        {
+            uint8_t  config;
+            uint8_t  temp;
+            uint16_t baud_val;
+            baud_val = HAL_get_8bit_reg( this_uart->base_address, CTRL1 );
+80001254:	fdc42783          	lw	a5,-36(s0)
+80001258:	0007a783          	lw	a5,0(a5)
+8000125c:	00878793          	addi	a5,a5,8
+80001260:	00078513          	mv	a0,a5
+80001264:	ee9ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001268:	00050793          	mv	a5,a0
+8000126c:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:78
+            config =  HAL_get_8bit_reg( this_uart->base_address, CTRL2 );
+80001270:	fdc42783          	lw	a5,-36(s0)
+80001274:	0007a783          	lw	a5,0(a5)
+80001278:	00c78793          	addi	a5,a5,12
+8000127c:	00078513          	mv	a0,a5
+80001280:	ecdff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001284:	00050793          	mv	a5,a0
+80001288:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:82
+            /*
+             * To resolve operator precedence between & and <<
+             */
+            temp =  ( config  &  (uint8_t)(CTRL2_BAUDVALUE_MASK ) );
+8000128c:	feb44783          	lbu	a5,-21(s0)
+80001290:	ff87f793          	andi	a5,a5,-8
+80001294:	fef40523          	sb	a5,-22(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:83
+            baud_val |= (uint16_t)( (uint16_t)(temp) << BAUDVALUE_SHIFT );
+80001298:	fea44783          	lbu	a5,-22(s0)
+8000129c:	01079793          	slli	a5,a5,0x10
+800012a0:	0107d793          	srli	a5,a5,0x10
+800012a4:	00579793          	slli	a5,a5,0x5
+800012a8:	01079713          	slli	a4,a5,0x10
+800012ac:	01075713          	srli	a4,a4,0x10
+800012b0:	fec45783          	lhu	a5,-20(s0)
+800012b4:	00f767b3          	or	a5,a4,a5
+800012b8:	fef41623          	sh	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:84
+            config &= (uint8_t)(~CTRL2_BAUDVALUE_MASK);
+800012bc:	feb44783          	lbu	a5,-21(s0)
+800012c0:	0077f793          	andi	a5,a5,7
+800012c4:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85
+            HAL_ASSERT( baud_val == baud_value );
+800012c8:	fec45703          	lhu	a4,-20(s0)
+800012cc:	fd645783          	lhu	a5,-42(s0)
+800012d0:	00f70463          	beq	a4,a5,800012d8 <UART_init+0x14c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:85 (discriminator 1)
+800012d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86
+            HAL_ASSERT( config == line_config );
+800012d8:	feb44703          	lbu	a4,-21(s0)
+800012dc:	fd544783          	lbu	a5,-43(s0)
+800012e0:	00f70463          	beq	a4,a5,800012e8 <UART_init+0x15c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:86 (discriminator 1)
+800012e4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800012e8:	fdc42783          	lw	a5,-36(s0)
+800012ec:	0007a783          	lw	a5,0(a5)
+800012f0:	01078793          	addi	a5,a5,16
+800012f4:	00078513          	mv	a0,a5
+800012f8:	e55ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800012fc:	00050793          	mv	a5,a0
+80001300:	0027f793          	andi	a5,a5,2
+80001304:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+80001308:	0380006f          	j	80001340 <UART_init+0x1b4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+8000130c:	fdc42783          	lw	a5,-36(s0)
+80001310:	0007a783          	lw	a5,0(a5)
+80001314:	00478793          	addi	a5,a5,4
+80001318:	00078513          	mv	a0,a5
+8000131c:	e31ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80001320:	fdc42783          	lw	a5,-36(s0)
+80001324:	0007a783          	lw	a5,0(a5)
+80001328:	01078793          	addi	a5,a5,16
+8000132c:	00078513          	mv	a0,a5
+80001330:	e1dff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+80001334:	00050793          	mv	a5,a0
+80001338:	0027f793          	andi	a5,a5,2
+8000133c:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+80001340:	fef44783          	lbu	a5,-17(s0)
+80001344:	fc0794e3          	bnez	a5,8000130c <UART_init+0x180>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+80001348:	fdc42783          	lw	a5,-36(s0)
+8000134c:	00078223          	sb	zero,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+80001350:	00000013          	nop
+80001354:	02c12083          	lw	ra,44(sp)
+80001358:	02812403          	lw	s0,40(sp)
+8000135c:	03010113          	addi	sp,sp,48
+80001360:	00008067          	ret
+
+80001364 <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+UART_polled_tx_string
+( 
+    UART_instance_t * this_uart, 
+    const uint8_t * p_sz_string
+)
+{
+80001364:	fd010113          	addi	sp,sp,-48
+80001368:	02112623          	sw	ra,44(sp)
+8000136c:	02812423          	sw	s0,40(sp)
+80001370:	03010413          	addi	s0,sp,48
+80001374:	fca42e23          	sw	a0,-36(s0)
+80001378:	fcb42c23          	sw	a1,-40(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243
+    uint32_t char_idx;
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+8000137c:	fdc42783          	lw	a5,-36(s0)
+80001380:	00079463          	bnez	a5,80001388 <UART_polled_tx_string+0x24>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:243 (discriminator 1)
+80001384:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+80001388:	fd842783          	lw	a5,-40(s0)
+8000138c:	00079463          	bnez	a5,80001394 <UART_polled_tx_string+0x30>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:244 (discriminator 1)
+80001390:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+80001394:	fdc42783          	lw	a5,-36(s0)
+80001398:	08078063          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+8000139c:	fd842783          	lw	a5,-40(s0)
+800013a0:	06078c63          	beqz	a5,80001418 <UART_polled_tx_string+0xb4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:248
+    {
+        char_idx = 0U;
+800013a4:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+800013a8:	05c0006f          	j	80001404 <UART_polled_tx_string+0xa0>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+        {
+            /* Wait for UART to become ready to transmit. */
+            do {
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800013ac:	fdc42783          	lw	a5,-36(s0)
+800013b0:	0007a783          	lw	a5,0(a5)
+800013b4:	01078793          	addi	a5,a5,16
+800013b8:	00078513          	mv	a0,a5
+800013bc:	d91ff0ef          	jal	ra,8000114c <HW_get_8bit_reg>
+800013c0:	00050793          	mv	a5,a0
+800013c4:	0017f793          	andi	a5,a5,1
+800013c8:	fef405a3          	sb	a5,-21(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+                                                              STATUS_TXRDY_MASK;
+            } while ( !tx_ready );
+800013cc:	feb44783          	lbu	a5,-21(s0)
+800013d0:	fc078ee3          	beqz	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            /* Send next character in the buffer. */
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+800013d4:	fdc42783          	lw	a5,-36(s0)
+800013d8:	0007a683          	lw	a3,0(a5)
+800013dc:	fd842703          	lw	a4,-40(s0)
+800013e0:	fec42783          	lw	a5,-20(s0)
+800013e4:	00f707b3          	add	a5,a4,a5
+800013e8:	0007c783          	lbu	a5,0(a5)
+800013ec:	00078593          	mv	a1,a5
+800013f0:	00068513          	mv	a0,a3
+800013f4:	d51ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+800013f8:	fec42783          	lw	a5,-20(s0)
+800013fc:	00178793          	addi	a5,a5,1
+80001400:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+        while( 0U != p_sz_string[char_idx] )
+80001404:	fd842703          	lw	a4,-40(s0)
+80001408:	fec42783          	lw	a5,-20(s0)
+8000140c:	00f707b3          	add	a5,a4,a5
+80001410:	0007c783          	lbu	a5,0(a5)
+80001414:	f8079ce3          	bnez	a5,800013ac <UART_polled_tx_string+0x48>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+        }
+    }
+}
+80001418:	00000013          	nop
+8000141c:	02c12083          	lw	ra,44(sp)
+80001420:	02812403          	lw	s0,40(sp)
+80001424:	03010113          	addi	sp,sp,48
+80001428:	00008067          	ret
+
+8000142c <TMR_init>:
+TMR_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:30
+    addr_t address,
+    uint8_t mode,
+    uint32_t prescale,
+    uint32_t load_value
+)
+{
+8000142c:	fd010113          	addi	sp,sp,-48
+80001430:	02112623          	sw	ra,44(sp)
+80001434:	02812423          	sw	s0,40(sp)
+80001438:	03010413          	addi	s0,sp,48
+8000143c:	fea42623          	sw	a0,-20(s0)
+80001440:	feb42423          	sw	a1,-24(s0)
+80001444:	00060793          	mv	a5,a2
+80001448:	fed42023          	sw	a3,-32(s0)
+8000144c:	fce42e23          	sw	a4,-36(s0)
+80001450:	fef403a3          	sb	a5,-25(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001454:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001458:	0007a783          	lw	a5,0(a5)
+8000145c:	fec42703          	lw	a4,-20(s0)
+80001460:	00f71463          	bne	a4,a5,80001468 <TMR_init+0x3c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:31 (discriminator 1)
+80001464:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32
+    HAL_ASSERT( prescale <= PRESCALER_DIV_1024 )
+80001468:	fe042703          	lw	a4,-32(s0)
+8000146c:	00900793          	li	a5,9
+80001470:	00e7f463          	bgeu	a5,a4,80001478 <TMR_init+0x4c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:32 (discriminator 1)
+80001474:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33
+    HAL_ASSERT( load_value != 0 )
+80001478:	fdc42783          	lw	a5,-36(s0)
+8000147c:	00079463          	bnez	a5,80001484 <TMR_init+0x58>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:33 (discriminator 1)
+80001480:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:35
+    
+    this_timer->base_address = address;
+80001484:	fec42783          	lw	a5,-20(s0)
+80001488:	fe842703          	lw	a4,-24(s0)
+8000148c:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:38
+
+    /* Disable interrupts. */
+    HAL_set_32bit_reg_field( address, InterruptEnable,0 );
+80001490:	fe842783          	lw	a5,-24(s0)
+80001494:	00878793          	addi	a5,a5,8
+80001498:	00000693          	li	a3,0
+8000149c:	00200613          	li	a2,2
+800014a0:	00100593          	li	a1,1
+800014a4:	00078513          	mv	a0,a5
+800014a8:	c1dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:41
+
+    /* Disable timer. */
+    HAL_set_32bit_reg_field( address, TimerEnable, 0 );
+800014ac:	fe842783          	lw	a5,-24(s0)
+800014b0:	00878793          	addi	a5,a5,8
+800014b4:	00000693          	li	a3,0
+800014b8:	00100613          	li	a2,1
+800014bc:	00000593          	li	a1,0
+800014c0:	00078513          	mv	a0,a5
+800014c4:	c01ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:44
+
+    /* Clear pending interrupt. */
+    HAL_set_32bit_reg( address, TimerIntClr, 1 );
+800014c8:	fe842783          	lw	a5,-24(s0)
+800014cc:	01078793          	addi	a5,a5,16
+800014d0:	00100593          	li	a1,1
+800014d4:	00078513          	mv	a0,a5
+800014d8:	bddff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:47
+
+    /* Configure prescaler and load value. */    
+    HAL_set_32bit_reg( address, TimerPrescale, prescale );
+800014dc:	fe842783          	lw	a5,-24(s0)
+800014e0:	00c78793          	addi	a5,a5,12
+800014e4:	fe042583          	lw	a1,-32(s0)
+800014e8:	00078513          	mv	a0,a5
+800014ec:	bc9ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:48
+    HAL_set_32bit_reg( address, TimerLoad, load_value );
+800014f0:	fdc42583          	lw	a1,-36(s0)
+800014f4:	fe842503          	lw	a0,-24(s0)
+800014f8:	bbdff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:51
+
+    /* Set the interrupt mode. */
+    if ( mode == TMR_CONTINUOUS_MODE )
+800014fc:	fe744783          	lbu	a5,-25(s0)
+80001500:	02079263          	bnez	a5,80001524 <TMR_init+0xf8>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:53
+    {
+        HAL_set_32bit_reg_field( address, TimerMode, 0 );
+80001504:	fe842783          	lw	a5,-24(s0)
+80001508:	00878793          	addi	a5,a5,8
+8000150c:	00000693          	li	a3,0
+80001510:	00400613          	li	a2,4
+80001514:	00200593          	li	a1,2
+80001518:	00078513          	mv	a0,a5
+8000151c:	ba9ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+    else
+    {
+        /* TMR_ONE_SHOT_MODE */
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+    }
+}
+80001520:	0200006f          	j	80001540 <TMR_init+0x114>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:58
+        HAL_set_32bit_reg_field( address, TimerMode, 1 );
+80001524:	fe842783          	lw	a5,-24(s0)
+80001528:	00878793          	addi	a5,a5,8
+8000152c:	00100693          	li	a3,1
+80001530:	00400613          	li	a2,4
+80001534:	00200593          	li	a1,2
+80001538:	00078513          	mv	a0,a5
+8000153c:	b89ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:60
+}
+80001540:	00000013          	nop
+80001544:	02c12083          	lw	ra,44(sp)
+80001548:	02812403          	lw	s0,40(sp)
+8000154c:	03010113          	addi	sp,sp,48
+80001550:	00008067          	ret
+
+80001554 <TMR_start>:
+TMR_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:71
+void
+TMR_start
+(
+    timer_instance_t * this_timer
+)
+{
+80001554:	fe010113          	addi	sp,sp,-32
+80001558:	00112e23          	sw	ra,28(sp)
+8000155c:	00812c23          	sw	s0,24(sp)
+80001560:	02010413          	addi	s0,sp,32
+80001564:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001568:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+8000156c:	0007a783          	lw	a5,0(a5)
+80001570:	fec42703          	lw	a4,-20(s0)
+80001574:	00f71463          	bne	a4,a5,8000157c <TMR_start+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:72 (discriminator 1)
+80001578:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:74
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, TimerEnable, 1 );
+8000157c:	fec42783          	lw	a5,-20(s0)
+80001580:	0007a783          	lw	a5,0(a5)
+80001584:	00878793          	addi	a5,a5,8
+80001588:	00100693          	li	a3,1
+8000158c:	00100613          	li	a2,1
+80001590:	00000593          	li	a1,0
+80001594:	00078513          	mv	a0,a5
+80001598:	b2dff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:75
+}
+8000159c:	00000013          	nop
+800015a0:	01c12083          	lw	ra,28(sp)
+800015a4:	01812403          	lw	s0,24(sp)
+800015a8:	02010113          	addi	sp,sp,32
+800015ac:	00008067          	ret
+
+800015b0 <TMR_enable_int>:
+TMR_enable_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:102
+void
+TMR_enable_int
+(
+    timer_instance_t * this_timer
+)
+{
+800015b0:	fe010113          	addi	sp,sp,-32
+800015b4:	00112e23          	sw	ra,28(sp)
+800015b8:	00812c23          	sw	s0,24(sp)
+800015bc:	02010413          	addi	s0,sp,32
+800015c0:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+800015c4:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+800015c8:	0007a783          	lw	a5,0(a5)
+800015cc:	fec42703          	lw	a4,-20(s0)
+800015d0:	00f71463          	bne	a4,a5,800015d8 <TMR_enable_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:103 (discriminator 1)
+800015d4:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:105
+    
+    HAL_set_32bit_reg_field( this_timer->base_address, InterruptEnable, 1 );
+800015d8:	fec42783          	lw	a5,-20(s0)
+800015dc:	0007a783          	lw	a5,0(a5)
+800015e0:	00878793          	addi	a5,a5,8
+800015e4:	00100693          	li	a3,1
+800015e8:	00200613          	li	a2,2
+800015ec:	00100593          	li	a1,1
+800015f0:	00078513          	mv	a0,a5
+800015f4:	ad1ff0ef          	jal	ra,800010c4 <HW_set_32bit_reg_field>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:106
+}
+800015f8:	00000013          	nop
+800015fc:	01c12083          	lw	ra,28(sp)
+80001600:	01812403          	lw	s0,24(sp)
+80001604:	02010113          	addi	sp,sp,32
+80001608:	00008067          	ret
+
+8000160c <TMR_clear_int>:
+TMR_clear_int():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:117
+void
+TMR_clear_int
+(
+    timer_instance_t * this_timer
+)
+{
+8000160c:	fe010113          	addi	sp,sp,-32
+80001610:	00112e23          	sw	ra,28(sp)
+80001614:	00812c23          	sw	s0,24(sp)
+80001618:	02010413          	addi	s0,sp,32
+8000161c:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118
+    HAL_ASSERT( this_timer != NULL_timer_instance )
+80001620:	8d418793          	addi	a5,gp,-1836 # 80001cd4 <NULL_timer_instance>
+80001624:	0007a783          	lw	a5,0(a5)
+80001628:	fec42703          	lw	a4,-20(s0)
+8000162c:	00f71463          	bne	a4,a5,80001634 <TMR_clear_int+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:118 (discriminator 1)
+80001630:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:120
+    
+    HAL_set_32bit_reg( this_timer->base_address, TimerIntClr, 0x01 );
+80001634:	fec42783          	lw	a5,-20(s0)
+80001638:	0007a783          	lw	a5,0(a5)
+8000163c:	01078793          	addi	a5,a5,16
+80001640:	00100593          	li	a1,1
+80001644:	00078513          	mv	a0,a5
+80001648:	a6dff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreTimer/core_timer.c:121
+}
+8000164c:	00000013          	nop
+80001650:	01c12083          	lw	ra,28(sp)
+80001654:	01812403          	lw	s0,24(sp)
+80001658:	02010113          	addi	sp,sp,32
+8000165c:	00008067          	ret
+
+80001660 <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+80001660:	fd010113          	addi	sp,sp,-48
+80001664:	02112623          	sw	ra,44(sp)
+80001668:	02812423          	sw	s0,40(sp)
+8000166c:	03010413          	addi	s0,sp,48
+80001670:	fca42e23          	sw	a0,-36(s0)
+80001674:	fcb42c23          	sw	a1,-40(s0)
+80001678:	fcc42a23          	sw	a2,-44(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:38
+    uint8_t i = 0;
+8000167c:	fe0407a3          	sb	zero,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:39
+    addr_t cfg_reg_addr = base_addr;
+80001680:	fd842783          	lw	a5,-40(s0)
+80001684:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    
+    this_gpio->base_addr = base_addr;
+80001688:	fdc42783          	lw	a5,-36(s0)
+8000168c:	fd842703          	lw	a4,-40(s0)
+80001690:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+80001694:	fdc42783          	lw	a5,-36(s0)
+80001698:	fd442703          	lw	a4,-44(s0)
+8000169c:	00e7a223          	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016a0:	fe0407a3          	sb	zero,-17(s0)
+800016a4:	fd842783          	lw	a5,-40(s0)
+800016a8:	fef42423          	sw	a5,-24(s0)
+800016ac:	0280006f          	j	800016d4 <GPIO_init+0x74>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+800016b0:	00000593          	li	a1,0
+800016b4:	fe842503          	lw	a0,-24(s0)
+800016b8:	a8dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+800016bc:	fe842783          	lw	a5,-24(s0)
+800016c0:	00478793          	addi	a5,a5,4
+800016c4:	fef42423          	sw	a5,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+800016c8:	fef44783          	lbu	a5,-17(s0)
+800016cc:	00178793          	addi	a5,a5,1
+800016d0:	fef407a3          	sb	a5,-17(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 1)
+800016d4:	fef44703          	lbu	a4,-17(s0)
+800016d8:	01f00793          	li	a5,31
+800016dc:	fce7fae3          	bgeu	a5,a4,800016b0 <GPIO_init+0x50>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+800016e0:	fdc42783          	lw	a5,-36(s0)
+800016e4:	0047a783          	lw	a5,4(a5)
+800016e8:	00100713          	li	a4,1
+800016ec:	02e78663          	beq	a5,a4,80001718 <GPIO_init+0xb8>
+800016f0:	06078263          	beqz	a5,80001754 <GPIO_init+0xf4>
+800016f4:	00200713          	li	a4,2
+800016f8:	0ce79063          	bne	a5,a4,800017b8 <GPIO_init+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+800016fc:	fdc42783          	lw	a5,-36(s0)
+80001700:	0007a783          	lw	a5,0(a5)
+80001704:	08078793          	addi	a5,a5,128
+80001708:	fff00593          	li	a1,-1
+8000170c:	00078513          	mv	a0,a5
+80001710:	9a5ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:55
+            break;
+80001714:	0ac0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+80001718:	fdc42783          	lw	a5,-36(s0)
+8000171c:	0007a783          	lw	a5,0(a5)
+80001720:	08078713          	addi	a4,a5,128
+80001724:	000107b7          	lui	a5,0x10
+80001728:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+8000172c:	00070513          	mv	a0,a4
+80001730:	9cdff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80001734:	fdc42783          	lw	a5,-36(s0)
+80001738:	0007a783          	lw	a5,0(a5)
+8000173c:	08478713          	addi	a4,a5,132
+80001740:	000107b7          	lui	a5,0x10
+80001744:	fff78593          	addi	a1,a5,-1 # ffff <RAM_SIZE+0x7fff>
+80001748:	00070513          	mv	a0,a4
+8000174c:	9b1ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:60
+            break;
+80001750:	0700006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+80001754:	fdc42783          	lw	a5,-36(s0)
+80001758:	0007a783          	lw	a5,0(a5)
+8000175c:	08078793          	addi	a5,a5,128
+80001760:	0ff00593          	li	a1,255
+80001764:	00078513          	mv	a0,a5
+80001768:	9ddff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+8000176c:	fdc42783          	lw	a5,-36(s0)
+80001770:	0007a783          	lw	a5,0(a5)
+80001774:	08478793          	addi	a5,a5,132
+80001778:	0ff00593          	li	a1,255
+8000177c:	00078513          	mv	a0,a5
+80001780:	9c5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+80001784:	fdc42783          	lw	a5,-36(s0)
+80001788:	0007a783          	lw	a5,0(a5)
+8000178c:	08878793          	addi	a5,a5,136
+80001790:	0ff00593          	li	a1,255
+80001794:	00078513          	mv	a0,a5
+80001798:	9adff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+8000179c:	fdc42783          	lw	a5,-36(s0)
+800017a0:	0007a783          	lw	a5,0(a5)
+800017a4:	08c78793          	addi	a5,a5,140
+800017a8:	0ff00593          	li	a1,255
+800017ac:	00078513          	mv	a0,a5
+800017b0:	995ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:67
+            break;
+800017b4:	00c0006f          	j	800017c0 <GPIO_init+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:70 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+800017b8:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:71 (discriminator 1)
+            break;
+800017bc:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+    }
+}
+800017c0:	00000013          	nop
+800017c4:	02c12083          	lw	ra,44(sp)
+800017c8:	02812403          	lw	s0,40(sp)
+800017cc:	03010113          	addi	sp,sp,48
+800017d0:	00008067          	ret
+
+800017d4 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+void GPIO_set_outputs
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+800017d4:	fe010113          	addi	sp,sp,-32
+800017d8:	00112e23          	sw	ra,28(sp)
+800017dc:	00812c23          	sw	s0,24(sp)
+800017e0:	02010413          	addi	s0,sp,32
+800017e4:	fea42623          	sw	a0,-20(s0)
+800017e8:	feb42423          	sw	a1,-24(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+800017ec:	fec42783          	lw	a5,-20(s0)
+800017f0:	0047a783          	lw	a5,4(a5)
+800017f4:	00100713          	li	a4,1
+800017f8:	02e78663          	beq	a5,a4,80001824 <GPIO_set_outputs+0x50>
+800017fc:	06078c63          	beqz	a5,80001874 <GPIO_set_outputs+0xa0>
+80001800:	00200713          	li	a4,2
+80001804:	10e79063          	bne	a5,a4,80001904 <GPIO_set_outputs+0x130>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80001808:	fec42783          	lw	a5,-20(s0)
+8000180c:	0007a783          	lw	a5,0(a5)
+80001810:	0a078793          	addi	a5,a5,160
+80001814:	fe842583          	lw	a1,-24(s0)
+80001818:	00078513          	mv	a0,a5
+8000181c:	899ff0ef          	jal	ra,800010b4 <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:119
+            break;
+80001820:	0ec0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            
+        case GPIO_APB_16_BITS_BUS:
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+80001824:	fec42783          	lw	a5,-20(s0)
+80001828:	0007a783          	lw	a5,0(a5)
+8000182c:	0a078793          	addi	a5,a5,160
+80001830:	fe842703          	lw	a4,-24(s0)
+80001834:	01071713          	slli	a4,a4,0x10
+80001838:	01075713          	srli	a4,a4,0x10
+8000183c:	00070593          	mv	a1,a4
+80001840:	00078513          	mv	a0,a5
+80001844:	8b9ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80001848:	fec42783          	lw	a5,-20(s0)
+8000184c:	0007a783          	lw	a5,0(a5)
+80001850:	0a478713          	addi	a4,a5,164
+80001854:	fe842783          	lw	a5,-24(s0)
+80001858:	0107d793          	srli	a5,a5,0x10
+8000185c:	01079793          	slli	a5,a5,0x10
+80001860:	0107d793          	srli	a5,a5,0x10
+80001864:	00078593          	mv	a1,a5
+80001868:	00070513          	mv	a0,a4
+8000186c:	891ff0ef          	jal	ra,800010fc <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:124
+            break;
+80001870:	09c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            
+        case GPIO_APB_8_BITS_BUS:
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+80001874:	fec42783          	lw	a5,-20(s0)
+80001878:	0007a783          	lw	a5,0(a5)
+8000187c:	0a078793          	addi	a5,a5,160
+80001880:	fe842703          	lw	a4,-24(s0)
+80001884:	0ff77713          	andi	a4,a4,255
+80001888:	00070593          	mv	a1,a4
+8000188c:	00078513          	mv	a0,a5
+80001890:	8b5ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+80001894:	fec42783          	lw	a5,-20(s0)
+80001898:	0007a783          	lw	a5,0(a5)
+8000189c:	0a478713          	addi	a4,a5,164
+800018a0:	fe842783          	lw	a5,-24(s0)
+800018a4:	0087d793          	srli	a5,a5,0x8
+800018a8:	0ff7f793          	andi	a5,a5,255
+800018ac:	00078593          	mv	a1,a5
+800018b0:	00070513          	mv	a0,a4
+800018b4:	891ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+800018b8:	fec42783          	lw	a5,-20(s0)
+800018bc:	0007a783          	lw	a5,0(a5)
+800018c0:	0a878713          	addi	a4,a5,168
+800018c4:	fe842783          	lw	a5,-24(s0)
+800018c8:	0107d793          	srli	a5,a5,0x10
+800018cc:	0ff7f793          	andi	a5,a5,255
+800018d0:	00078593          	mv	a1,a5
+800018d4:	00070513          	mv	a0,a4
+800018d8:	86dff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+800018dc:	fec42783          	lw	a5,-20(s0)
+800018e0:	0007a783          	lw	a5,0(a5)
+800018e4:	0ac78713          	addi	a4,a5,172
+800018e8:	fe842783          	lw	a5,-24(s0)
+800018ec:	0187d793          	srli	a5,a5,0x18
+800018f0:	0ff7f793          	andi	a5,a5,255
+800018f4:	00078593          	mv	a1,a5
+800018f8:	00070513          	mv	a0,a4
+800018fc:	849ff0ef          	jal	ra,80001144 <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:131
+            break;
+80001900:	00c0006f          	j	8000190c <GPIO_set_outputs+0x138>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:134 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001904:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:135 (discriminator 1)
+            break;
+80001908:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145
+     * the expected value may indicate that some of the GPIOs may not exist due to
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+8000190c:	fec42503          	lw	a0,-20(s0)
+80001910:	028000ef          	jal	ra,80001938 <GPIO_get_outputs>
+80001914:	00050713          	mv	a4,a0
+80001918:	fe842783          	lw	a5,-24(s0)
+8000191c:	00e78463          	beq	a5,a4,80001924 <GPIO_set_outputs+0x150>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:145 (discriminator 1)
+80001920:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80001924:	00000013          	nop
+80001928:	01c12083          	lw	ra,28(sp)
+8000192c:	01812403          	lw	s0,24(sp)
+80001930:	02010113          	addi	sp,sp,32
+80001934:	00008067          	ret
+
+80001938 <GPIO_get_outputs>:
+GPIO_get_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:193
+ */
+uint32_t GPIO_get_outputs
+(
+    gpio_instance_t *   this_gpio
+)
+{
+80001938:	fd010113          	addi	sp,sp,-48
+8000193c:	02112623          	sw	ra,44(sp)
+80001940:	02812423          	sw	s0,40(sp)
+80001944:	03010413          	addi	s0,sp,48
+80001948:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:194
+    uint32_t gpio_out = 0;
+8000194c:	fe042623          	sw	zero,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:196
+    
+    switch( this_gpio->apb_bus_width )
+80001950:	fdc42783          	lw	a5,-36(s0)
+80001954:	0047a783          	lw	a5,4(a5)
+80001958:	00100713          	li	a4,1
+8000195c:	02e78663          	beq	a5,a4,80001988 <GPIO_get_outputs+0x50>
+80001960:	08078063          	beqz	a5,800019e0 <GPIO_get_outputs+0xa8>
+80001964:	00200713          	li	a4,2
+80001968:	12e79463          	bne	a5,a4,80001a90 <GPIO_get_outputs+0x158>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:199
+    {
+        case GPIO_APB_32_BITS_BUS:
+            gpio_out = HAL_get_32bit_reg( this_gpio->base_addr, GPIO_OUT );
+8000196c:	fdc42783          	lw	a5,-36(s0)
+80001970:	0007a783          	lw	a5,0(a5)
+80001974:	0a078793          	addi	a5,a5,160
+80001978:	00078513          	mv	a0,a5
+8000197c:	f40ff0ef          	jal	ra,800010bc <HW_get_32bit_reg>
+80001980:	fea42623          	sw	a0,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:200
+            break;
+80001984:	1140006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:203
+            
+        case GPIO_APB_16_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+80001988:	fdc42783          	lw	a5,-36(s0)
+8000198c:	0007a783          	lw	a5,0(a5)
+80001990:	0a078793          	addi	a5,a5,160
+80001994:	00078513          	mv	a0,a5
+80001998:	f6cff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+8000199c:	00050793          	mv	a5,a0
+800019a0:	00078713          	mv	a4,a5
+800019a4:	fec42783          	lw	a5,-20(s0)
+800019a8:	00e7e7b3          	or	a5,a5,a4
+800019ac:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:204
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 16);
+800019b0:	fdc42783          	lw	a5,-36(s0)
+800019b4:	0007a783          	lw	a5,0(a5)
+800019b8:	0a478793          	addi	a5,a5,164
+800019bc:	00078513          	mv	a0,a5
+800019c0:	f44ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019c4:	00050793          	mv	a5,a0
+800019c8:	01079793          	slli	a5,a5,0x10
+800019cc:	00078713          	mv	a4,a5
+800019d0:	fec42783          	lw	a5,-20(s0)
+800019d4:	00e7e7b3          	or	a5,a5,a4
+800019d8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:205
+            break;
+800019dc:	0bc0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:208
+            
+        case GPIO_APB_8_BITS_BUS:
+            gpio_out |= HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT0 );
+800019e0:	fdc42783          	lw	a5,-36(s0)
+800019e4:	0007a783          	lw	a5,0(a5)
+800019e8:	0a078793          	addi	a5,a5,160
+800019ec:	00078513          	mv	a0,a5
+800019f0:	f14ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+800019f4:	00050793          	mv	a5,a0
+800019f8:	00078713          	mv	a4,a5
+800019fc:	fec42783          	lw	a5,-20(s0)
+80001a00:	00e7e7b3          	or	a5,a5,a4
+80001a04:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:209
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT1 ) << 8);
+80001a08:	fdc42783          	lw	a5,-36(s0)
+80001a0c:	0007a783          	lw	a5,0(a5)
+80001a10:	0a478793          	addi	a5,a5,164
+80001a14:	00078513          	mv	a0,a5
+80001a18:	eecff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a1c:	00050793          	mv	a5,a0
+80001a20:	00879793          	slli	a5,a5,0x8
+80001a24:	00078713          	mv	a4,a5
+80001a28:	fec42783          	lw	a5,-20(s0)
+80001a2c:	00e7e7b3          	or	a5,a5,a4
+80001a30:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:210
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT2 ) << 16);
+80001a34:	fdc42783          	lw	a5,-36(s0)
+80001a38:	0007a783          	lw	a5,0(a5)
+80001a3c:	0a878793          	addi	a5,a5,168
+80001a40:	00078513          	mv	a0,a5
+80001a44:	ec0ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a48:	00050793          	mv	a5,a0
+80001a4c:	01079793          	slli	a5,a5,0x10
+80001a50:	00078713          	mv	a4,a5
+80001a54:	fec42783          	lw	a5,-20(s0)
+80001a58:	00e7e7b3          	or	a5,a5,a4
+80001a5c:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:211
+            gpio_out |= (HAL_get_16bit_reg( this_gpio->base_addr, GPIO_OUT3 ) << 24);
+80001a60:	fdc42783          	lw	a5,-36(s0)
+80001a64:	0007a783          	lw	a5,0(a5)
+80001a68:	0ac78793          	addi	a5,a5,172
+80001a6c:	00078513          	mv	a0,a5
+80001a70:	e94ff0ef          	jal	ra,80001104 <HW_get_16bit_reg>
+80001a74:	00050793          	mv	a5,a0
+80001a78:	01879793          	slli	a5,a5,0x18
+80001a7c:	00078713          	mv	a4,a5
+80001a80:	fec42783          	lw	a5,-20(s0)
+80001a84:	00e7e7b3          	or	a5,a5,a4
+80001a88:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:212
+            break;
+80001a8c:	00c0006f          	j	80001a98 <GPIO_get_outputs+0x160>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:215 (discriminator 1)
+            
+        default:
+            HAL_ASSERT(0);
+80001a90:	00100073          	ebreak
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:216 (discriminator 1)
+            break;
+80001a94:	00000013          	nop
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:219
+    }
+    
+    return gpio_out;
+80001a98:	fec42783          	lw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:220
+}
+80001a9c:	00078513          	mv	a0,a5
+80001aa0:	02c12083          	lw	ra,44(sp)
+80001aa4:	02812403          	lw	s0,40(sp)
+80001aa8:	03010113          	addi	sp,sp,48
+80001aac:	00008067          	ret
+
+80001ab0 <MRV_enable_local_irq>:
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:586
+{
+80001ab0:	fd010113          	addi	sp,sp,-48
+80001ab4:	02812623          	sw	s0,44(sp)
+80001ab8:	03010413          	addi	s0,sp,48
+80001abc:	fca42e23          	sw	a0,-36(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80001ac0:	fdc42783          	lw	a5,-36(s0)
+80001ac4:	3047a7f3          	csrrs	a5,mie,a5
+80001ac8:	fef42623          	sw	a5,-20(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\src\platform/miv_rv32_hal/miv_rv32_hal.h:588
+}
+80001acc:	00000013          	nop
+80001ad0:	02c12403          	lw	s0,44(sp)
+80001ad4:	03010113          	addi	sp,sp,48
+80001ad8:	00008067          	ret
+
+80001adc <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:48
+/*--------------------------------------------------------------------------------------------------
+ * Interrupt handler for the MIV_RV32 MSYS_EI interrupt connected to CoreTimer 0
+ */
+uint8_t
+MSYS_EI0_IRQHandler(void)
+{
+80001adc:	ff010113          	addi	sp,sp,-16
+80001ae0:	00112623          	sw	ra,12(sp)
+80001ae4:	00812423          	sw	s0,8(sp)
+80001ae8:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:61
+     */
+
+    /* LEDs 1 - 4 are connected to GPIO pins 0 - 3.
+     * Invert the state of GPIO pins 0 - 3 every time the interrupt is triggered
+     */
+    gpio_pins_state = gpio_pins_state ^ (GPIO_0_MASK | GPIO_1_MASK | GPIO_2_MASK | GPIO_3_MASK);
+80001aec:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001af0:	0007a783          	lw	a5,0(a5)
+80001af4:	00f7c713          	xori	a4,a5,15
+80001af8:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001afc:	00e7a023          	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:63
+
+    GPIO_set_outputs(&g_gpio, gpio_pins_state);
+80001b00:	8d818793          	addi	a5,gp,-1832 # 80001cd8 <gpio_pins_state>
+80001b04:	0007a783          	lw	a5,0(a5)
+80001b08:	00078593          	mv	a1,a5
+80001b0c:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b10:	cc5ff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:66
+
+    /* Clear the interrupt within the timer */
+    TMR_clear_int(&g_core_timer_0);
+80001b14:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001b18:	af5ff0ef          	jal	ra,8000160c <TMR_clear_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:67
+    return (EXT_IRQ_KEEP_ENABLED);
+80001b1c:	00000793          	li	a5,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:68
+}
+80001b20:	00078513          	mv	a0,a5
+80001b24:	00c12083          	lw	ra,12(sp)
+80001b28:	00812403          	lw	s0,8(sp)
+80001b2c:	01010113          	addi	sp,sp,16
+80001b30:	00008067          	ret
+
+80001b34 <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:72
+
+int
+main(void)
+{
+80001b34:	ff010113          	addi	sp,sp,-16
+80001b38:	00112623          	sw	ra,12(sp)
+80001b3c:	00812423          	sw	s0,8(sp)
+80001b40:	01010413          	addi	s0,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:74
+    /* Initialise the UART and print the greeting message*/
+    UART_init(&g_core_uart_0, COREUARTAPB0_BASE_ADDR, BAUD_VALUE_115200, DATA_8_BITS | NO_PARITY);
+80001b44:	00100693          	li	a3,1
+80001b48:	01a00613          	li	a2,26
+80001b4c:	710005b7          	lui	a1,0x71000
+80001b50:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b54:	e38ff0ef          	jal	ra,8000118c <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:76
+
+    UART_polled_tx_string(&g_core_uart_0, g_message);
+80001b58:	00000597          	auipc	a1,0x0
+80001b5c:	0a858593          	addi	a1,a1,168 # 80001c00 <__data_load>
+80001b60:	8ec18513          	addi	a0,gp,-1812 # 80001cec <g_core_uart_0>
+80001b64:	801ff0ef          	jal	ra,80001364 <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:79
+
+    /* Enable local interrupt for the MSYS_EI interrupt pin */
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn);
+80001b68:	01000537          	lui	a0,0x1000
+80001b6c:	f45ff0ef          	jal	ra,80001ab0 <MRV_enable_local_irq>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:82
+
+    /* Initialise the GPIO */
+    GPIO_init(&g_gpio, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+80001b70:	00200613          	li	a2,2
+80001b74:	750005b7          	lui	a1,0x75000
+80001b78:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b7c:	ae5ff0ef          	jal	ra,80001660 <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:85
+
+    /* Configure the GPIOs, turn them all off initially */
+    GPIO_set_outputs(&g_gpio, 0x00u);
+80001b80:	00000593          	li	a1,0
+80001b84:	8e018513          	addi	a0,gp,-1824 # 80001ce0 <__sbss_end>
+80001b88:	c4dff0ef          	jal	ra,800017d4 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:88
+
+    /* Initialise and configure the timer */
+    TMR_init(&g_core_timer_0,
+80001b8c:	000147b7          	lui	a5,0x14
+80001b90:	c9a78713          	addi	a4,a5,-870 # 13c9a <RAM_SIZE+0xbc9a>
+80001b94:	00900693          	li	a3,9
+80001b98:	00000613          	li	a2,0
+80001b9c:	730005b7          	lui	a1,0x73000
+80001ba0:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001ba4:	889ff0ef          	jal	ra,8000142c <TMR_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:95
+             TMR_CONTINUOUS_MODE,
+             PRESCALER_DIV_1024,
+             TIMER_LOAD_VALUE);
+
+    /* Enable interrupts in general.*/
+    HAL_enable_interrupts();
+80001ba8:	ce4ff0ef          	jal	ra,8000108c <HAL_enable_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:98
+
+    /* Enable the timer to generate interrupts */
+    TMR_enable_int(&g_core_timer_0);
+80001bac:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb0:	a01ff0ef          	jal	ra,800015b0 <TMR_enable_int>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:101
+
+    /* Start the timer */
+    TMR_start(&g_core_timer_0);
+80001bb4:	8e818513          	addi	a0,gp,-1816 # 80001ce8 <g_core_timer_0>
+80001bb8:	99dff0ef          	jal	ra,80001554 <TMR_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32-coretimer-timer_interrupt\miv-rv32-imc-debug/../src/application/main.c:103 (discriminator 1)
+
+    while (1u)
+80001bbc:	0000006f          	j	80001bbc <main+0x88>
+
+80001bc0 <local_irq_handler_table>:
+80001bc0:	80000f24 80000f08 80000f40 80001038     $.......@...8...
+80001bd0:	80000fe8 80000fe8 80000fe8 80000fe8     ................
+80001be0:	80001adc 80000f5c 80000f78 80000f94     ....\...x.......
+80001bf0:	80000fb0 80000fcc 80001000 8000101c     ................
diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.hex b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.hex
index 3d00050..40f9a4d 100644
--- a/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.hex
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.hex
@@ -1,391 +1,525 @@
-:100000006F00101E6F00C00800000000000000001C
-:100010006F00401100000000000000000000000020
-:100020006F00001900000000000000000000000048
-:100030006F00C02000000000000000000000000071
-:10004000000000006F0040286F00C030000000007A
-:100050000000000000000000000000006F0010071A
-:100060006F00806C6F00C0376F0040406F00C04869
-:100070006F0040516F00C0596F0040626F00807385
-:100080006F00007C1300000013000000130000004C
-:10009000130101F823201100232011002322210045
-:1000A000232431002326410023285100232A610004
-:1000B000232C7100232E8100232091022322A102F0
-:1000C0002324B1022326C1022328D102232AE102DC
-:1000D000232CF102232E01032320110523222105C5
-:1000E000232431052326410523285105232A6105B0
-:1000F000232C7105232E8105232091072322A1079C
-:100100002324B1072326C1072328D107232AE10787
-:10011000232CF10773252034F3251034EF00903E93
-:100120006F009003130101F8232011002320110018
-:1001300023222100232431002326410023285100BB
-:10014000232A6100232C7100232E81002320910299
-:100150002322A1022324B1022326C1022328D10293
-:10016000232AE102232CF102232E0103232011056F
-:100170002322210523243105232641052328510567
-:10018000232A6105232C7105232E81052320910745
-:100190002322A1072324B1072326C1072328D1073F
-:1001A000232AE107232CF107EF0010316F00C07AFA
-:1001B000130101F823201100232011002322210024
-:1001C000232431002326410023285100232A6100E3
-:1001D000232C7100232E8100232091022322A102CF
-:1001E0002324B1022326C1022328D102232AE102BB
-:1001F000232CF102232E01032320110523222105A4
-:10020000232431052326410523285105232A61058E
-:10021000232C7105232E8105232091072322A1077A
-:100220002324B1072326C1072328D107232AE10766
-:10023000232CF107EF00D01B6F000072130101F8AF
-:100240002320110023201100232221002324310028
-:100250002326410023285100232A6100232C71000A
-:10026000232E8100232091022322A1022324B10204
-:100270002326C1022328D102232AE102232CF102E2
-:10028000232E0103232011052322210523243105D8
-:100290002326410523285105232A6105232C7105B6
-:1002A000232E8105232091072322A1072324B107B0
-:1002B0002326C1072328D107232AE107232CF1078E
-:1002C000EF00502C6F004069130101F8232011004A
-:1002D0002320110023222100232431002326410062
-:1002E00023285100232A6100232C7100232E810032
-:1002F000232091022322A1022324B1022326C1023A
-:100300002328D102232AE102232CF102232E010308
-:10031000232011052322210523243105232641050D
-:1003200023285105232A6105232C7105232E8105DD
-:10033000232091072322A1072324B1072326C107E5
-:100340002328D107232AE107232CF107EF001024EB
-:100350006F008060130101F8232011002320110099
-:100360002322210023243100232641002328510089
-:10037000232A6100232C7100232E81002320910267
-:100380002322A1022324B1022326C1022328D10261
-:10039000232AE102232CF102232E0103232011053D
-:1003A0002322210523243105232641052328510535
-:1003B000232A6105232C7105232E81052320910713
-:1003C0002322A1072324B1072326C1072328D1070D
-:1003D000232AE107232CF107EF00101B6F00C05701
-:1003E000130101F8232011002320110023222100F2
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diff --git a/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.lst b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.lst
new file mode 100644
index 0000000..758e7b6
--- /dev/null
+++ b/Libero_Projects/import/software_example/MIV_RV32/CFG3/hex/miv-rv32i-systick-blinky.lst
@@ -0,0 +1,5195 @@
+
+miv-rv32i-systick-blinky.elf:     file format elf32-littleriscv
+miv-rv32i-systick-blinky.elf
+architecture: riscv:rv32, flags 0x00000112:
+EXEC_P, HAS_SYMS, D_PAGED
+start address 0x80000000
+
+Program Header:
+    LOAD off    0x00001000 vaddr 0x80000000 paddr 0x80000000 align 2**12
+         filesz 0x00002034 memsz 0x00002034 flags r-x
+    LOAD off    0x00004000 vaddr 0x80004000 paddr 0x80002040 align 2**12
+         filesz 0x00000070 memsz 0x000000a0 flags rw-
+    LOAD off    0x000040a0 vaddr 0x800040a0 paddr 0x800020b0 align 2**12
+         filesz 0x00000000 memsz 0x00000060 flags rw-
+    LOAD off    0x00004100 vaddr 0x80004100 paddr 0x800020b0 align 2**12
+         filesz 0x00000000 memsz 0x00000400 flags rw-
+
+Sections:
+Idx Name                       Size      VMA       LMA       File off  Algn  Flags
+  0 .entry                     00000560  80000000  80000000  00001000  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  1 .text                      00001ad0  80000560  80000560  00001560  2**4  CONTENTS, ALLOC, LOAD, READONLY, CODE
+  2 .sdata2._global_impure_ptr 00000004  80002030  80002030  00003030  2**2  CONTENTS, ALLOC, LOAD, READONLY, DATA
+  3 .sdata                     00000010  80004000  80002040  00004000  2**4  CONTENTS, ALLOC, LOAD, DATA
+  4 .data                      00000060  80004010  80002050  00004010  2**4  CONTENTS, ALLOC, LOAD, DATA
+  5 .sbss                      00000030  80004070  800020b0  00004070  2**4  ALLOC
+  6 .bss                       00000060  800040a0  800020b0  000040a0  2**4  ALLOC
+  7 .heap                      00000000  80004100  80004100  00004070  2**4  CONTENTS
+  8 .stack                     00000400  80004100  800020b0  00004100  2**4  ALLOC
+  9 .riscv.attributes          00000026  00000000  00000000  00004070  2**0  CONTENTS, READONLY
+ 10 .comment                   00000051  00000000  00000000  00004096  2**0  CONTENTS, READONLY
+ 11 .debug_line                000034f7  00000000  00000000  000040e7  2**0  CONTENTS, READONLY, DEBUGGING
+ 12 .debug_info                00003c3c  00000000  00000000  000075de  2**0  CONTENTS, READONLY, DEBUGGING
+ 13 .debug_abbrev              00001098  00000000  00000000  0000b21a  2**0  CONTENTS, READONLY, DEBUGGING
+ 14 .debug_aranges             000002b0  00000000  00000000  0000c2b8  2**3  CONTENTS, READONLY, DEBUGGING
+ 15 .debug_str                 00001394  00000000  00000000  0000c568  2**0  CONTENTS, READONLY, DEBUGGING
+ 16 .debug_ranges              00000310  00000000  00000000  0000d900  2**3  CONTENTS, READONLY, DEBUGGING
+ 17 .debug_loc                 00001863  00000000  00000000  0000dc10  2**0  CONTENTS, READONLY, DEBUGGING
+ 18 .debug_frame               000010b8  00000000  00000000  0000f474  2**2  CONTENTS, READONLY, DEBUGGING
+SYMBOL TABLE:
+80000000 l    d  .entry	00000000 .entry
+80000560 l    d  .text	00000000 .text
+80002030 l    d  .sdata2._global_impure_ptr	00000000 .sdata2._global_impure_ptr
+80004000 l    d  .sdata	00000000 .sdata
+80004010 l    d  .data	00000000 .data
+80004070 l    d  .sbss	00000000 .sbss
+800040a0 l    d  .bss	00000000 .bss
+80004100 l    d  .heap	00000000 .heap
+80004100 l    d  .stack	00000000 .stack
+00000000 l    d  .riscv.attributes	00000000 .riscv.attributes
+00000000 l    d  .comment	00000000 .comment
+00000000 l    d  .debug_line	00000000 .debug_line
+00000000 l    d  .debug_info	00000000 .debug_info
+00000000 l    d  .debug_abbrev	00000000 .debug_abbrev
+00000000 l    d  .debug_aranges	00000000 .debug_aranges
+00000000 l    d  .debug_str	00000000 .debug_str
+00000000 l    d  .debug_ranges	00000000 .debug_ranges
+00000000 l    d  .debug_loc	00000000 .debug_loc
+00000000 l    d  .debug_frame	00000000 .debug_frame
+00000000 l    df *ABS*	00000000 ./src/platform/miv_rv32_hal/miv_rv32_entry.o
+80000560 l       .text	00000000 handle_reset
+80000004 l       .entry	00000000 trap_entry
+80000090 l       .entry	00000000 generic_trap_handler
+80000010 l       .entry	00000000 sw_trap_entry
+800000e0 l       .entry	00000000 vector_sw_trap_handler
+80000020 l       .entry	00000000 tmr_trap_entry
+80000128 l       .entry	00000000 vector_tmr_trap_handler
+80000030 l       .entry	00000000 ext_trap_entry
+80000170 l       .entry	00000000 vector_ext_trap_handler
+80000044 l       .entry	00000000 MGEUI_trap_entry
+800001b8 l       .entry	00000000 vector_MGEUI_trap_handler
+80000048 l       .entry	00000000 MGECI_trap_entry
+80000200 l       .entry	00000000 vector_MGECI_trap_handler
+8000005c l       .entry	00000000 MSYS_MIE22_trap_entry
+800004d0 l       .entry	00000000 vector_SUBSYSR_IRQHandler
+80000060 l       .entry	00000000 MSYS_MIE23_trap_entry
+800003f8 l       .entry	00000000 vector_SUBSYS_IRQHandler
+80000064 l       .entry	00000000 MSYS_MIE24_trap_entry
+80000248 l       .entry	00000000 vector_MSYS_EI0_trap_handler
+80000068 l       .entry	00000000 MSYS_MIE25_trap_entry
+80000290 l       .entry	00000000 vector_MSYS_EI1_trap_handler
+8000006c l       .entry	00000000 MSYS_MIE26_trap_entry
+800002d8 l       .entry	00000000 vector_MSYS_EI2_trap_handler
+80000070 l       .entry	00000000 MSYS_MIE27_trap_entry
+80000320 l       .entry	00000000 vector_MSYS_EI3_trap_handler
+80000074 l       .entry	00000000 MSYS_MIE28_trap_entry
+80000368 l       .entry	00000000 vector_MSYS_EI4_trap_handler
+80000078 l       .entry	00000000 MSYS_MIE29_trap_entry
+800003b0 l       .entry	00000000 vector_MSYS_EI5_trap_handler
+8000007c l       .entry	00000000 MSYS_MIE30_trap_entry
+80000440 l       .entry	00000000 vector_MSYS_EI6_trap_handler
+80000080 l       .entry	00000000 MSYS_MIE31_trap_entry
+80000488 l       .entry	00000000 vector_MSYS_EI7_trap_handler
+80000518 l       .entry	00000000 generic_restore
+800005ac l       .text	00000000 ima_cores_setup
+800005f2 l       .text	00000000 vector_address_not_matching
+800005b8 l       .text	00000000 generic_reset_handling
+8000065a l       .text	00000000 block_copy
+800005f4 l       .text	00000000 initializations
+8000063e l       .text	00000000 zeroize_block
+8000067c l       .text	00000000 block_copy_error
+8000064e l       .text	00000000 zeroize_loop
+8000066a l       .text	00000000 block_copy_loop
+8000067e l       .text	00000000 block_copy_exit
+00000000 l    df *ABS*	00000000 miv_rv32_hal.c
+80000680 l     F .text	0000002a MRV_read_mtime
+80004070 l     O .sbss	00000008 g_systick_cmp_value
+80004078 l     O .sbss	00000008 g_systick_increment
+00000000 l    df *ABS*	00000000 miv_rv32_init.c
+00000000 l    df *ABS*	00000000 miv_rv32_stubs.c
+80000830 l     F .text	00000008 Software_IRQHandler.localalias.0
+00000000 l    df *ABS*	00000000 miv_rv32_syscall.c
+80004000 l     O .sdata	00000004 curbrk.2478
+00000000 l    df *ABS*	00000000 hal_irq.c
+00000000 l    df *ABS*	00000000 core_uart_apb.c
+00000000 l    df *ABS*	00000000 core_gpio.c
+00000000 l    df *ABS*	00000000 main.c
+80004084 l     O .sbss	00000004 interrupt_counter.2878
+80004088 l     O .sbss	00000004 val.2879
+00000000 l    df *ABS*	00000000 printf.c
+00000000 l    df *ABS*	00000000 sysisatty.c
+00000000 l    df *ABS*	00000000 writer.c
+00000000 l    df *ABS*	00000000 findfp.c
+80000cfc l     F .text	00000068 std
+00000000 l    df *ABS*	00000000 fwalk.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 nano-vfprintf.c
+80000ffa l     F .text	00000028 __sfputc_r
+00000000 l    df *ABS*	00000000 nano-vfprintf_i.c
+00000000 l    df *ABS*	00000000 sbrkr.c
+00000000 l    df *ABS*	00000000 stdio.c
+00000000 l    df *ABS*	00000000 wbuf.c
+00000000 l    df *ABS*	00000000 wsetup.c
+00000000 l    df *ABS*	00000000 closer.c
+00000000 l    df *ABS*	00000000 fflush.c
+00000000 l    df *ABS*	00000000 lseekr.c
+00000000 l    df *ABS*	00000000 makebuf.c
+00000000 l    df *ABS*	00000000 memchr.c
+00000000 l    df *ABS*	00000000 mlock.c
+00000000 l    df *ABS*	00000000 nano-mallocr.c
+00000000 l    df *ABS*	00000000 readr.c
+00000000 l    df *ABS*	00000000 fstatr.c
+00000000 l    df *ABS*	00000000 isattyr.c
+00000000 l    df *ABS*	00000000 impure.c
+80004010 l     O .data	00000060 impure_data
+00000000 l    df *ABS*	00000000 reent.c
+80001d82 g     F .text	0000002a _isatty_r
+80001b42 g     F .text	0000002e _lseek_r
+00000400 g       *ABS*	00000000 STACK_SIZE
+80000c8c g     F .text	00000042 printf
+80004800 g       .sdata	00000000 __global_pointer$
+800009d0 g     F .text	0000006e UART_get_rx
+80001758 g     F .text	00000036 __sseek
+80000db2 g     F .text	0000006a __sinit
+80001794 g     F .text	000000c2 __swbuf_r
+80000d6e g     F .text	00000044 __sfmoreglue
+80001c82 g     F .text	00000002 __malloc_unlock
+80002050 g       *ABS*	00000000 __data_load
+80000bc6 g     F .text	00000036 SysTick_Handler
+80004004 g     O .sdata	00000004 g_hello_msg
+8000095a g       .text	00000000 HW_get_8bit_reg_field
+80004070 g       .sbss	00000000 __sbss_start
+800040a0 g     O .bss	00000040 g_rx_buff
+800007cc g     F .text	0000001c handle_local_ei_interrupts
+80001d56 g     F .text	0000002c _fstat_r
+800040f0 g     O .bss	00000004 errno
+800008be g       .text	00000000 HW_set_32bit_reg
+800040e0 g     O .bss	00000008 g_gpio_out
+80000d64 g     F .text	0000000a _cleanup_r
+80004000 g       .sdata	00000000 __sdata_start
+80000848  w    F .text	00000002 MSYS_EI4_IRQHandler
+800040e8 g     O .bss	00000008 g_uart
+80000938 g       .text	00000000 HW_set_8bit_reg_field
+8000083e  w    F .text	00000002 SUBSYS_IRQHandler
+80000cce g     F .text	00000002 isatty
+8000088c g     F .text	0000001c _fstat
+800007e8 g     F .text	00000044 handle_trap
+8000084e  w    F .text	00000002 MSYS_EI6_IRQHandler
+800016ae g     F .text	0000002a _sbrk_r
+80000852  w    F .text	00000002 SUBSYSR_IRQHandler
+80001d28 g     F .text	0000002e _read_r
+800006aa g     F .text	0000009c MRV_systick_config
+8000083a  w    F .text	00000002 MGECI_IRQHandler
+80004100 g       .heap	00000000 _heap_end
+80001db0 g     O .text	00000040 local_irq_handler_table
+80000850  w    F .text	00000002 MSYS_EI7_IRQHandler
+80000882 g     F .text	00000006 _isatty
+80002030 g     O .sdata2._global_impure_ptr	00000004 _global_impure_ptr
+80004100 g       .bss	00000000 __bss_end
+80000856 g     F .text	0000002c _sbrk
+8000082c g     F .text	00000002 _init
+8000092c g       .text	00000000 HW_set_8bit_reg
+80000932 g       .text	00000000 HW_get_8bit_reg
+80000842  w    F .text	00000002 MSYS_EI1_IRQHandler
+800040a0 g       .sbss	00000000 __sbss_end
+800008c6 g       .text	00000000 HW_set_32bit_reg_field
+80004500 g       .stack	00000000 __stack_top
+80001f8c g     O .text	00000020 __sf_fake_stderr
+80000a3e g     F .text	00000038 UART_polled_tx_string
+00000000 g       *ABS*	00000000 HEAP_SIZE
+80001022 g     F .text	00000042 __sfputs_r
+80001c66 g     F .text	0000001a memchr
+80001c84 g     F .text	000000a4 _free_r
+80000b26 g     F .text	00000096 GPIO_set_outputs
+80000000 g       .entry	00000000 _start
+800008a8 g     F .text	00000008 _lseek
+80000746 g     F .text	00000072 handle_m_timer_interrupt
+80002040 g       *ABS*	00000000 __sdata_load
+80004070 g       .data	00000000 __data_end
+800008e8 g       .text	00000000 HW_get_32bit_reg_field
+80001968 g     F .text	0000002a _close_r
+80000a76 g     F .text	000000b0 GPIO_init
+80001856 g     F .text	00000112 __swsetup_r
+80000e1c g     F .text	0000009e __sfp
+800016d8 g     F .text	00000030 __sread
+80001c80 g     F .text	00000002 __malloc_lock
+80001adc g     F .text	00000066 _fflush_r
+80001fac g     O .text	00000020 __sf_fake_stdin
+800040a0 g       .bss	00000000 __bss_start
+800008b8 g     F .text	00000006 HAL_enable_interrupts
+80000c7c g     F .text	00000010 memset
+80000bfc g     F .text	00000080 main
+8000084a  w    F .text	00000002 MSYS_EI5_IRQHandler
+8000178e g     F .text	00000006 __sclose
+80000f26 g     F .text	000000d4 _malloc_r
+8000083c  w    F .text	00000002 MGEUI_IRQHandler
+800008f8 g       .text	00000000 HW_get_16bit_reg
+80004010 g       .sdata	00000000 __sdata_end
+80004100 g       .heap	00000000 __heap_end
+80004080 g     O .sbss	00000001 g_rx_size
+8000082e g     F .text	00000002 _fini
+80000c8c g     F .text	00000042 iprintf
+80000cd0 g     F .text	0000002c _write_r
+800008fe g       .text	00000000 HW_set_16bit_reg_field
+80000844  w    F .text	00000002 MSYS_EI2_IRQHandler
+80001300 g     F .text	0000010c _printf_common
+80004008 g     O .sdata	00000004 _impure_ptr
+80004100 g       .stack	00000000 __stack_bottom
+80001992 g     F .text	0000014a __sflush_r
+80000bbc g     F .text	0000000a Software_IRQHandler
+80004100 g       .heap	00000000 __heap_start
+80001b70 g     F .text	00000058 __swhatbuf_r
+800008b4 g     F .text	00000004 _write
+80004100 g       .bss	00000000 _end
+8000084c  w    F .text	00000002 Reserved_IRQHandler
+80001708 g     F .text	00000050 __swrite
+80001064 g     F .text	0000029c _vfiprintf_r
+80000eba g     F .text	0000006c _fwalk_reent
+80000966 g     F .text	0000006a UART_init
+80001fcc g     O .text	00000020 __sf_fake_stdout
+800008c2 g       .text	00000000 HW_get_32bit_reg
+800008b0 g     F .text	00000004 _read
+80000854 g     F .text	00000002 _exit
+800008f2 g       .text	00000000 HW_set_16bit_reg
+80001bc8 g     F .text	0000009e __smakebuf_r
+8000140c g     F .text	000002a2 _printf_i
+80000846  w    F .text	00000002 MSYS_EI3_IRQHandler
+80004090 g     O .sbss	00000004 __malloc_sbrk_start
+80000838  w    F .text	00000002 External_IRQHandler
+80004010 g       .data	00000000 __data_start
+8000408c g     O .sbss	00000004 __malloc_free_list
+80001064 g     F .text	0000029c _vfprintf_r
+800007b8 g     F .text	00000014 handle_m_soft_interrupt
+80000920 g       .text	00000000 HW_get_16bit_reg_field
+80000888 g     F .text	00000004 _close
+80000840  w    F .text	00000002 MSYS_EI0_IRQHandler
+
+
+
+Disassembly of section .entry:
+
+80000000 <_start>:
+_start():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:114
+
+  .section      .entry, "ax"
+  .globl _start
+
+_start:
+  j handle_reset
+80000000:	5600006f          	j	80000560 <handle_reset>
+
+80000004 <trap_entry>:
+trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:125
+   at the jump and you can at least look at mcause, mepc and get some hints
+   about the crash. */
+trap_entry:
+.option push
+.option norvc
+j generic_trap_handler
+80000004:	08c0006f          	j	80000090 <generic_trap_handler>
+	...
+
+80000010 <sw_trap_entry>:
+sw_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:131
+.option pop
+  .word 0
+  .word 0
+
+sw_trap_entry:
+  j vector_sw_trap_handler
+80000010:	a8c1                	j	800000e0 <vector_sw_trap_handler>
+	...
+
+80000020 <tmr_trap_entry>:
+tmr_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:140
+  .word 0
+  .word 0
+  .word 0
+
+tmr_trap_entry:
+  j vector_tmr_trap_handler
+80000020:	a221                	j	80000128 <vector_tmr_trap_handler>
+	...
+
+80000030 <ext_trap_entry>:
+ext_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:149
+  .word 0
+  .word 0
+  .word 0
+
+ext_trap_entry:
+  j vector_ext_trap_handler
+80000030:	a281                	j	80000170 <vector_ext_trap_handler>
+	...
+
+80000044 <MGEUI_trap_entry>:
+MGEUI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:160
+  .word 0
+  .word 0
+
+#ifndef MIV_LEGACY_RV32
+MGEUI_trap_entry:
+  j vector_MGEUI_trap_handler
+80000044:	aa95                	j	800001b8 <vector_MGEUI_trap_handler>
+	...
+
+80000048 <MGECI_trap_entry>:
+MGECI_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:166
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MGECI_trap_entry:
+  j vector_MGECI_trap_handler
+80000048:	aa65                	j	80000200 <vector_MGECI_trap_handler>
+	...
+
+8000005c <MSYS_MIE22_trap_entry>:
+MSYS_MIE22_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:178
+  .word 0
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE22_trap_entry:
+#ifndef MIV_RV32_V3_0 
+  j vector_SUBSYSR_IRQHandler
+8000005c:	a995                	j	800004d0 <vector_SUBSYSR_IRQHandler>
+	...
+
+80000060 <MSYS_MIE23_trap_entry>:
+MSYS_MIE23_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:185
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE23_trap_entry:
+  j vector_SUBSYS_IRQHandler
+80000060:	ae61                	j	800003f8 <vector_SUBSYS_IRQHandler>
+	...
+
+80000064 <MSYS_MIE24_trap_entry>:
+MSYS_MIE24_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:192
+  .2byte 0
+#endif
+#endif /*MIV_RV32_V3_0*/
+
+MSYS_MIE24_trap_entry:
+  j vector_MSYS_EI0_trap_handler
+80000064:	a2d5                	j	80000248 <vector_MSYS_EI0_trap_handler>
+	...
+
+80000068 <MSYS_MIE25_trap_entry>:
+MSYS_MIE25_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:198
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE25_trap_entry:
+  j vector_MSYS_EI1_trap_handler
+80000068:	a425                	j	80000290 <vector_MSYS_EI1_trap_handler>
+	...
+
+8000006c <MSYS_MIE26_trap_entry>:
+MSYS_MIE26_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:204
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE26_trap_entry:
+  j vector_MSYS_EI2_trap_handler
+8000006c:	a4b5                	j	800002d8 <vector_MSYS_EI2_trap_handler>
+	...
+
+80000070 <MSYS_MIE27_trap_entry>:
+MSYS_MIE27_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:210
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE27_trap_entry:
+  j vector_MSYS_EI3_trap_handler
+80000070:	ac45                	j	80000320 <vector_MSYS_EI3_trap_handler>
+	...
+
+80000074 <MSYS_MIE28_trap_entry>:
+MSYS_MIE28_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:216
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE28_trap_entry:
+  j vector_MSYS_EI4_trap_handler
+80000074:	acd5                	j	80000368 <vector_MSYS_EI4_trap_handler>
+	...
+
+80000078 <MSYS_MIE29_trap_entry>:
+MSYS_MIE29_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:222
+#ifdef __riscv_compressed
+  .2byte 0
+#endif
+
+MSYS_MIE29_trap_entry:
+  j vector_MSYS_EI5_trap_handler
+80000078:	ae25                	j	800003b0 <vector_MSYS_EI5_trap_handler>
+	...
+
+8000007c <MSYS_MIE30_trap_entry>:
+MSYS_MIE30_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:229
+  .2byte 0
+#endif
+
+MSYS_MIE30_trap_entry:
+#ifndef MIV_RV32_V3_0
+  j vector_MSYS_EI6_trap_handler
+8000007c:	a6d1                	j	80000440 <vector_MSYS_EI6_trap_handler>
+	...
+
+80000080 <MSYS_MIE31_trap_entry>:
+MSYS_MIE31_trap_entry():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:239
+  .2byte 0
+#endif
+
+#ifndef MIV_RV32_V3_0
+MSYS_MIE31_trap_entry:
+  j vector_MSYS_EI7_trap_handler
+80000080:	a121                	j	80000488 <vector_MSYS_EI7_trap_handler>
+80000082:	0000                	unimp
+80000084:	00000013          	nop
+80000088:	00000013          	nop
+8000008c:	00000013          	nop
+
+80000090 <generic_trap_handler>:
+generic_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:248
+#endif /* MIV_RV32_V3_0 */
+#endif /* MIV_LEGACY_RV32 */
+
+.align 4
+generic_trap_handler:
+  STORE_CONTEXT
+80000090:	7119                	addi	sp,sp,-128
+80000092:	c006                	sw	ra,0(sp)
+80000094:	c006                	sw	ra,0(sp)
+80000096:	c20a                	sw	sp,4(sp)
+80000098:	c40e                	sw	gp,8(sp)
+8000009a:	c612                	sw	tp,12(sp)
+8000009c:	c816                	sw	t0,16(sp)
+8000009e:	ca1a                	sw	t1,20(sp)
+800000a0:	cc1e                	sw	t2,24(sp)
+800000a2:	ce22                	sw	s0,28(sp)
+800000a4:	d026                	sw	s1,32(sp)
+800000a6:	d22a                	sw	a0,36(sp)
+800000a8:	d42e                	sw	a1,40(sp)
+800000aa:	d632                	sw	a2,44(sp)
+800000ac:	d836                	sw	a3,48(sp)
+800000ae:	da3a                	sw	a4,52(sp)
+800000b0:	dc3e                	sw	a5,56(sp)
+800000b2:	de42                	sw	a6,60(sp)
+800000b4:	c0c6                	sw	a7,64(sp)
+800000b6:	c2ca                	sw	s2,68(sp)
+800000b8:	c4ce                	sw	s3,72(sp)
+800000ba:	c6d2                	sw	s4,76(sp)
+800000bc:	c8d6                	sw	s5,80(sp)
+800000be:	cada                	sw	s6,84(sp)
+800000c0:	ccde                	sw	s7,88(sp)
+800000c2:	cee2                	sw	s8,92(sp)
+800000c4:	d0e6                	sw	s9,96(sp)
+800000c6:	d2ea                	sw	s10,100(sp)
+800000c8:	d4ee                	sw	s11,104(sp)
+800000ca:	d6f2                	sw	t3,108(sp)
+800000cc:	d8f6                	sw	t4,112(sp)
+800000ce:	dafa                	sw	t5,116(sp)
+800000d0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:249
+  csrr a0, mcause
+800000d2:	34202573          	csrr	a0,mcause
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:250
+  csrr a1, mepc
+800000d6:	341025f3          	csrr	a1,mepc
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:251
+  jal handle_trap
+800000da:	70e000ef          	jal	ra,800007e8 <handle_trap>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:252
+  j generic_restore
+800000de:	a92d                	j	80000518 <generic_restore>
+
+800000e0 <vector_sw_trap_handler>:
+vector_sw_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:255
+
+vector_sw_trap_handler:
+  STORE_CONTEXT
+800000e0:	7119                	addi	sp,sp,-128
+800000e2:	c006                	sw	ra,0(sp)
+800000e4:	c006                	sw	ra,0(sp)
+800000e6:	c20a                	sw	sp,4(sp)
+800000e8:	c40e                	sw	gp,8(sp)
+800000ea:	c612                	sw	tp,12(sp)
+800000ec:	c816                	sw	t0,16(sp)
+800000ee:	ca1a                	sw	t1,20(sp)
+800000f0:	cc1e                	sw	t2,24(sp)
+800000f2:	ce22                	sw	s0,28(sp)
+800000f4:	d026                	sw	s1,32(sp)
+800000f6:	d22a                	sw	a0,36(sp)
+800000f8:	d42e                	sw	a1,40(sp)
+800000fa:	d632                	sw	a2,44(sp)
+800000fc:	d836                	sw	a3,48(sp)
+800000fe:	da3a                	sw	a4,52(sp)
+80000100:	dc3e                	sw	a5,56(sp)
+80000102:	de42                	sw	a6,60(sp)
+80000104:	c0c6                	sw	a7,64(sp)
+80000106:	c2ca                	sw	s2,68(sp)
+80000108:	c4ce                	sw	s3,72(sp)
+8000010a:	c6d2                	sw	s4,76(sp)
+8000010c:	c8d6                	sw	s5,80(sp)
+8000010e:	cada                	sw	s6,84(sp)
+80000110:	ccde                	sw	s7,88(sp)
+80000112:	cee2                	sw	s8,92(sp)
+80000114:	d0e6                	sw	s9,96(sp)
+80000116:	d2ea                	sw	s10,100(sp)
+80000118:	d4ee                	sw	s11,104(sp)
+8000011a:	d6f2                	sw	t3,108(sp)
+8000011c:	d8f6                	sw	t4,112(sp)
+8000011e:	dafa                	sw	t5,116(sp)
+80000120:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:256
+  jal handle_m_soft_interrupt
+80000122:	696000ef          	jal	ra,800007b8 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:257
+  j generic_restore
+80000126:	aecd                	j	80000518 <generic_restore>
+
+80000128 <vector_tmr_trap_handler>:
+vector_tmr_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:260
+
+vector_tmr_trap_handler:
+  STORE_CONTEXT
+80000128:	7119                	addi	sp,sp,-128
+8000012a:	c006                	sw	ra,0(sp)
+8000012c:	c006                	sw	ra,0(sp)
+8000012e:	c20a                	sw	sp,4(sp)
+80000130:	c40e                	sw	gp,8(sp)
+80000132:	c612                	sw	tp,12(sp)
+80000134:	c816                	sw	t0,16(sp)
+80000136:	ca1a                	sw	t1,20(sp)
+80000138:	cc1e                	sw	t2,24(sp)
+8000013a:	ce22                	sw	s0,28(sp)
+8000013c:	d026                	sw	s1,32(sp)
+8000013e:	d22a                	sw	a0,36(sp)
+80000140:	d42e                	sw	a1,40(sp)
+80000142:	d632                	sw	a2,44(sp)
+80000144:	d836                	sw	a3,48(sp)
+80000146:	da3a                	sw	a4,52(sp)
+80000148:	dc3e                	sw	a5,56(sp)
+8000014a:	de42                	sw	a6,60(sp)
+8000014c:	c0c6                	sw	a7,64(sp)
+8000014e:	c2ca                	sw	s2,68(sp)
+80000150:	c4ce                	sw	s3,72(sp)
+80000152:	c6d2                	sw	s4,76(sp)
+80000154:	c8d6                	sw	s5,80(sp)
+80000156:	cada                	sw	s6,84(sp)
+80000158:	ccde                	sw	s7,88(sp)
+8000015a:	cee2                	sw	s8,92(sp)
+8000015c:	d0e6                	sw	s9,96(sp)
+8000015e:	d2ea                	sw	s10,100(sp)
+80000160:	d4ee                	sw	s11,104(sp)
+80000162:	d6f2                	sw	t3,108(sp)
+80000164:	d8f6                	sw	t4,112(sp)
+80000166:	dafa                	sw	t5,116(sp)
+80000168:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:261
+  jal handle_m_timer_interrupt
+8000016a:	5dc000ef          	jal	ra,80000746 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:262
+  j generic_restore
+8000016e:	a66d                	j	80000518 <generic_restore>
+
+80000170 <vector_ext_trap_handler>:
+vector_ext_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:265
+
+vector_ext_trap_handler:
+  STORE_CONTEXT
+80000170:	7119                	addi	sp,sp,-128
+80000172:	c006                	sw	ra,0(sp)
+80000174:	c006                	sw	ra,0(sp)
+80000176:	c20a                	sw	sp,4(sp)
+80000178:	c40e                	sw	gp,8(sp)
+8000017a:	c612                	sw	tp,12(sp)
+8000017c:	c816                	sw	t0,16(sp)
+8000017e:	ca1a                	sw	t1,20(sp)
+80000180:	cc1e                	sw	t2,24(sp)
+80000182:	ce22                	sw	s0,28(sp)
+80000184:	d026                	sw	s1,32(sp)
+80000186:	d22a                	sw	a0,36(sp)
+80000188:	d42e                	sw	a1,40(sp)
+8000018a:	d632                	sw	a2,44(sp)
+8000018c:	d836                	sw	a3,48(sp)
+8000018e:	da3a                	sw	a4,52(sp)
+80000190:	dc3e                	sw	a5,56(sp)
+80000192:	de42                	sw	a6,60(sp)
+80000194:	c0c6                	sw	a7,64(sp)
+80000196:	c2ca                	sw	s2,68(sp)
+80000198:	c4ce                	sw	s3,72(sp)
+8000019a:	c6d2                	sw	s4,76(sp)
+8000019c:	c8d6                	sw	s5,80(sp)
+8000019e:	cada                	sw	s6,84(sp)
+800001a0:	ccde                	sw	s7,88(sp)
+800001a2:	cee2                	sw	s8,92(sp)
+800001a4:	d0e6                	sw	s9,96(sp)
+800001a6:	d2ea                	sw	s10,100(sp)
+800001a8:	d4ee                	sw	s11,104(sp)
+800001aa:	d6f2                	sw	t3,108(sp)
+800001ac:	d8f6                	sw	t4,112(sp)
+800001ae:	dafa                	sw	t5,116(sp)
+800001b0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:269
+#ifdef MIV_LEGACY_RV32
+  jal handle_m_ext_interrupt
+#else
+  jal External_IRQHandler
+800001b2:	686000ef          	jal	ra,80000838 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:271
+#endif /* MIV_LEGACY_RV32 */
+  j generic_restore
+800001b6:	a68d                	j	80000518 <generic_restore>
+
+800001b8 <vector_MGEUI_trap_handler>:
+vector_MGEUI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:275
+
+#ifndef MIV_LEGACY_RV32
+vector_MGEUI_trap_handler:
+  STORE_CONTEXT
+800001b8:	7119                	addi	sp,sp,-128
+800001ba:	c006                	sw	ra,0(sp)
+800001bc:	c006                	sw	ra,0(sp)
+800001be:	c20a                	sw	sp,4(sp)
+800001c0:	c40e                	sw	gp,8(sp)
+800001c2:	c612                	sw	tp,12(sp)
+800001c4:	c816                	sw	t0,16(sp)
+800001c6:	ca1a                	sw	t1,20(sp)
+800001c8:	cc1e                	sw	t2,24(sp)
+800001ca:	ce22                	sw	s0,28(sp)
+800001cc:	d026                	sw	s1,32(sp)
+800001ce:	d22a                	sw	a0,36(sp)
+800001d0:	d42e                	sw	a1,40(sp)
+800001d2:	d632                	sw	a2,44(sp)
+800001d4:	d836                	sw	a3,48(sp)
+800001d6:	da3a                	sw	a4,52(sp)
+800001d8:	dc3e                	sw	a5,56(sp)
+800001da:	de42                	sw	a6,60(sp)
+800001dc:	c0c6                	sw	a7,64(sp)
+800001de:	c2ca                	sw	s2,68(sp)
+800001e0:	c4ce                	sw	s3,72(sp)
+800001e2:	c6d2                	sw	s4,76(sp)
+800001e4:	c8d6                	sw	s5,80(sp)
+800001e6:	cada                	sw	s6,84(sp)
+800001e8:	ccde                	sw	s7,88(sp)
+800001ea:	cee2                	sw	s8,92(sp)
+800001ec:	d0e6                	sw	s9,96(sp)
+800001ee:	d2ea                	sw	s10,100(sp)
+800001f0:	d4ee                	sw	s11,104(sp)
+800001f2:	d6f2                	sw	t3,108(sp)
+800001f4:	d8f6                	sw	t4,112(sp)
+800001f6:	dafa                	sw	t5,116(sp)
+800001f8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:276
+  jal MGEUI_IRQHandler
+800001fa:	642000ef          	jal	ra,8000083c <MGEUI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:277
+  j generic_restore
+800001fe:	ae29                	j	80000518 <generic_restore>
+
+80000200 <vector_MGECI_trap_handler>:
+vector_MGECI_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:280
+
+vector_MGECI_trap_handler:
+  STORE_CONTEXT
+80000200:	7119                	addi	sp,sp,-128
+80000202:	c006                	sw	ra,0(sp)
+80000204:	c006                	sw	ra,0(sp)
+80000206:	c20a                	sw	sp,4(sp)
+80000208:	c40e                	sw	gp,8(sp)
+8000020a:	c612                	sw	tp,12(sp)
+8000020c:	c816                	sw	t0,16(sp)
+8000020e:	ca1a                	sw	t1,20(sp)
+80000210:	cc1e                	sw	t2,24(sp)
+80000212:	ce22                	sw	s0,28(sp)
+80000214:	d026                	sw	s1,32(sp)
+80000216:	d22a                	sw	a0,36(sp)
+80000218:	d42e                	sw	a1,40(sp)
+8000021a:	d632                	sw	a2,44(sp)
+8000021c:	d836                	sw	a3,48(sp)
+8000021e:	da3a                	sw	a4,52(sp)
+80000220:	dc3e                	sw	a5,56(sp)
+80000222:	de42                	sw	a6,60(sp)
+80000224:	c0c6                	sw	a7,64(sp)
+80000226:	c2ca                	sw	s2,68(sp)
+80000228:	c4ce                	sw	s3,72(sp)
+8000022a:	c6d2                	sw	s4,76(sp)
+8000022c:	c8d6                	sw	s5,80(sp)
+8000022e:	cada                	sw	s6,84(sp)
+80000230:	ccde                	sw	s7,88(sp)
+80000232:	cee2                	sw	s8,92(sp)
+80000234:	d0e6                	sw	s9,96(sp)
+80000236:	d2ea                	sw	s10,100(sp)
+80000238:	d4ee                	sw	s11,104(sp)
+8000023a:	d6f2                	sw	t3,108(sp)
+8000023c:	d8f6                	sw	t4,112(sp)
+8000023e:	dafa                	sw	t5,116(sp)
+80000240:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:281
+  jal MGECI_IRQHandler
+80000242:	5f8000ef          	jal	ra,8000083a <MGECI_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:282
+  j generic_restore
+80000246:	acc9                	j	80000518 <generic_restore>
+
+80000248 <vector_MSYS_EI0_trap_handler>:
+vector_MSYS_EI0_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:285
+
+vector_MSYS_EI0_trap_handler:
+  STORE_CONTEXT
+80000248:	7119                	addi	sp,sp,-128
+8000024a:	c006                	sw	ra,0(sp)
+8000024c:	c006                	sw	ra,0(sp)
+8000024e:	c20a                	sw	sp,4(sp)
+80000250:	c40e                	sw	gp,8(sp)
+80000252:	c612                	sw	tp,12(sp)
+80000254:	c816                	sw	t0,16(sp)
+80000256:	ca1a                	sw	t1,20(sp)
+80000258:	cc1e                	sw	t2,24(sp)
+8000025a:	ce22                	sw	s0,28(sp)
+8000025c:	d026                	sw	s1,32(sp)
+8000025e:	d22a                	sw	a0,36(sp)
+80000260:	d42e                	sw	a1,40(sp)
+80000262:	d632                	sw	a2,44(sp)
+80000264:	d836                	sw	a3,48(sp)
+80000266:	da3a                	sw	a4,52(sp)
+80000268:	dc3e                	sw	a5,56(sp)
+8000026a:	de42                	sw	a6,60(sp)
+8000026c:	c0c6                	sw	a7,64(sp)
+8000026e:	c2ca                	sw	s2,68(sp)
+80000270:	c4ce                	sw	s3,72(sp)
+80000272:	c6d2                	sw	s4,76(sp)
+80000274:	c8d6                	sw	s5,80(sp)
+80000276:	cada                	sw	s6,84(sp)
+80000278:	ccde                	sw	s7,88(sp)
+8000027a:	cee2                	sw	s8,92(sp)
+8000027c:	d0e6                	sw	s9,96(sp)
+8000027e:	d2ea                	sw	s10,100(sp)
+80000280:	d4ee                	sw	s11,104(sp)
+80000282:	d6f2                	sw	t3,108(sp)
+80000284:	d8f6                	sw	t4,112(sp)
+80000286:	dafa                	sw	t5,116(sp)
+80000288:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:286
+  jal MSYS_EI0_IRQHandler
+8000028a:	5b6000ef          	jal	ra,80000840 <MSYS_EI0_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:287
+  j generic_restore
+8000028e:	a469                	j	80000518 <generic_restore>
+
+80000290 <vector_MSYS_EI1_trap_handler>:
+vector_MSYS_EI1_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:290
+
+vector_MSYS_EI1_trap_handler:
+  STORE_CONTEXT
+80000290:	7119                	addi	sp,sp,-128
+80000292:	c006                	sw	ra,0(sp)
+80000294:	c006                	sw	ra,0(sp)
+80000296:	c20a                	sw	sp,4(sp)
+80000298:	c40e                	sw	gp,8(sp)
+8000029a:	c612                	sw	tp,12(sp)
+8000029c:	c816                	sw	t0,16(sp)
+8000029e:	ca1a                	sw	t1,20(sp)
+800002a0:	cc1e                	sw	t2,24(sp)
+800002a2:	ce22                	sw	s0,28(sp)
+800002a4:	d026                	sw	s1,32(sp)
+800002a6:	d22a                	sw	a0,36(sp)
+800002a8:	d42e                	sw	a1,40(sp)
+800002aa:	d632                	sw	a2,44(sp)
+800002ac:	d836                	sw	a3,48(sp)
+800002ae:	da3a                	sw	a4,52(sp)
+800002b0:	dc3e                	sw	a5,56(sp)
+800002b2:	de42                	sw	a6,60(sp)
+800002b4:	c0c6                	sw	a7,64(sp)
+800002b6:	c2ca                	sw	s2,68(sp)
+800002b8:	c4ce                	sw	s3,72(sp)
+800002ba:	c6d2                	sw	s4,76(sp)
+800002bc:	c8d6                	sw	s5,80(sp)
+800002be:	cada                	sw	s6,84(sp)
+800002c0:	ccde                	sw	s7,88(sp)
+800002c2:	cee2                	sw	s8,92(sp)
+800002c4:	d0e6                	sw	s9,96(sp)
+800002c6:	d2ea                	sw	s10,100(sp)
+800002c8:	d4ee                	sw	s11,104(sp)
+800002ca:	d6f2                	sw	t3,108(sp)
+800002cc:	d8f6                	sw	t4,112(sp)
+800002ce:	dafa                	sw	t5,116(sp)
+800002d0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:291
+  jal MSYS_EI1_IRQHandler
+800002d2:	570000ef          	jal	ra,80000842 <MSYS_EI1_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:292
+  j generic_restore
+800002d6:	a489                	j	80000518 <generic_restore>
+
+800002d8 <vector_MSYS_EI2_trap_handler>:
+vector_MSYS_EI2_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:295
+
+vector_MSYS_EI2_trap_handler:
+  STORE_CONTEXT
+800002d8:	7119                	addi	sp,sp,-128
+800002da:	c006                	sw	ra,0(sp)
+800002dc:	c006                	sw	ra,0(sp)
+800002de:	c20a                	sw	sp,4(sp)
+800002e0:	c40e                	sw	gp,8(sp)
+800002e2:	c612                	sw	tp,12(sp)
+800002e4:	c816                	sw	t0,16(sp)
+800002e6:	ca1a                	sw	t1,20(sp)
+800002e8:	cc1e                	sw	t2,24(sp)
+800002ea:	ce22                	sw	s0,28(sp)
+800002ec:	d026                	sw	s1,32(sp)
+800002ee:	d22a                	sw	a0,36(sp)
+800002f0:	d42e                	sw	a1,40(sp)
+800002f2:	d632                	sw	a2,44(sp)
+800002f4:	d836                	sw	a3,48(sp)
+800002f6:	da3a                	sw	a4,52(sp)
+800002f8:	dc3e                	sw	a5,56(sp)
+800002fa:	de42                	sw	a6,60(sp)
+800002fc:	c0c6                	sw	a7,64(sp)
+800002fe:	c2ca                	sw	s2,68(sp)
+80000300:	c4ce                	sw	s3,72(sp)
+80000302:	c6d2                	sw	s4,76(sp)
+80000304:	c8d6                	sw	s5,80(sp)
+80000306:	cada                	sw	s6,84(sp)
+80000308:	ccde                	sw	s7,88(sp)
+8000030a:	cee2                	sw	s8,92(sp)
+8000030c:	d0e6                	sw	s9,96(sp)
+8000030e:	d2ea                	sw	s10,100(sp)
+80000310:	d4ee                	sw	s11,104(sp)
+80000312:	d6f2                	sw	t3,108(sp)
+80000314:	d8f6                	sw	t4,112(sp)
+80000316:	dafa                	sw	t5,116(sp)
+80000318:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:296
+  jal MSYS_EI2_IRQHandler
+8000031a:	52a000ef          	jal	ra,80000844 <MSYS_EI2_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:297
+  j generic_restore
+8000031e:	aaed                	j	80000518 <generic_restore>
+
+80000320 <vector_MSYS_EI3_trap_handler>:
+vector_MSYS_EI3_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:300
+
+vector_MSYS_EI3_trap_handler:
+  STORE_CONTEXT
+80000320:	7119                	addi	sp,sp,-128
+80000322:	c006                	sw	ra,0(sp)
+80000324:	c006                	sw	ra,0(sp)
+80000326:	c20a                	sw	sp,4(sp)
+80000328:	c40e                	sw	gp,8(sp)
+8000032a:	c612                	sw	tp,12(sp)
+8000032c:	c816                	sw	t0,16(sp)
+8000032e:	ca1a                	sw	t1,20(sp)
+80000330:	cc1e                	sw	t2,24(sp)
+80000332:	ce22                	sw	s0,28(sp)
+80000334:	d026                	sw	s1,32(sp)
+80000336:	d22a                	sw	a0,36(sp)
+80000338:	d42e                	sw	a1,40(sp)
+8000033a:	d632                	sw	a2,44(sp)
+8000033c:	d836                	sw	a3,48(sp)
+8000033e:	da3a                	sw	a4,52(sp)
+80000340:	dc3e                	sw	a5,56(sp)
+80000342:	de42                	sw	a6,60(sp)
+80000344:	c0c6                	sw	a7,64(sp)
+80000346:	c2ca                	sw	s2,68(sp)
+80000348:	c4ce                	sw	s3,72(sp)
+8000034a:	c6d2                	sw	s4,76(sp)
+8000034c:	c8d6                	sw	s5,80(sp)
+8000034e:	cada                	sw	s6,84(sp)
+80000350:	ccde                	sw	s7,88(sp)
+80000352:	cee2                	sw	s8,92(sp)
+80000354:	d0e6                	sw	s9,96(sp)
+80000356:	d2ea                	sw	s10,100(sp)
+80000358:	d4ee                	sw	s11,104(sp)
+8000035a:	d6f2                	sw	t3,108(sp)
+8000035c:	d8f6                	sw	t4,112(sp)
+8000035e:	dafa                	sw	t5,116(sp)
+80000360:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:301
+  jal MSYS_EI3_IRQHandler
+80000362:	4e4000ef          	jal	ra,80000846 <MSYS_EI3_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:302
+  j generic_restore
+80000366:	aa4d                	j	80000518 <generic_restore>
+
+80000368 <vector_MSYS_EI4_trap_handler>:
+vector_MSYS_EI4_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:305
+
+vector_MSYS_EI4_trap_handler:
+  STORE_CONTEXT
+80000368:	7119                	addi	sp,sp,-128
+8000036a:	c006                	sw	ra,0(sp)
+8000036c:	c006                	sw	ra,0(sp)
+8000036e:	c20a                	sw	sp,4(sp)
+80000370:	c40e                	sw	gp,8(sp)
+80000372:	c612                	sw	tp,12(sp)
+80000374:	c816                	sw	t0,16(sp)
+80000376:	ca1a                	sw	t1,20(sp)
+80000378:	cc1e                	sw	t2,24(sp)
+8000037a:	ce22                	sw	s0,28(sp)
+8000037c:	d026                	sw	s1,32(sp)
+8000037e:	d22a                	sw	a0,36(sp)
+80000380:	d42e                	sw	a1,40(sp)
+80000382:	d632                	sw	a2,44(sp)
+80000384:	d836                	sw	a3,48(sp)
+80000386:	da3a                	sw	a4,52(sp)
+80000388:	dc3e                	sw	a5,56(sp)
+8000038a:	de42                	sw	a6,60(sp)
+8000038c:	c0c6                	sw	a7,64(sp)
+8000038e:	c2ca                	sw	s2,68(sp)
+80000390:	c4ce                	sw	s3,72(sp)
+80000392:	c6d2                	sw	s4,76(sp)
+80000394:	c8d6                	sw	s5,80(sp)
+80000396:	cada                	sw	s6,84(sp)
+80000398:	ccde                	sw	s7,88(sp)
+8000039a:	cee2                	sw	s8,92(sp)
+8000039c:	d0e6                	sw	s9,96(sp)
+8000039e:	d2ea                	sw	s10,100(sp)
+800003a0:	d4ee                	sw	s11,104(sp)
+800003a2:	d6f2                	sw	t3,108(sp)
+800003a4:	d8f6                	sw	t4,112(sp)
+800003a6:	dafa                	sw	t5,116(sp)
+800003a8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:306
+  jal MSYS_EI4_IRQHandler
+800003aa:	49e000ef          	jal	ra,80000848 <MSYS_EI4_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:307
+  j generic_restore
+800003ae:	a2ad                	j	80000518 <generic_restore>
+
+800003b0 <vector_MSYS_EI5_trap_handler>:
+vector_MSYS_EI5_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:310
+
+vector_MSYS_EI5_trap_handler:
+  STORE_CONTEXT
+800003b0:	7119                	addi	sp,sp,-128
+800003b2:	c006                	sw	ra,0(sp)
+800003b4:	c006                	sw	ra,0(sp)
+800003b6:	c20a                	sw	sp,4(sp)
+800003b8:	c40e                	sw	gp,8(sp)
+800003ba:	c612                	sw	tp,12(sp)
+800003bc:	c816                	sw	t0,16(sp)
+800003be:	ca1a                	sw	t1,20(sp)
+800003c0:	cc1e                	sw	t2,24(sp)
+800003c2:	ce22                	sw	s0,28(sp)
+800003c4:	d026                	sw	s1,32(sp)
+800003c6:	d22a                	sw	a0,36(sp)
+800003c8:	d42e                	sw	a1,40(sp)
+800003ca:	d632                	sw	a2,44(sp)
+800003cc:	d836                	sw	a3,48(sp)
+800003ce:	da3a                	sw	a4,52(sp)
+800003d0:	dc3e                	sw	a5,56(sp)
+800003d2:	de42                	sw	a6,60(sp)
+800003d4:	c0c6                	sw	a7,64(sp)
+800003d6:	c2ca                	sw	s2,68(sp)
+800003d8:	c4ce                	sw	s3,72(sp)
+800003da:	c6d2                	sw	s4,76(sp)
+800003dc:	c8d6                	sw	s5,80(sp)
+800003de:	cada                	sw	s6,84(sp)
+800003e0:	ccde                	sw	s7,88(sp)
+800003e2:	cee2                	sw	s8,92(sp)
+800003e4:	d0e6                	sw	s9,96(sp)
+800003e6:	d2ea                	sw	s10,100(sp)
+800003e8:	d4ee                	sw	s11,104(sp)
+800003ea:	d6f2                	sw	t3,108(sp)
+800003ec:	d8f6                	sw	t4,112(sp)
+800003ee:	dafa                	sw	t5,116(sp)
+800003f0:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:311
+  jal MSYS_EI5_IRQHandler
+800003f2:	458000ef          	jal	ra,8000084a <MSYS_EI5_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:312
+  j generic_restore
+800003f6:	a20d                	j	80000518 <generic_restore>
+
+800003f8 <vector_SUBSYS_IRQHandler>:
+vector_SUBSYS_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:315
+
+vector_SUBSYS_IRQHandler:
+  STORE_CONTEXT
+800003f8:	7119                	addi	sp,sp,-128
+800003fa:	c006                	sw	ra,0(sp)
+800003fc:	c006                	sw	ra,0(sp)
+800003fe:	c20a                	sw	sp,4(sp)
+80000400:	c40e                	sw	gp,8(sp)
+80000402:	c612                	sw	tp,12(sp)
+80000404:	c816                	sw	t0,16(sp)
+80000406:	ca1a                	sw	t1,20(sp)
+80000408:	cc1e                	sw	t2,24(sp)
+8000040a:	ce22                	sw	s0,28(sp)
+8000040c:	d026                	sw	s1,32(sp)
+8000040e:	d22a                	sw	a0,36(sp)
+80000410:	d42e                	sw	a1,40(sp)
+80000412:	d632                	sw	a2,44(sp)
+80000414:	d836                	sw	a3,48(sp)
+80000416:	da3a                	sw	a4,52(sp)
+80000418:	dc3e                	sw	a5,56(sp)
+8000041a:	de42                	sw	a6,60(sp)
+8000041c:	c0c6                	sw	a7,64(sp)
+8000041e:	c2ca                	sw	s2,68(sp)
+80000420:	c4ce                	sw	s3,72(sp)
+80000422:	c6d2                	sw	s4,76(sp)
+80000424:	c8d6                	sw	s5,80(sp)
+80000426:	cada                	sw	s6,84(sp)
+80000428:	ccde                	sw	s7,88(sp)
+8000042a:	cee2                	sw	s8,92(sp)
+8000042c:	d0e6                	sw	s9,96(sp)
+8000042e:	d2ea                	sw	s10,100(sp)
+80000430:	d4ee                	sw	s11,104(sp)
+80000432:	d6f2                	sw	t3,108(sp)
+80000434:	d8f6                	sw	t4,112(sp)
+80000436:	dafa                	sw	t5,116(sp)
+80000438:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:316
+  jal SUBSYS_IRQHandler
+8000043a:	404000ef          	jal	ra,8000083e <SUBSYS_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:317
+  j generic_restore
+8000043e:	a8e9                	j	80000518 <generic_restore>
+
+80000440 <vector_MSYS_EI6_trap_handler>:
+vector_MSYS_EI6_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:321
+
+#ifndef MIV_RV32_V3_0
+vector_MSYS_EI6_trap_handler:
+  STORE_CONTEXT
+80000440:	7119                	addi	sp,sp,-128
+80000442:	c006                	sw	ra,0(sp)
+80000444:	c006                	sw	ra,0(sp)
+80000446:	c20a                	sw	sp,4(sp)
+80000448:	c40e                	sw	gp,8(sp)
+8000044a:	c612                	sw	tp,12(sp)
+8000044c:	c816                	sw	t0,16(sp)
+8000044e:	ca1a                	sw	t1,20(sp)
+80000450:	cc1e                	sw	t2,24(sp)
+80000452:	ce22                	sw	s0,28(sp)
+80000454:	d026                	sw	s1,32(sp)
+80000456:	d22a                	sw	a0,36(sp)
+80000458:	d42e                	sw	a1,40(sp)
+8000045a:	d632                	sw	a2,44(sp)
+8000045c:	d836                	sw	a3,48(sp)
+8000045e:	da3a                	sw	a4,52(sp)
+80000460:	dc3e                	sw	a5,56(sp)
+80000462:	de42                	sw	a6,60(sp)
+80000464:	c0c6                	sw	a7,64(sp)
+80000466:	c2ca                	sw	s2,68(sp)
+80000468:	c4ce                	sw	s3,72(sp)
+8000046a:	c6d2                	sw	s4,76(sp)
+8000046c:	c8d6                	sw	s5,80(sp)
+8000046e:	cada                	sw	s6,84(sp)
+80000470:	ccde                	sw	s7,88(sp)
+80000472:	cee2                	sw	s8,92(sp)
+80000474:	d0e6                	sw	s9,96(sp)
+80000476:	d2ea                	sw	s10,100(sp)
+80000478:	d4ee                	sw	s11,104(sp)
+8000047a:	d6f2                	sw	t3,108(sp)
+8000047c:	d8f6                	sw	t4,112(sp)
+8000047e:	dafa                	sw	t5,116(sp)
+80000480:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:322
+  jal MSYS_EI6_IRQHandler
+80000482:	3cc000ef          	jal	ra,8000084e <MSYS_EI6_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:323
+  j generic_restore
+80000486:	a849                	j	80000518 <generic_restore>
+
+80000488 <vector_MSYS_EI7_trap_handler>:
+vector_MSYS_EI7_trap_handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:326
+
+vector_MSYS_EI7_trap_handler:
+  STORE_CONTEXT
+80000488:	7119                	addi	sp,sp,-128
+8000048a:	c006                	sw	ra,0(sp)
+8000048c:	c006                	sw	ra,0(sp)
+8000048e:	c20a                	sw	sp,4(sp)
+80000490:	c40e                	sw	gp,8(sp)
+80000492:	c612                	sw	tp,12(sp)
+80000494:	c816                	sw	t0,16(sp)
+80000496:	ca1a                	sw	t1,20(sp)
+80000498:	cc1e                	sw	t2,24(sp)
+8000049a:	ce22                	sw	s0,28(sp)
+8000049c:	d026                	sw	s1,32(sp)
+8000049e:	d22a                	sw	a0,36(sp)
+800004a0:	d42e                	sw	a1,40(sp)
+800004a2:	d632                	sw	a2,44(sp)
+800004a4:	d836                	sw	a3,48(sp)
+800004a6:	da3a                	sw	a4,52(sp)
+800004a8:	dc3e                	sw	a5,56(sp)
+800004aa:	de42                	sw	a6,60(sp)
+800004ac:	c0c6                	sw	a7,64(sp)
+800004ae:	c2ca                	sw	s2,68(sp)
+800004b0:	c4ce                	sw	s3,72(sp)
+800004b2:	c6d2                	sw	s4,76(sp)
+800004b4:	c8d6                	sw	s5,80(sp)
+800004b6:	cada                	sw	s6,84(sp)
+800004b8:	ccde                	sw	s7,88(sp)
+800004ba:	cee2                	sw	s8,92(sp)
+800004bc:	d0e6                	sw	s9,96(sp)
+800004be:	d2ea                	sw	s10,100(sp)
+800004c0:	d4ee                	sw	s11,104(sp)
+800004c2:	d6f2                	sw	t3,108(sp)
+800004c4:	d8f6                	sw	t4,112(sp)
+800004c6:	dafa                	sw	t5,116(sp)
+800004c8:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:327
+  jal MSYS_EI7_IRQHandler
+800004ca:	386000ef          	jal	ra,80000850 <MSYS_EI7_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:328
+  j generic_restore
+800004ce:	a0a9                	j	80000518 <generic_restore>
+
+800004d0 <vector_SUBSYSR_IRQHandler>:
+vector_SUBSYSR_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:332
+
+
+vector_SUBSYSR_IRQHandler:
+  STORE_CONTEXT
+800004d0:	7119                	addi	sp,sp,-128
+800004d2:	c006                	sw	ra,0(sp)
+800004d4:	c006                	sw	ra,0(sp)
+800004d6:	c20a                	sw	sp,4(sp)
+800004d8:	c40e                	sw	gp,8(sp)
+800004da:	c612                	sw	tp,12(sp)
+800004dc:	c816                	sw	t0,16(sp)
+800004de:	ca1a                	sw	t1,20(sp)
+800004e0:	cc1e                	sw	t2,24(sp)
+800004e2:	ce22                	sw	s0,28(sp)
+800004e4:	d026                	sw	s1,32(sp)
+800004e6:	d22a                	sw	a0,36(sp)
+800004e8:	d42e                	sw	a1,40(sp)
+800004ea:	d632                	sw	a2,44(sp)
+800004ec:	d836                	sw	a3,48(sp)
+800004ee:	da3a                	sw	a4,52(sp)
+800004f0:	dc3e                	sw	a5,56(sp)
+800004f2:	de42                	sw	a6,60(sp)
+800004f4:	c0c6                	sw	a7,64(sp)
+800004f6:	c2ca                	sw	s2,68(sp)
+800004f8:	c4ce                	sw	s3,72(sp)
+800004fa:	c6d2                	sw	s4,76(sp)
+800004fc:	c8d6                	sw	s5,80(sp)
+800004fe:	cada                	sw	s6,84(sp)
+80000500:	ccde                	sw	s7,88(sp)
+80000502:	cee2                	sw	s8,92(sp)
+80000504:	d0e6                	sw	s9,96(sp)
+80000506:	d2ea                	sw	s10,100(sp)
+80000508:	d4ee                	sw	s11,104(sp)
+8000050a:	d6f2                	sw	t3,108(sp)
+8000050c:	d8f6                	sw	t4,112(sp)
+8000050e:	dafa                	sw	t5,116(sp)
+80000510:	dcfe                	sw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:333
+  jal SUBSYSR_IRQHandler
+80000512:	340000ef          	jal	ra,80000852 <SUBSYSR_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:334
+  j generic_restore
+80000516:	a009                	j	80000518 <generic_restore>
+
+80000518 <generic_restore>:
+generic_restore():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:340
+
+#endif /*MIV_RV32_V3_0*/
+#endif /* MIV_LEGACY_RV32 */
+
+generic_restore:
+  LREG x1, 0 * REGBYTES(sp)
+80000518:	4082                	lw	ra,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:341
+  LREG x2, 1 * REGBYTES(sp)
+8000051a:	4112                	lw	sp,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:342
+  LREG x3, 2 * REGBYTES(sp)
+8000051c:	41a2                	lw	gp,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:343
+  LREG x4, 3 * REGBYTES(sp)
+8000051e:	4232                	lw	tp,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:344
+  LREG x5, 4 * REGBYTES(sp)
+80000520:	42c2                	lw	t0,16(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:345
+  LREG x6, 5 * REGBYTES(sp)
+80000522:	4352                	lw	t1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:346
+  LREG x7, 6 * REGBYTES(sp)
+80000524:	43e2                	lw	t2,24(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:347
+  LREG x8, 7 * REGBYTES(sp)
+80000526:	4472                	lw	s0,28(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:348
+  LREG x9, 8 * REGBYTES(sp)
+80000528:	5482                	lw	s1,32(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:349
+  LREG x10, 9 * REGBYTES(sp)
+8000052a:	5512                	lw	a0,36(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:350
+  LREG x11, 10 * REGBYTES(sp)
+8000052c:	55a2                	lw	a1,40(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:351
+  LREG x12, 11 * REGBYTES(sp)
+8000052e:	5632                	lw	a2,44(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:352
+  LREG x13, 12 * REGBYTES(sp)
+80000530:	56c2                	lw	a3,48(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:353
+  LREG x14, 13 * REGBYTES(sp)
+80000532:	5752                	lw	a4,52(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:354
+  LREG x15, 14 * REGBYTES(sp)
+80000534:	57e2                	lw	a5,56(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:355
+  LREG x16, 15 * REGBYTES(sp)
+80000536:	5872                	lw	a6,60(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:356
+  LREG x17, 16 * REGBYTES(sp)
+80000538:	4886                	lw	a7,64(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:357
+  LREG x18, 17 * REGBYTES(sp)
+8000053a:	4916                	lw	s2,68(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:358
+  LREG x19, 18 * REGBYTES(sp)
+8000053c:	49a6                	lw	s3,72(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:359
+  LREG x20, 19 * REGBYTES(sp)
+8000053e:	4a36                	lw	s4,76(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:360
+  LREG x21, 20 * REGBYTES(sp)
+80000540:	4ac6                	lw	s5,80(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:361
+  LREG x22, 21 * REGBYTES(sp)
+80000542:	4b56                	lw	s6,84(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:362
+  LREG x23, 22 * REGBYTES(sp)
+80000544:	4be6                	lw	s7,88(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:363
+  LREG x24, 23 * REGBYTES(sp)
+80000546:	4c76                	lw	s8,92(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:364
+  LREG x25, 24 * REGBYTES(sp)
+80000548:	5c86                	lw	s9,96(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:365
+  LREG x26, 25 * REGBYTES(sp)
+8000054a:	5d16                	lw	s10,100(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:366
+  LREG x27, 26 * REGBYTES(sp)
+8000054c:	5da6                	lw	s11,104(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:367
+  LREG x28, 27 * REGBYTES(sp)
+8000054e:	5e36                	lw	t3,108(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:368
+  LREG x29, 28 * REGBYTES(sp)
+80000550:	5ec6                	lw	t4,112(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:369
+  LREG x30, 29 * REGBYTES(sp)
+80000552:	5f56                	lw	t5,116(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:370
+  LREG x31, 30 * REGBYTES(sp)
+80000554:	5fe6                	lw	t6,120(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:409
+  flw	f30, 30 * REGBYTES(sp)
+  flw	f31, 31 * REGBYTES(sp)
+  #endif /* __riscv_flen */
+  #endif /* MIV_FP_CONTEXT_SAVE */
+
+  addi sp, sp, SP_SHIFT_OFFSET*REGBYTES
+80000556:	6109                	addi	sp,sp,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:410
+  mret
+80000558:	30200073          	mret
+8000055c:	0000                	unimp
+	...
+
+Disassembly of section .text:
+
+80000560 <handle_reset>:
+handle_reset():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:419
+/* Ensure instructions are not relaxed, since gp is not yet set */
+.option push
+.option norelax
+
+#ifndef MIV_RV32_V3_0
+  csrwi mstatus, 0
+80000560:	30005073          	csrwi	mstatus,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:420
+  csrwi mie, 0
+80000564:	30405073          	csrwi	mie,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:421
+  la ra, _start
+80000568:	00000097          	auipc	ra,0x0
+8000056c:	a9808093          	addi	ra,ra,-1384 # 80000000 <_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:425
+
+/* Clearnig this to be on safer side as RTL doesnt seem to clear it on reset. */
+#ifndef MIV_LEGACY_RV32
+  li t0, MTIMEH_ADDR
+80000570:	0200c2b7          	lui	t0,0x200c
+80000574:	ffc28293          	addi	t0,t0,-4 # 200bffc <STACK_SIZE+0x200bbfc>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:426
+  sw x0, 0(t0)
+80000578:	0002a023          	sw	zero,0(t0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:429
+#endif
+
+  csrr t0, misa
+8000057c:	301022f3          	csrr	t0,misa
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:430
+  andi t0, t0, A_EXTENSION_MASK
+80000580:	0012f293          	andi	t0,t0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:431
+  bnez t0, ima_cores_setup          /* Jump to IMA core handling */
+80000584:	02029463          	bnez	t0,800005ac <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:439
+/* For MIV_RV32 cores the mtvec exception base address is fixed at Reset vector
+   address + 0x4. Check the mode bits. */
+/* In the MIV_RV32 v3.1, the MTVEC exception base address is WARL, and can be 
+   configured by the user at runtime */
+
+  csrr t0, mtvec
+80000588:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:440
+  andi t0, t0, MTVEC_MODE_BIT_MASK
+8000058c:	0032f293          	andi	t0,t0,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:441
+  li t1, MTVEC_VECTORED_MODE_VAL
+80000590:	4305                	li	t1,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:442
+  bne t0, t1, ima_cores_setup        /* Jump to IMA core handling */
+80000592:	00629d63          	bne	t0,t1,800005ac <ima_cores_setup>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:446
+
+  /* When mode = 1 => this is vectored mode on MIV_RV32 core.
+     Verify that the trap_handler address matches the configuration in MTVEC */
+  csrr t0, mtvec
+80000596:	305022f3          	csrr	t0,mtvec
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:447
+  andi t0, t0, 0xFFFFFFFC
+8000059a:	ffc2f293          	andi	t0,t0,-4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:448
+  la t1, trap_entry
+8000059e:	00000317          	auipc	t1,0x0
+800005a2:	a6630313          	addi	t1,t1,-1434 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:449
+  bne t0, t1, vector_address_not_matching
+800005a6:	04629663          	bne	t0,t1,800005f2 <vector_address_not_matching>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:450
+  j generic_reset_handling
+800005aa:	a039                	j	800005b8 <generic_reset_handling>
+
+800005ac <ima_cores_setup>:
+ima_cores_setup():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:477
+  bne t0, t1, vector_address_not_matching
+  j generic_reset_handling
+#endif /*MIV_RV32_V3_0*/
+
+ima_cores_setup:
+  la t0, trap_entry
+800005ac:	00000297          	auipc	t0,0x0
+800005b0:	a5828293          	addi	t0,t0,-1448 # 80000004 <trap_entry>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:483
+
+#ifdef MIV_LEGACY_RV32_VECTORED_INTERRUPTS
+  addi t0, t0, 0x01 /* Set the mode bit for IMA cores.
+                       For both MIV_RV32 v3.1 and v3.0 cores this is done by configurator. */
+#endif
+  csrw mtvec, t0
+800005b4:	30529073          	csrw	mtvec,t0
+
+800005b8 <generic_reset_handling>:
+generic_reset_handling():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:488
+
+generic_reset_handling:
+/* Copy sdata section first so that the gp is set and linker relaxation can be
+   used */
+    la a4, __sdata_load
+800005b8:	00002717          	auipc	a4,0x2
+800005bc:	a8870713          	addi	a4,a4,-1400 # 80002040 <__sdata_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:489
+    la a5, __sdata_start
+800005c0:	00004797          	auipc	a5,0x4
+800005c4:	a4078793          	addi	a5,a5,-1472 # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:490
+    la a6, __sdata_end
+800005c8:	00004817          	auipc	a6,0x4
+800005cc:	a4880813          	addi	a6,a6,-1464 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:491
+    beq a4, a5, 1f     /* Exit if source and dest are same */
+800005d0:	00f70863          	beq	a4,a5,800005e0 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:492
+    beq a5, a6, 1f     /* Exit if section start and end addresses are same */
+800005d4:	01078663          	beq	a5,a6,800005e0 <generic_reset_handling+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:493
+    call block_copy
+800005d8:	00000097          	auipc	ra,0x0
+800005dc:	082080e7          	jalr	130(ra) # 8000065a <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:497
+
+1:
+  /* initialize global pointer */
+  la gp, __global_pointer$
+800005e0:	00004197          	auipc	gp,0x4
+800005e4:	22018193          	addi	gp,gp,544 # 80004800 <__global_pointer$>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:514
+  csrw mstatus, t1
+
+  lui t0, 0x0
+  fscsr t0
+#endif
+  call initializations
+800005e8:	2031                	jal	800005f4 <initializations>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:516
+  /* Initialize stack pointer */
+  la sp, __stack_top
+800005ea:	d0018113          	addi	sp,gp,-768 # 80004500 <__stack_top>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:519
+
+  /* Jump into C code */
+  j _init
+800005ee:	23e0006f          	j	8000082c <_init>
+
+800005f2 <vector_address_not_matching>:
+vector_address_not_matching():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:524
+
+/* Error: trap_entry is not at the expected address of reset_vector+mtvec offset
+   as configured in the MIV_RV32 core vectored mode */
+vector_address_not_matching:
+  ebreak
+800005f2:	9002                	ebreak
+
+800005f4 <initializations>:
+initializations():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:528
+
+initializations:
+/* Initialize the .bss section */
+    mv t0, ra           /* Store ra for future use */
+800005f4:	8286                	mv	t0,ra
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:529
+    la  a5, __bss_start
+800005f6:	8a018793          	addi	a5,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:530
+    la  a6, __bss_end
+800005fa:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:531
+    beq a5, a6, 1f     /* Section start and end address are the same */
+800005fe:	01078363          	beq	a5,a6,80000604 <initializations+0x10>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:532
+    call zeroize_block
+80000602:	2835                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:536
+
+1:
+/* Initialize the .sbss section */
+    la  a5, __sbss_start
+80000604:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:537
+    la  a6, __sbss_end
+80000608:	8a018813          	addi	a6,gp,-1888 # 800040a0 <__sbss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:538
+    beq a5, a6, 1f     /* Section start and end address are the same */
+8000060c:	01078a63          	beq	a5,a6,80000620 <initializations+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:539
+    call zeroize_block
+80000610:	203d                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:542
+
+/* Clear heap */
+    la  a5, __heap_start
+80000612:	90018793          	addi	a5,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:543
+    la  a6, __heap_end
+80000616:	90018813          	addi	a6,gp,-1792 # 80004100 <__bss_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:544
+    beq a5, a6, 1f     /* Section start and end address are the same */
+8000061a:	01078363          	beq	a5,a6,80000620 <initializations+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:545
+    call zeroize_block
+8000061e:	2005                	jal	8000063e <zeroize_block>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:549
+
+1:
+/* Copy data section */
+    la  a4, __data_load
+80000620:	00002717          	auipc	a4,0x2
+80000624:	a3070713          	addi	a4,a4,-1488 # 80002050 <__data_load>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:550
+    la  a5, __data_start
+80000628:	81018793          	addi	a5,gp,-2032 # 80004010 <__sdata_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:551
+    la  a6, __data_end
+8000062c:	87018813          	addi	a6,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:552
+    beq a4, a5, 1f     /* Exit early if source and dest are same */
+80000630:	00f70563          	beq	a4,a5,8000063a <initializations+0x46>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:553
+    beq a5, a6, 1f     /* Section start and end addresses are the same */
+80000634:	01078363          	beq	a5,a6,8000063a <initializations+0x46>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:554
+    call block_copy
+80000638:	200d                	jal	8000065a <block_copy>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:557
+
+1:
+    mv ra, t0           /* Retrieve ra */
+8000063a:	8096                	mv	ra,t0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:558
+    ret
+8000063c:	8082                	ret
+
+8000063e <zeroize_block>:
+zeroize_block():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:561
+
+zeroize_block:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+8000063e:	02f86f63          	bltu	a6,a5,8000067c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:562
+    or a7, a6, a5                   /* Check if start or end is unalined */
+80000642:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:563
+    andi a7, a7, 0x03u
+80000646:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:564
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+8000064a:	03104963          	bgtz	a7,8000067c <block_copy_error>
+
+8000064e <zeroize_loop>:
+zeroize_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:566
+zeroize_loop:
+    sw x0, 0(a5)
+8000064e:	0007a023          	sw	zero,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:567
+    add a5, a5, __SIZEOF_POINTER__
+80000652:	0791                	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:568
+    blt a5, a6, zeroize_loop
+80000654:	ff07cde3          	blt	a5,a6,8000064e <zeroize_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:569
+    ret
+80000658:	8082                	ret
+
+8000065a <block_copy>:
+block_copy():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:572
+
+block_copy:
+    bltu a6, a5, block_copy_error   /* Error. End address is less than start */
+8000065a:	02f86163          	bltu	a6,a5,8000067c <block_copy_error>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:573
+    or a7, a6, a5                   /* Check if start or end is unalined */
+8000065e:	00f868b3          	or	a7,a6,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:574
+    andi a7, a7, 0x03u
+80000662:	0038f893          	andi	a7,a7,3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:575
+    bgtz a7, block_copy_error       /* Unaligned addresses error*/
+80000666:	01104b63          	bgtz	a7,8000067c <block_copy_error>
+
+8000066a <block_copy_loop>:
+block_copy_loop():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:577
+block_copy_loop:
+    lw a7, 0(a4)
+8000066a:	00072883          	lw	a7,0(a4)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:578
+    sw a7, 0(a5)
+8000066e:	0117a023          	sw	a7,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:579
+    addi a5, a5, 0x04
+80000672:	0791                	addi	a5,a5,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:580
+    addi a4, a4, 0x04
+80000674:	0711                	addi	a4,a4,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:581
+    blt a5, a6, block_copy_loop
+80000676:	ff07cae3          	blt	a5,a6,8000066a <block_copy_loop>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:582
+    j block_copy_exit
+8000067a:	a011                	j	8000067e <block_copy_exit>
+
+8000067c <block_copy_error>:
+block_copy_error():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:585
+
+block_copy_error:
+    j block_copy_error
+8000067c:	a001                	j	8000067c <block_copy_error>
+
+8000067e <block_copy_exit>:
+block_copy_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_entry.S:588
+
+block_copy_exit:
+    ret
+8000067e:	8082                	ret
+
+80000680 <MRV_read_mtime>:
+MRV_read_mtime():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:684
+
+/***************************************************************************//**
+  The MRV_read_mtime() function returns the current MTIME register value.
+ */
+static inline uint64_t MRV_read_mtime(void)
+{
+80000680:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:685
+    volatile uint32_t hi = 0u;
+80000682:	c402                	sw	zero,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:686
+    volatile uint32_t lo = 0u;
+80000684:	c602                	sw	zero,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691
+
+    /* when mtime lower word is 0xFFFFFFFF, there will be rollover and
+     * returned value could be wrong. */
+    do {
+        hi = MTIMEH;
+80000686:	0200c7b7          	lui	a5,0x200c
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:691 (discriminator 1)
+8000068a:	ffc7a683          	lw	a3,-4(a5) # 200bffc <STACK_SIZE+0x200bbfc>
+8000068e:	c436                	sw	a3,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:692 (discriminator 1)
+        lo = MTIME;
+80000690:	ff87a683          	lw	a3,-8(a5)
+80000694:	c636                	sw	a3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:693 (discriminator 1)
+    } while(hi != MTIMEH);
+80000696:	ffc7a603          	lw	a2,-4(a5)
+8000069a:	46a2                	lw	a3,8(sp)
+8000069c:	fed617e3          	bne	a2,a3,8000068a <MRV_read_mtime+0xa>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:695
+
+    return((((uint64_t)MTIMEH) << 32u) | lo);
+800006a0:	ffc7a583          	lw	a1,-4(a5)
+800006a4:	4532                	lw	a0,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:696
+}
+800006a6:	0141                	addi	sp,sp,16
+800006a8:	8082                	ret
+
+800006aa <MRV_systick_config>:
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+
+/*------------------------------------------------------------------------------
+ * Configure the machine timer to generate an interrupt.
+ */
+uint32_t MRV_systick_config(uint64_t ticks)
+{
+800006aa:	1141                	addi	sp,sp,-16
+800006ac:	c422                	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    uint32_t ret_val = ERROR;
+    uint64_t remainder = ticks;
+    g_systick_increment = 0U;
+800006ae:	4701                	li	a4,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006b0:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:163
+{
+800006b4:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006b6:	87818413          	addi	s0,gp,-1928 # 80004078 <g_systick_increment>
+800006ba:	4681                	li	a3,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006bc:	c3d8                	sw	a4,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006be:	c058                	sw	a4,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:167
+    g_systick_cmp_value = 0U;
+800006c0:	c394                	sw	a3,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:166
+    g_systick_increment = 0U;
+800006c2:	c014                	sw	a3,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:169
+
+    while (remainder >= MTIME_PRESCALER)
+800006c4:	4781                	li	a5,0
+800006c6:	4701                	li	a4,0
+800006c8:	4601                	li	a2,0
+800006ca:	02005837          	lui	a6,0x2005
+800006ce:	00178893          	addi	a7,a5,1
+800006d2:	00082303          	lw	t1,0(a6) # 2005000 <STACK_SIZE+0x2004c00>
+800006d6:	00f8b6b3          	sltu	a3,a7,a5
+800006da:	96ba                	add	a3,a3,a4
+800006dc:	e9a9                	bnez	a1,8000072e <MRV_systick_config+0x84>
+800006de:	04657863          	bgeu	a0,t1,8000072e <MRV_systick_config+0x84>
+800006e2:	c609                	beqz	a2,800006ec <MRV_systick_config+0x42>
+800006e4:	86f1ac23          	sw	a5,-1928(gp) # 80004078 <g_systick_increment>
+800006e8:	86e1ae23          	sw	a4,-1924(gp) # 8000407c <g_systick_increment+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:175
+    {
+        remainder -= MTIME_PRESCALER;
+        g_systick_increment++;
+    }
+
+    g_systick_cmp_value = g_systick_increment + MRV_read_mtime();
+800006ec:	3f51                	jal	80000680 <MRV_read_mtime>
+800006ee:	401c                	lw	a5,0(s0)
+800006f0:	4054                	lw	a3,4(s0)
+800006f2:	00f50733          	add	a4,a0,a5
+800006f6:	00a73533          	sltu	a0,a4,a0
+800006fa:	95b6                	add	a1,a1,a3
+800006fc:	95aa                	add	a1,a1,a0
+800006fe:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000702:	86b1aa23          	sw	a1,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+
+    if (g_systick_increment > 0U)
+80000706:	8fd5                	or	a5,a5,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:164
+    uint32_t ret_val = ERROR;
+80000708:	4505                	li	a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:177
+    if (g_systick_increment > 0U)
+8000070a:	cf91                	beqz	a5,80000726 <MRV_systick_config+0x7c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:179
+    {
+        WRITE_MTIMECMP(g_systick_cmp_value);
+8000070c:	020047b7          	lui	a5,0x2004
+80000710:	56fd                	li	a3,-1
+80000712:	c3d4                	sw	a3,4(a5)
+80000714:	c398                	sw	a4,0(a5)
+80000716:	c3cc                	sw	a1,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:180
+        set_csr(mie, MIP_MTIP);
+80000718:	08000793          	li	a5,128
+8000071c:	3047a7f3          	csrrs	a5,mie,a5
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:617
+    set_csr(mstatus, MSTATUS_MIE);
+80000720:	300467f3          	csrrsi	a5,mstatus,8
+MRV_systick_config():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:182
+        MRV_enable_interrupts();
+        ret_val = SUCCESS;
+80000724:	4501                	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:186
+    }
+
+    return ret_val;
+}
+80000726:	40b2                	lw	ra,12(sp)
+80000728:	4422                	lw	s0,8(sp)
+8000072a:	0141                	addi	sp,sp,16
+8000072c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:171
+        remainder -= MTIME_PRESCALER;
+8000072e:	00082783          	lw	a5,0(a6)
+80000732:	4605                	li	a2,1
+80000734:	40f507b3          	sub	a5,a0,a5
+80000738:	00f53733          	sltu	a4,a0,a5
+8000073c:	8d99                	sub	a1,a1,a4
+8000073e:	853e                	mv	a0,a5
+80000740:	8736                	mv	a4,a3
+80000742:	87c6                	mv	a5,a7
+80000744:	b769                	j	800006ce <MRV_systick_config+0x24>
+
+80000746 <handle_m_timer_interrupt>:
+handle_m_timer_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:192
+
+/*------------------------------------------------------------------------------
+ * RISC-V interrupt handler for machine timer interrupts.
+ */
+void handle_m_timer_interrupt(void)
+{
+80000746:	1141                	addi	sp,sp,-16
+80000748:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:193
+    clear_csr(mie, MIP_MTIP);
+8000074a:	08000793          	li	a5,128
+8000074e:	3047b7f3          	csrrc	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:195
+
+    uint64_t mtime_at_irq = MRV_read_mtime();
+80000752:	373d                	jal	80000680 <MRV_read_mtime>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+
+#ifndef NDEBUG
+    static volatile uint32_t d_tick = 0u;
+#endif
+
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000754:	87018793          	addi	a5,gp,-1936 # 80004070 <__data_end>
+80000758:	4398                	lw	a4,0(a5)
+8000075a:	00550613          	addi	a2,a0,5
+8000075e:	43dc                	lw	a5,4(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000760:	87818693          	addi	a3,gp,-1928 # 80004078 <g_systick_increment>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000764:	00a63533          	sltu	a0,a2,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+80000768:	0006a803          	lw	a6,0(a3)
+8000076c:	0046a883          	lw	a7,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:201
+    while(g_systick_cmp_value < (mtime_at_irq + MTIME_DELTA)) {
+80000770:	95aa                	add	a1,a1,a0
+80000772:	4681                	li	a3,0
+80000774:	02b7e963          	bltu	a5,a1,800007a6 <handle_m_timer_interrupt+0x60>
+80000778:	00f59463          	bne	a1,a5,80000780 <handle_m_timer_interrupt+0x3a>
+8000077c:	02c76563          	bltu	a4,a2,800007a6 <handle_m_timer_interrupt+0x60>
+80000780:	c689                	beqz	a3,8000078a <handle_m_timer_interrupt+0x44>
+80000782:	86e1a823          	sw	a4,-1936(gp) # 80004070 <__data_end>
+80000786:	86f1aa23          	sw	a5,-1932(gp) # 80004074 <__data_end+0x4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:223
+     * If you are running the program using the debugger and halt the CPU at a 
+     * breakpoint, MTIME will continue to increment and interrupts will be 
+     * missed; resulting in d_tick > 1.
+     */
+
+    WRITE_MTIMECMP(g_systick_cmp_value);
+8000078a:	020046b7          	lui	a3,0x2004
+8000078e:	567d                	li	a2,-1
+80000790:	c2d0                	sw	a2,4(a3)
+80000792:	c298                	sw	a4,0(a3)
+80000794:	c2dc                	sw	a5,4(a3)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:225
+
+    SysTick_Handler();
+80000796:	2905                	jal	80000bc6 <SysTick_Handler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:227
+
+    set_csr(mie, MIP_MTIP);
+80000798:	08000793          	li	a5,128
+8000079c:	3047a7f3          	csrrs	a5,mie,a5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:228
+}
+800007a0:	40b2                	lw	ra,12(sp)
+800007a2:	0141                	addi	sp,sp,16
+800007a4:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:202
+        g_systick_cmp_value = g_systick_cmp_value + g_systick_increment;
+800007a6:	010706b3          	add	a3,a4,a6
+800007aa:	00e6b533          	sltu	a0,a3,a4
+800007ae:	97c6                	add	a5,a5,a7
+800007b0:	8736                	mv	a4,a3
+800007b2:	97aa                	add	a5,a5,a0
+800007b4:	4685                	li	a3,1
+800007b6:	bf7d                	j	80000774 <handle_m_timer_interrupt+0x2e>
+
+800007b8 <handle_m_soft_interrupt>:
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:231
+
+void handle_m_soft_interrupt(void)
+{
+800007b8:	1141                	addi	sp,sp,-16
+800007ba:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:232
+    Software_IRQHandler();
+800007bc:	2101                	jal	80000bbc <Software_IRQHandler>
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+800007be:	6719                	lui	a4,0x6
+800007c0:	531c                	lw	a5,32(a4)
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+    MRV_clear_soft_irq();
+}
+800007c2:	40b2                	lw	ra,12(sp)
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.h:735
+800007c4:	9bf5                	andi	a5,a5,-3
+800007c6:	d31c                	sw	a5,32(a4)
+handle_m_soft_interrupt():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:234
+800007c8:	0141                	addi	sp,sp,16
+800007ca:	8082                	ret
+
+800007cc <handle_local_ei_interrupts>:
+handle_local_ei_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:306
+/*------------------------------------------------------------------------------
+ * Jump to interrupt table containing local interrupts
+ */
+void handle_local_ei_interrupts(uint8_t irq_no)
+{
+    uint64_t mhart_id = read_csr(mhartid);
+800007cc:	f14027f3          	csrr	a5,mhartid
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:310
+    ASSERT(irq_no <= MIV_LOCAL_IRQ_MAX)
+    ASSERT(irq_no >= MIV_LOCAL_IRQ_MIN)
+
+    uint8_t ei_no = (uint8_t)(irq_no - MIV_LOCAL_IRQ_MIN);
+800007d0:	1541                	addi	a0,a0,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:311
+    (*local_irq_handler_table[ei_no])();
+800007d2:	0ff57513          	andi	a0,a0,255
+800007d6:	050a                	slli	a0,a0,0x2
+800007d8:	00001797          	auipc	a5,0x1
+800007dc:	5d878793          	addi	a5,a5,1496 # 80001db0 <local_irq_handler_table>
+800007e0:	953e                	add	a0,a0,a5
+800007e2:	00052303          	lw	t1,0(a0)
+800007e6:	8302                	jr	t1
+
+800007e8 <handle_trap>:
+handle_trap():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:323
+ */
+void handle_trap(uintptr_t mcause, uintptr_t mepc)
+{   
+    uint64_t is_interrupt = mcause & MCAUSE_INT;
+
+    if (is_interrupt)
+800007e8:	02055d63          	bgez	a0,80000822 <handle_trap+0x3a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326
+    {
+#ifndef MIV_LEGACY_RV32
+        if (((mcause & MCAUSE_CAUSE) >= MIV_LOCAL_IRQ_MIN) && ((mcause & MCAUSE_CAUSE) <= MIV_LOCAL_IRQ_MAX))
+800007ec:	800007b7          	lui	a5,0x80000
+800007f0:	ff07c713          	xori	a4,a5,-16
+800007f4:	8f69                	and	a4,a4,a0
+800007f6:	cb01                	beqz	a4,80000806 <handle_trap+0x1e>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:326 (discriminator 1)
+800007f8:	fe07c793          	xori	a5,a5,-32
+800007fc:	8fe9                	and	a5,a5,a0
+800007fe:	e781                	bnez	a5,80000806 <handle_trap+0x1e>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:328
+        {
+            handle_local_ei_interrupts((uint8_t)(mcause & MCAUSE_CAUSE));
+80000800:	0ff57513          	andi	a0,a0,255
+80000804:	b7e1                	j	800007cc <handle_local_ei_interrupts>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:330
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+80000806:	0506                	slli	a0,a0,0x1
+80000808:	8105                	srli	a0,a0,0x1
+8000080a:	47ad                	li	a5,11
+8000080c:	00f51363          	bne	a0,a5,80000812 <handle_trap+0x2a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:336
+#else
+        if ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)
+#endif
+        {
+#ifndef MIV_LEGACY_RV32
+            External_IRQHandler();
+80000810:	a025                	j	80000838 <External_IRQHandler>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:341
+#else
+            handle_m_ext_interrupt();
+#endif
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_SOFT)
+80000812:	478d                	li	a5,3
+80000814:	00f51363          	bne	a0,a5,8000081a <handle_trap+0x32>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:343
+        {
+            handle_m_soft_interrupt();
+80000818:	b745                	j	800007b8 <handle_m_soft_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:345
+        }
+        else if ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)
+8000081a:	479d                	li	a5,7
+8000081c:	00f51763          	bne	a0,a5,8000082a <handle_trap+0x42>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:347
+        {
+            handle_m_timer_interrupt();
+80000820:	b71d                	j	80000746 <handle_m_timer_interrupt>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000822:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+         uintptr_t mmepc  = read_csr(mepc);
+
+        /* breakpoint */
+        __asm__("ebreak");
+#else
+        _exit(1 + mcause);
+80000824:	0505                	addi	a0,a0,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:320
+{   
+80000826:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_hal.c:402
+        _exit(1 + mcause);
+80000828:	2035                	jal	80000854 <_exit>
+8000082a:	8082                	ret
+
+8000082c <_init>:
+_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:27
+    /* This function is a placeholder for the case where some more hardware
+     * specific initializations are required before jumping into the application
+     * code. You can implement it here. */
+
+    /* Jump to the application code after all initializations are completed */
+    main();
+8000082c:	aec1                	j	80000bfc <main>
+
+8000082e <_fini>:
+_fini():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_init.c:34
+
+/* Function called after main() finishes */
+void
+_fini(void)
+{
+}
+8000082e:	8082                	ret
+
+80000830 <Software_IRQHandler.localalias.0>:
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+__attribute__((weak)) void Software_IRQHandler(void)
+{
+80000830:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000832:	4529                	li	a0,10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:23
+{
+80000834:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_stubs.c:24
+    _exit(10);
+80000836:	2839                	jal	80000854 <_exit>
+
+80000838 <External_IRQHandler>:
+External_IRQHandler():
+80000838:	8082                	ret
+
+8000083a <MGECI_IRQHandler>:
+MGECI_IRQHandler():
+8000083a:	8082                	ret
+
+8000083c <MGEUI_IRQHandler>:
+MGEUI_IRQHandler():
+8000083c:	8082                	ret
+
+8000083e <SUBSYS_IRQHandler>:
+SUBSYS_IRQHandler():
+8000083e:	8082                	ret
+
+80000840 <MSYS_EI0_IRQHandler>:
+MSYS_EI0_IRQHandler():
+80000840:	8082                	ret
+
+80000842 <MSYS_EI1_IRQHandler>:
+MSYS_EI1_IRQHandler():
+80000842:	8082                	ret
+
+80000844 <MSYS_EI2_IRQHandler>:
+MSYS_EI2_IRQHandler():
+80000844:	8082                	ret
+
+80000846 <MSYS_EI3_IRQHandler>:
+MSYS_EI3_IRQHandler():
+80000846:	8082                	ret
+
+80000848 <MSYS_EI4_IRQHandler>:
+MSYS_EI4_IRQHandler():
+80000848:	8082                	ret
+
+8000084a <MSYS_EI5_IRQHandler>:
+MSYS_EI5_IRQHandler():
+8000084a:	8082                	ret
+
+8000084c <Reserved_IRQHandler>:
+Reserved_IRQHandler():
+8000084c:	b7d5                	j	80000830 <Software_IRQHandler.localalias.0>
+
+8000084e <MSYS_EI6_IRQHandler>:
+MSYS_EI6_IRQHandler():
+8000084e:	8082                	ret
+
+80000850 <MSYS_EI7_IRQHandler>:
+MSYS_EI7_IRQHandler():
+80000850:	8082                	ret
+
+80000852 <SUBSYSR_IRQHandler>:
+SUBSYSR_IRQHandler():
+80000852:	8082                	ret
+
+80000854 <_exit>:
+_exit():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:150 (discriminator 1)
+
+    write(STDERR_FILENO, message, strlen(message));
+    write_hex(STDERR_FILENO, code);
+#endif
+
+    while (1){};
+80000854:	a001                	j	80000854 <_exit>
+
+80000856 <_sbrk>:
+_sbrk():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169
+     * You need to set HEAP_SIZE to a non-zero value in your linker script if
+     * the following assertion fires.
+     */
+    ASSERT(&__heap_end > &__heap_start);
+
+    if (((curbrk + incr) < &_end) || ((curbrk + incr) > &_heap_end))
+80000856:	00003797          	auipc	a5,0x3
+8000085a:	7aa78793          	addi	a5,a5,1962 # 80004000 <__sdata_start>
+8000085e:	439c                	lw	a5,0(a5)
+80000860:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+80000864:	953e                	add	a0,a0,a5
+80000866:	00e56c63          	bltu	a0,a4,8000087e <_sbrk+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:169 (discriminator 1)
+8000086a:	90018713          	addi	a4,gp,-1792 # 80004100 <__bss_end>
+8000086e:	00a76863          	bltu	a4,a0,8000087e <_sbrk+0x28>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:176
+        errno = ENOMEM;
+        ret = ((char *) - 1);
+    }
+    else
+    {
+        curbrk += incr;
+80000872:	00003717          	auipc	a4,0x3
+80000876:	78a72723          	sw	a0,1934(a4) # 80004000 <__sdata_start>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:188
+     * assertion fires.
+     * */
+    ASSERT(curbrk <= &__heap_end);
+
+    return(ret);
+}
+8000087a:	853e                	mv	a0,a5
+8000087c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:172
+        ret = ((char *) - 1);
+8000087e:	57fd                	li	a5,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:187
+    return(ret);
+80000880:	bfed                	j	8000087a <_sbrk+0x24>
+
+80000882 <_isatty>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:205
+        errno = EBADF;
+        ret = 0;
+    }
+
+    return(ret);
+}
+80000882:	00352513          	slti	a0,a0,3
+80000886:	8082                	ret
+
+80000888 <_close>:
+_close():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:226
+}
+
+int _close(int fd)
+{
+    return stub(EBADF);
+}
+80000888:	557d                	li	a0,-1
+8000088a:	8082                	ret
+
+8000088c <_fstat>:
+_fstat():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:239
+{
+    return stub(EAGAIN);
+}
+
+int _fstat(int fd, struct stat *st)
+{
+8000088c:	1101                	addi	sp,sp,-32
+8000088e:	ce06                	sw	ra,28(sp)
+80000890:	c62e                	sw	a1,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:242
+    int ret = 0;
+
+    if (isatty(fd))
+80000892:	2935                	jal	80000cce <isatty>
+80000894:	c901                	beqz	a0,800008a4 <_fstat+0x18>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+    {
+        st->st_mode = S_IFCHR;
+80000896:	45b2                	lw	a1,12(sp)
+80000898:	6789                	lui	a5,0x2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:245
+        ret = 0;
+8000089a:	4501                	li	a0,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:244
+        st->st_mode = S_IFCHR;
+8000089c:	c1dc                	sw	a5,4(a1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:253
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+8000089e:	40f2                	lw	ra,28(sp)
+800008a0:	6105                	addi	sp,sp,32
+800008a2:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:249
+        ret = stub(EBADF);
+800008a4:	557d                	li	a0,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:252
+    return ret;
+800008a6:	bfe5                	j	8000089e <_fstat+0x12>
+
+800008a8 <_lseek>:
+_isatty():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:194
+    if (fd <= 2)    /* one of stdin, stdout, stderr */
+800008a8:	00352513          	slti	a0,a0,3
+_lseek():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:283
+    {
+        ret = stub(EBADF);
+    }
+
+    return ret;
+}
+800008ac:	157d                	addi	a0,a0,-1
+800008ae:	8082                	ret
+
+800008b0 <_read>:
+_read():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/miv_rv32_hal/miv_rv32_syscall.c:313
+        return  count;          /* Filled the buffer */
+    }
+#endif
+
+    return stub(EBADF);
+}
+800008b0:	557d                	li	a0,-1
+800008b2:	8082                	ret
+
+800008b4 <_write>:
+_write():
+800008b4:	557d                	li	a0,-1
+800008b6:	8082                	ret
+
+800008b8 <HAL_enable_interrupts>:
+MRV_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:617
+  @return
+  This functions returns the CORE_GPR_DED_RESET_REG bit value.
+ */
+static inline void MRV_enable_interrupts(void)
+{
+    set_csr(mstatus, MSTATUS_MIE);
+800008b8:	300467f3          	csrrsi	a5,mstatus,8
+HAL_enable_interrupts():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hal_irq.c:24
+/*------------------------------------------------------------------------------
+ * 
+ */
+void HAL_enable_interrupts(void) {
+    MRV_enable_interrupts();
+}
+800008bc:	8082                	ret
+
+800008be <HW_set_32bit_reg>:
+HW_set_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:39
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    sw a1, 0(a0)
+800008be:	c10c                	sw	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:40
+    ret
+800008c0:	8082                	ret
+
+800008c2 <HW_get_32bit_reg>:
+HW_get_32bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:51
+ * a0:   addr_t reg_addr
+
+ * @return          32 bits value read from the peripheral register.
+ */
+HW_get_32bit_reg:
+    lw a0, 0(a0)
+800008c2:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:52
+    ret
+800008c4:	8082                	ret
+
+800008c6 <HW_set_32bit_reg_field>:
+HW_set_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:64
+ * a1:   int_fast8_t shift
+ * a2:   uint32_t mask
+ * a3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    mv t3, a3
+800008c6:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:65
+    sll t3, t3, a1
+800008c8:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:66
+    and  t3, t3, a2
+800008cc:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:67
+    lw t1, 0(a0)
+800008d0:	00052303          	lw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:68
+    mv t2, a2
+800008d4:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:69
+    not t2, t2
+800008d6:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:70
+    and t1, t1, t2
+800008da:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:71
+    or t1, t1, t3
+800008de:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:72
+    sw t1, 0(a0)
+800008e2:	00652023          	sw	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:73
+    ret
+800008e6:	8082                	ret
+
+800008e8 <HW_get_32bit_reg_field>:
+HW_get_32bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:87
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_32bit_reg_field:
+    lw a0, 0(a0)
+800008e8:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:88
+    and a0, a0, a2
+800008ea:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:89
+    srl a0, a0, a1
+800008ec:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:90
+    ret
+800008f0:	8082                	ret
+
+800008f2 <HW_set_16bit_reg>:
+HW_set_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:100
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    sh a1, 0(a0)
+800008f2:	00b51023          	sh	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:101
+    ret
+800008f6:	8082                	ret
+
+800008f8 <HW_get_16bit_reg>:
+HW_get_16bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:112
+ * a0:   addr_t reg_addr
+
+ * @return          16 bits value read from the peripheral register.
+ */
+HW_get_16bit_reg:
+    lh a0, (a0)
+800008f8:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:113
+    ret
+800008fc:	8082                	ret
+
+800008fe <HW_set_16bit_reg_field>:
+HW_set_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:126
+ * a2:   uint_fast16_t mask
+ * a3:   uint_fast16_t value
+ * @param value     Value to be written in the specified field.
+ */
+HW_set_16bit_reg_field:
+    mv t3, a3
+800008fe:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:127
+    sll t3, t3, a1
+80000900:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:128
+    and  t3, t3, a2
+80000904:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:129
+    lh t1, 0(a0)
+80000908:	00051303          	lh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:130
+    mv t2, a2
+8000090c:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:131
+    not t2, t2
+8000090e:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:132
+    and t1, t1, t2
+80000912:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:133
+    or t1, t1, t3
+80000916:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:134
+    sh t1, 0(a0)
+8000091a:	00651023          	sh	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:135
+    ret
+8000091e:	8082                	ret
+
+80000920 <HW_get_16bit_reg_field>:
+HW_get_16bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:149
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_16bit_reg_field:
+    lh a0, 0(a0)
+80000920:	00051503          	lh	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:150
+    and a0, a0, a2
+80000924:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:151
+    srl a0, a0, a1
+80000926:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:152
+    ret
+8000092a:	8082                	ret
+
+8000092c <HW_set_8bit_reg>:
+HW_set_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:162
+ *
+ * a0:   addr_t reg_addr
+ * a1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    sb a1, 0(a0)
+8000092c:	00b50023          	sb	a1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:163
+    ret
+80000930:	8082                	ret
+
+80000932 <HW_get_8bit_reg>:
+HW_get_8bit_reg():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:174
+ * a0:   addr_t reg_addr
+
+ * @return          8 bits value read from the peripheral register.
+ */
+HW_get_8bit_reg:
+    lb a0, 0(a0)
+80000932:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:175
+    ret
+80000936:	8082                	ret
+
+80000938 <HW_set_8bit_reg_field>:
+HW_set_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:187
+ * a1:   int_fast8_t shift
+ * a2:   uint_fast8_t mask
+ * a3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    mv t3, a3
+80000938:	8e36                	mv	t3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:188
+    sll t3, t3, a1
+8000093a:	00be1e33          	sll	t3,t3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:189
+    and  t3, t3, a2
+8000093e:	00ce7e33          	and	t3,t3,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:190
+    lb t1, 0(a0)
+80000942:	00050303          	lb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:191
+    mv t2, a2
+80000946:	83b2                	mv	t2,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:192
+    not t2, t2
+80000948:	fff3c393          	not	t2,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:193
+    and t1, t1, t2
+8000094c:	00737333          	and	t1,t1,t2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:194
+    or t1, t1, t3
+80000950:	01c36333          	or	t1,t1,t3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:195
+    sb t1, 0(a0)
+80000954:	00650023          	sb	t1,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:196
+    ret
+80000958:	8082                	ret
+
+8000095a <HW_get_8bit_reg_field>:
+HW_get_8bit_reg_field():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:210
+ *
+ * @return          8 bits value containing the register field value specified
+ *                  as parameter.
+ */
+HW_get_8bit_reg_field:
+    lb a0, 0(a0)
+8000095a:	00050503          	lb	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:211
+    and a0, a0, a2
+8000095e:	8d71                	and	a0,a0,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:212
+    srl a0, a0, a1
+80000960:	00b55533          	srl	a0,a0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/hal/hw_reg_access.S:213
+    ret
+80000964:	8082                	ret
+
+80000966 <UART_init>:
+UART_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( line_config <= MAX_LINE_CONFIG )
+    HAL_ASSERT( baud_value <= MAX_BAUD_VALUE )
+
+    if( ( this_uart != NULL_INSTANCE ) &&
+80000966:	c525                	beqz	a0,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:53 (discriminator 1)
+80000968:	479d                	li	a5,7
+8000096a:	06d7e263          	bltu	a5,a3,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:54
+        ( line_config <= MAX_LINE_CONFIG ) &&
+8000096e:	6789                	lui	a5,0x2
+80000970:	04f67f63          	bgeu	a2,a5,800009ce <UART_init+0x68>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+80000974:	1101                	addi	sp,sp,-32
+80000976:	cc22                	sw	s0,24(sp)
+80000978:	c84a                	sw	s2,16(sp)
+8000097a:	8432                	mv	s0,a2
+8000097c:	892e                	mv	s2,a1
+8000097e:	ca26                	sw	s1,20(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        ( baud_value <= MAX_BAUD_VALUE ) )
+    {
+        /*
+         * Store lower 8-bits of baud value in CTRL1.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000980:	0ff67593          	andi	a1,a2,255
+80000984:	84aa                	mv	s1,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+    
+        /*
+         * Extract higher 5-bits of baud value and store in higher 5-bits 
+         * of CTRL2, along with line configuration in lower 3 three bits.
+         */
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000986:	8415                	srai	s0,s0,0x5
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000988:	00890513          	addi	a0,s2,8
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:46
+{
+8000098c:	ce06                	sw	ra,28(sp)
+8000098e:	c64e                	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000990:	7f847413          	andi	s0,s0,2040
+80000994:	89b6                	mv	s3,a3
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:60
+        HAL_set_8bit_reg( base_addr, CTRL1, (uint_fast8_t)(baud_value &
+80000996:	3f59                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:67
+        HAL_set_8bit_reg( base_addr, CTRL2, (uint_fast8_t)line_config | 
+80000998:	00c90513          	addi	a0,s2,12
+8000099c:	013465b3          	or	a1,s0,s3
+800009a0:	3771                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:94
+        
+        /*
+         * Flush the receive FIFO of data that may have been received before the
+         * driver was initialized.
+         */
+        rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009a2:	01090513          	addi	a0,s2,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:71
+        this_uart->base_address = base_addr;
+800009a6:	0124a023          	sw	s2,0(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+                                                    STATUS_RXFULL_MASK;
+        while ( rx_full )
+        {
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009aa:	3761                	jal	80000932 <HW_get_8bit_reg>
+800009ac:	8909                	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:96
+        while ( rx_full )
+800009ae:	e911                	bnez	a0,800009c2 <UART_init+0x5c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:106
+        }
+
+        /*
+         * Clear status of the UART instance.
+         */
+        this_uart->status = (uint8_t)0;
+800009b0:	00048223          	sb	zero,4(s1)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:108
+    }
+}
+800009b4:	40f2                	lw	ra,28(sp)
+800009b6:	4462                	lw	s0,24(sp)
+800009b8:	44d2                	lw	s1,20(sp)
+800009ba:	4942                	lw	s2,16(sp)
+800009bc:	49b2                	lw	s3,12(sp)
+800009be:	6105                	addi	sp,sp,32
+800009c0:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:98
+            HAL_get_8bit_reg( this_uart->base_address, RXDATA );
+800009c2:	4088                	lw	a0,0(s1)
+800009c4:	0511                	addi	a0,a0,4
+800009c6:	37b5                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:99
+            rx_full = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+800009c8:	4088                	lw	a0,0(s1)
+800009ca:	0541                	addi	a0,a0,16
+800009cc:	bff9                	j	800009aa <UART_init+0x44>
+800009ce:	8082                	ret
+
+800009d0 <UART_get_rx>:
+UART_get_rx():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:199
+(
+    UART_instance_t * this_uart,
+    uint8_t * rx_buffer,
+    size_t buff_size
+)
+{
+800009d0:	1101                	addi	sp,sp,-32
+800009d2:	ce06                	sw	ra,28(sp)
+800009d4:	cc22                	sw	s0,24(sp)
+800009d6:	ca26                	sw	s1,20(sp)
+800009d8:	c84a                	sw	s2,16(sp)
+800009da:	c64e                	sw	s3,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208
+    
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( rx_buffer != NULL_BUFFER )
+    HAL_ASSERT( buff_size > 0 )
+      
+    if( (this_uart != NULL_INSTANCE) &&
+800009dc:	cd29                	beqz	a0,80000a36 <UART_get_rx+0x66>
+800009de:	89ae                	mv	s3,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:208 (discriminator 1)
+800009e0:	c9b9                	beqz	a1,80000a36 <UART_get_rx+0x66>
+800009e2:	84b2                	mv	s1,a2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:209
+        (rx_buffer != NULL_BUFFER)   &&
+800009e4:	ce19                	beqz	a2,80000a02 <UART_get_rx+0x32>
+800009e6:	842a                	mv	s0,a0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        (buff_size > 0u) )
+    {
+        rx_idx = 0u;
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800009e8:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:212
+        rx_idx = 0u;
+800009ea:	4901                	li	s2,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:213
+        new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+800009ec:	0541                	addi	a0,a0,16
+800009ee:	3791                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:214
+        this_uart->status |= new_status;
+800009f0:	00444783          	lbu	a5,4(s0)
+800009f4:	8fc9                	or	a5,a5,a0
+800009f6:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:215
+        rx_full = new_status & STATUS_RXFULL_MASK;
+800009fa:	8909                	andi	a0,a0,2
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216
+        while ( ( rx_full ) && ( rx_idx < buff_size ) )
+800009fc:	cd1d                	beqz	a0,80000a3a <UART_get_rx+0x6a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:216 (discriminator 1)
+800009fe:	00991a63          	bne	s2,s1,80000a12 <UART_get_rx+0x42>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:227
+            this_uart->status |= new_status;
+            rx_full = new_status & STATUS_RXFULL_MASK;
+        }
+    }
+    return rx_idx;
+}
+80000a02:	40f2                	lw	ra,28(sp)
+80000a04:	4462                	lw	s0,24(sp)
+80000a06:	8526                	mv	a0,s1
+80000a08:	4942                	lw	s2,16(sp)
+80000a0a:	44d2                	lw	s1,20(sp)
+80000a0c:	49b2                	lw	s3,12(sp)
+80000a0e:	6105                	addi	sp,sp,32
+80000a10:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:218
+            rx_buffer[rx_idx] = HAL_get_8bit_reg( this_uart->base_address,
+80000a12:	4008                	lw	a0,0(s0)
+80000a14:	0511                	addi	a0,a0,4
+80000a16:	3f31                	jal	80000932 <HW_get_8bit_reg>
+80000a18:	012987b3          	add	a5,s3,s2
+80000a1c:	00a78023          	sb	a0,0(a5) # 2000 <STACK_SIZE+0x1c00>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+80000a20:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:220
+            rx_idx++;
+80000a22:	0905                	addi	s2,s2,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:221
+            new_status = HAL_get_8bit_reg( this_uart->base_address, STATUS );
+80000a24:	0541                	addi	a0,a0,16
+80000a26:	3731                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:222
+            this_uart->status |= new_status;
+80000a28:	00444783          	lbu	a5,4(s0)
+80000a2c:	8fc9                	or	a5,a5,a0
+80000a2e:	00f40223          	sb	a5,4(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:223
+            rx_full = new_status & STATUS_RXFULL_MASK;
+80000a32:	8909                	andi	a0,a0,2
+80000a34:	b7e1                	j	800009fc <UART_get_rx+0x2c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:202
+    size_t rx_idx = 0u;
+80000a36:	4481                	li	s1,0
+80000a38:	b7e9                	j	80000a02 <UART_get_rx+0x32>
+80000a3a:	84ca                	mv	s1,s2
+80000a3c:	b7d9                	j	80000a02 <UART_get_rx+0x32>
+
+80000a3e <UART_polled_tx_string>:
+UART_polled_tx_string():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246
+    uint8_t tx_ready;
+
+    HAL_ASSERT( this_uart != NULL_INSTANCE )
+    HAL_ASSERT( p_sz_string != NULL_BUFFER )
+    
+    if( ( this_uart != NULL_INSTANCE ) && ( p_sz_string != NULL_BUFFER ) )
+80000a3e:	c91d                	beqz	a0,80000a74 <UART_polled_tx_string+0x36>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:246 (discriminator 1)
+80000a40:	c995                	beqz	a1,80000a74 <UART_polled_tx_string+0x36>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:239
+{
+80000a42:	1141                	addi	sp,sp,-16
+80000a44:	c422                	sw	s0,8(sp)
+80000a46:	c226                	sw	s1,4(sp)
+80000a48:	c606                	sw	ra,12(sp)
+80000a4a:	84aa                	mv	s1,a0
+80000a4c:	842e                	mv	s0,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:249
+    {
+        char_idx = 0U;
+        while( 0U != p_sz_string[char_idx] )
+80000a4e:	00044783          	lbu	a5,0(s0)
+80000a52:	e791                	bnez	a5,80000a5e <UART_polled_tx_string+0x20>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:262
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+                              (uint_fast8_t)p_sz_string[char_idx] );
+            char_idx++;
+        }
+    }
+}
+80000a54:	40b2                	lw	ra,12(sp)
+80000a56:	4422                	lw	s0,8(sp)
+80000a58:	4492                	lw	s1,4(sp)
+80000a5a:	0141                	addi	sp,sp,16
+80000a5c:	8082                	ret
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:253 (discriminator 1)
+                tx_ready = HAL_get_8bit_reg( this_uart->base_address, STATUS ) &
+80000a5e:	4088                	lw	a0,0(s1)
+80000a60:	0541                	addi	a0,a0,16
+80000a62:	3dc1                	jal	80000932 <HW_get_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:255 (discriminator 1)
+            } while ( !tx_ready );
+80000a64:	8905                	andi	a0,a0,1
+80000a66:	dd65                	beqz	a0,80000a5e <UART_polled_tx_string+0x20>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:257
+            HAL_set_8bit_reg( this_uart->base_address, TXDATA,
+80000a68:	00044583          	lbu	a1,0(s0)
+80000a6c:	4088                	lw	a0,0(s1)
+80000a6e:	0405                	addi	s0,s0,1
+80000a70:	3d75                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreUARTapb/core_uart_apb.c:259
+            char_idx++;
+80000a72:	bff1                	j	80000a4e <UART_polled_tx_string+0x10>
+80000a74:	8082                	ret
+
+80000a76 <GPIO_init>:
+GPIO_init():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+(
+    gpio_instance_t *   this_gpio,
+    addr_t              base_addr,
+    gpio_apb_width_t    bus_width
+)
+{
+80000a76:	1141                	addi	sp,sp,-16
+80000a78:	c422                	sw	s0,8(sp)
+80000a7a:	842a                	mv	s0,a0
+80000a7c:	c226                	sw	s1,4(sp)
+80000a7e:	c04a                	sw	s2,0(sp)
+80000a80:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:41
+    uint8_t i = 0;
+    addr_t cfg_reg_addr = base_addr;
+    
+    this_gpio->base_addr = base_addr;
+80000a82:	c00c                	sw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:37
+{
+80000a84:	84ae                	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:42
+    this_gpio->apb_bus_width = bus_width;
+80000a86:	c150                	sw	a2,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45
+    
+    /* Clear configuration. */
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80000a88:	08058913          	addi	s2,a1,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+    {
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80000a8c:	8526                	mv	a0,s1
+80000a8e:	4581                	li	a1,0
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:48 (discriminator 3)
+        cfg_reg_addr += 4;
+80000a90:	0491                	addi	s1,s1,4
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:47 (discriminator 3)
+        HW_set_8bit_reg( cfg_reg_addr, 0 );
+80000a92:	3d69                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:45 (discriminator 3)
+    for( i = 0, cfg_reg_addr = base_addr; i < NB_OF_GPIO; ++i )
+80000a94:	ff249ce3          	bne	s1,s2,80000a8c <GPIO_init+0x16>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:51
+    }
+    /* Clear any pending interrupts */
+    switch( this_gpio->apb_bus_width )
+80000a98:	405c                	lw	a5,4(s0)
+80000a9a:	4705                	li	a4,1
+80000a9c:	02e78063          	beq	a5,a4,80000abc <GPIO_init+0x46>
+80000aa0:	c3a1                	beqz	a5,80000ae0 <GPIO_init+0x6a>
+80000aa2:	4709                	li	a4,2
+80000aa4:	06e79b63          	bne	a5,a4,80000b1a <GPIO_init+0xa4>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000aa8:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+            
+        default:
+            HAL_ASSERT(0);
+            break;
+    }
+}
+80000aaa:	4422                	lw	s0,8(sp)
+80000aac:	40b2                	lw	ra,12(sp)
+80000aae:	4492                	lw	s1,4(sp)
+80000ab0:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000ab2:	55fd                	li	a1,-1
+80000ab4:	08050513          	addi	a0,a0,128
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000ab8:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:54
+            HAL_set_32bit_reg( this_gpio->base_addr, IRQ, CLEAR_ALL_IRQ32 );
+80000aba:	b511                	j	800008be <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:58
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ0, (uint16_t)CLEAR_ALL_IRQ16 );
+80000abc:	4008                	lw	a0,0(s0)
+80000abe:	64c1                	lui	s1,0x10
+80000ac0:	fff48593          	addi	a1,s1,-1 # ffff <STACK_SIZE+0xfbff>
+80000ac4:	08050513          	addi	a0,a0,128
+80000ac8:	352d                	jal	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000aca:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000acc:	4422                	lw	s0,8(sp)
+80000ace:	40b2                	lw	ra,12(sp)
+80000ad0:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ad2:	fff48593          	addi	a1,s1,-1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000ad6:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ad8:	08450513          	addi	a0,a0,132
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000adc:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:59
+            HAL_set_16bit_reg( this_gpio->base_addr, IRQ1, (uint16_t)CLEAR_ALL_IRQ16 );
+80000ade:	bd11                	j	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:63
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ0, (uint8_t)CLEAR_ALL_IRQ8 );
+80000ae0:	4008                	lw	a0,0(s0)
+80000ae2:	0ff00593          	li	a1,255
+80000ae6:	08050513          	addi	a0,a0,128
+80000aea:	3589                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:64
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ1, (uint8_t)CLEAR_ALL_IRQ8 );
+80000aec:	4008                	lw	a0,0(s0)
+80000aee:	0ff00593          	li	a1,255
+80000af2:	08450513          	addi	a0,a0,132
+80000af6:	3d1d                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:65
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ2, (uint8_t)CLEAR_ALL_IRQ8 );
+80000af8:	4008                	lw	a0,0(s0)
+80000afa:	0ff00593          	li	a1,255
+80000afe:	08850513          	addi	a0,a0,136
+80000b02:	352d                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b04:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b06:	4422                	lw	s0,8(sp)
+80000b08:	40b2                	lw	ra,12(sp)
+80000b0a:	4492                	lw	s1,4(sp)
+80000b0c:	4902                	lw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b0e:	0ff00593          	li	a1,255
+80000b12:	08c50513          	addi	a0,a0,140
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b16:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:66
+            HAL_set_8bit_reg( this_gpio->base_addr, IRQ3, (uint8_t)CLEAR_ALL_IRQ8 );
+80000b18:	bd11                	j	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:73
+}
+80000b1a:	40b2                	lw	ra,12(sp)
+80000b1c:	4422                	lw	s0,8(sp)
+80000b1e:	4492                	lw	s1,4(sp)
+80000b20:	4902                	lw	s2,0(sp)
+80000b22:	0141                	addi	sp,sp,16
+80000b24:	8082                	ret
+
+80000b26 <GPIO_set_outputs>:
+GPIO_set_outputs():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+(
+    gpio_instance_t *   this_gpio,
+    uint32_t            value
+)
+{
+    switch( this_gpio->apb_bus_width )
+80000b26:	415c                	lw	a5,4(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+80000b28:	1141                	addi	sp,sp,-16
+80000b2a:	c422                	sw	s0,8(sp)
+80000b2c:	c226                	sw	s1,4(sp)
+80000b2e:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+80000b30:	4705                	li	a4,1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:114
+{
+80000b32:	842a                	mv	s0,a0
+80000b34:	84ae                	mv	s1,a1
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:115
+    switch( this_gpio->apb_bus_width )
+80000b36:	00e78e63          	beq	a5,a4,80000b52 <GPIO_set_outputs+0x2c>
+80000b3a:	cf85                	beqz	a5,80000b72 <GPIO_set_outputs+0x4c>
+80000b3c:	4709                	li	a4,2
+80000b3e:	06e79a63          	bne	a5,a4,80000bb2 <GPIO_set_outputs+0x8c>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+    {
+        case GPIO_APB_32_BITS_BUS:
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b42:	4108                	lw	a0,0(a0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+     * the number of GPIOs selected in the CoreGPIO hardware flow configuration.
+     * It may also indicate that the base address or APB bus width passed as
+     * parameter to the GPIO_init() function do not match the hardware design.
+     */
+    HAL_ASSERT( GPIO_get_outputs( this_gpio ) == value );
+}
+80000b44:	4422                	lw	s0,8(sp)
+80000b46:	40b2                	lw	ra,12(sp)
+80000b48:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b4a:	0a050513          	addi	a0,a0,160
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b4e:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:118
+            HAL_set_32bit_reg( this_gpio->base_addr, GPIO_OUT, value );
+80000b50:	b3bd                	j	800008be <HW_set_32bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:122
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint16_t)value );
+80000b52:	4108                	lw	a0,0(a0)
+80000b54:	05c2                	slli	a1,a1,0x10
+80000b56:	81c1                	srli	a1,a1,0x10
+80000b58:	0a050513          	addi	a0,a0,160
+80000b5c:	3b59                	jal	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b5e:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b60:	4422                	lw	s0,8(sp)
+80000b62:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b64:	0104d593          	srli	a1,s1,0x10
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b68:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b6a:	0a450513          	addi	a0,a0,164
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000b6e:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:123
+            HAL_set_16bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint16_t)(value >> 16) );
+80000b70:	b349                	j	800008f2 <HW_set_16bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:127
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT0, (uint8_t)value );
+80000b72:	4108                	lw	a0,0(a0)
+80000b74:	0ff5f593          	andi	a1,a1,255
+80000b78:	0a050513          	addi	a0,a0,160
+80000b7c:	3b45                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:128
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT1, (uint8_t)(value >> 8) );
+80000b7e:	4008                	lw	a0,0(s0)
+80000b80:	0084d593          	srli	a1,s1,0x8
+80000b84:	0ff5f593          	andi	a1,a1,255
+80000b88:	0a450513          	addi	a0,a0,164
+80000b8c:	3345                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:129
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT2, (uint8_t)(value >> 16) );
+80000b8e:	4008                	lw	a0,0(s0)
+80000b90:	0104d593          	srli	a1,s1,0x10
+80000b94:	0ff5f593          	andi	a1,a1,255
+80000b98:	0a850513          	addi	a0,a0,168
+80000b9c:	3b41                	jal	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000b9e:	4008                	lw	a0,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000ba0:	4422                	lw	s0,8(sp)
+80000ba2:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000ba4:	0184d593          	srli	a1,s1,0x18
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000ba8:	4492                	lw	s1,4(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000baa:	0ac50513          	addi	a0,a0,172
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000bae:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:130
+            HAL_set_8bit_reg( this_gpio->base_addr, GPIO_OUT3, (uint8_t)(value >> 24) );
+80000bb0:	bbb5                	j	8000092c <HW_set_8bit_reg>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/platform/drivers/fpga_ip/CoreGPIO/core_gpio.c:146
+}
+80000bb2:	40b2                	lw	ra,12(sp)
+80000bb4:	4422                	lw	s0,8(sp)
+80000bb6:	4492                	lw	s1,4(sp)
+80000bb8:	0141                	addi	sp,sp,16
+80000bba:	8082                	ret
+
+80000bbc <Software_IRQHandler>:
+MRV_clear_soft_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:735
+{
+#ifdef MIV_LEGACY_RV32
+    MSIP = 0x00u;   /* clear soft interrupt */
+#else
+    /* Clear soft IRQ on MIV_RV32 processor */
+    SUBSYS->soft_reg &= ~SUBSYS_SOFT_IRQ;
+80000bbc:	6719                	lui	a4,0x6
+80000bbe:	531c                	lw	a5,32(a4)
+80000bc0:	9bf5                	andi	a5,a5,-3
+80000bc2:	d31c                	sw	a5,32(a4)
+Software_IRQHandler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:45
+ * in miv_rv32_stubs.c.
+ */
+void Software_IRQHandler()
+{
+    MRV_clear_soft_irq();
+}
+80000bc4:	8082                	ret
+
+80000bc6 <SysTick_Handler>:
+SysTick_Handler():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+ * Toggles the LEDs on the board through the GPIO and counts the number of Ticks
+ * that have occured and prints the interrupt count in message on the UART.
+ */
+
+void SysTick_Handler(void)
+{
+80000bc6:	1141                	addi	sp,sp,-16
+80000bc8:	c422                	sw	s0,8(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    static uint32_t interrupt_counter = 0;
+    interrupt_counter++;
+80000bca:	88418413          	addi	s0,gp,-1916 # 80004084 <interrupt_counter.2878>
+80000bce:	401c                	lw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:54
+{
+80000bd0:	c606                	sw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    static volatile uint32_t val = 0u;
+    val ^= 0xFu;
+    GPIO_set_outputs(&g_gpio_out, val);
+80000bd2:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:56
+    interrupt_counter++;
+80000bd6:	0785                	addi	a5,a5,1
+80000bd8:	c01c                	sw	a5,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:58
+    val ^= 0xFu;
+80000bda:	88818793          	addi	a5,gp,-1912 # 80004088 <val.2879>
+80000bde:	4398                	lw	a4,0(a5)
+80000be0:	00f74713          	xori	a4,a4,15
+80000be4:	c398                	sw	a4,0(a5)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:59
+    GPIO_set_outputs(&g_gpio_out, val);
+80000be6:	438c                	lw	a1,0(a5)
+80000be8:	3f3d                	jal	80000b26 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bea:	400c                	lw	a1,0(s0)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+80000bec:	4422                	lw	s0,8(sp)
+80000bee:	40b2                	lw	ra,12(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bf0:	00001517          	auipc	a0,0x1
+80000bf4:	20050513          	addi	a0,a0,512 # 80001df0 <local_irq_handler_table+0x40>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:61
+}
+80000bf8:	0141                	addi	sp,sp,16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:60
+    printf("\r\nInternal System Timer Interrupt Counter = %d", interrupt_counter);
+80000bfa:	a849                	j	80000c8c <iprintf>
+
+80000bfc <main>:
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+
+/*-------------------------------------------------------------------------//**
+  main() function.
+*/
+int main(void)
+{
+80000bfc:	1141                	addi	sp,sp,-16
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    uint8_t rx_char;
+    uint8_t rx_count;
+    uint32_t switches;
+
+    UART_init(&g_uart,
+80000bfe:	4685                	li	a3,1
+80000c00:	4669                	li	a2,26
+80000c02:	710005b7          	lui	a1,0x71000
+80000c06:	8e818513          	addi	a0,gp,-1816 # 800040e8 <g_uart>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:67
+{
+80000c0a:	c606                	sw	ra,12(sp)
+80000c0c:	c422                	sw	s0,8(sp)
+80000c0e:	c226                	sw	s1,4(sp)
+80000c10:	c04a                	sw	s2,0(sp)
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:72
+    UART_init(&g_uart,
+80000c12:	3b91                	jal	80000966 <UART_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:77
+              COREUARTAPB0_BASE_ADDR,
+              BAUD_VALUE_115200,
+              (DATA_8_BITS | NO_PARITY));
+
+    printf(g_hello_msg);
+80000c14:	00003797          	auipc	a5,0x3
+80000c18:	3f078793          	addi	a5,a5,1008 # 80004004 <g_hello_msg>
+80000c1c:	4388                	lw	a0,0(a5)
+80000c1e:	20bd                	jal	80000c8c <iprintf>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:80
+
+    /* Initializing GPIOs */
+    GPIO_init(&g_gpio_out, COREGPIO_OUT_BASE_ADDR, GPIO_APB_32_BITS_BUS);
+80000c20:	4609                	li	a2,2
+80000c22:	750005b7          	lui	a1,0x75000
+80000c26:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+80000c2a:	35b1                	jal	80000a76 <GPIO_init>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:98
+	 * GPIO_config(&g_gpio_out, 0, GPIO_OUTPUT_MODE);
+     * GPIO_config(&g_gpio_out, 1, GPIO_OUTPUT_MODE);
+	 */
+
+    /* set the output value */
+    GPIO_set_outputs(&g_gpio_out, 0x0u);
+80000c2c:	4581                	li	a1,0
+80000c2e:	8e018513          	addi	a0,gp,-1824 # 800040e0 <g_gpio_out>
+80000c32:	3dd5                	jal	80000b26 <GPIO_set_outputs>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:101
+
+    /* This must be done for all Mi-V cores to enable interrupts globally. */
+    HAL_enable_interrupts();
+80000c34:	3151                	jal	800008b8 <HAL_enable_interrupts>
+MRV_enable_local_irq():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\src\platform/miv_rv32_hal/miv_rv32_hal.h:587
+    set_csr(mie, mask);
+80000c36:	070007b7          	lui	a5,0x7000
+80000c3a:	3047a7f3          	csrrs	a5,mie,a5
+main():
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:107
+
+#ifndef MIV_LEGACY_RV32
+    MRV_enable_local_irq(MRV32_MSYS_EIE0_IRQn | MRV32_MSYS_EIE1_IRQn | MRV32_MSYS_EIE2_IRQn);
+#endif
+
+    MRV_systick_config(SYS_CLK_FREQ);
+80000c3e:	02faf537          	lui	a0,0x2faf
+80000c42:	08050513          	addi	a0,a0,128 # 2faf080 <STACK_SIZE+0x2faec80>
+80000c46:	4581                	li	a1,0
+80000c48:	348d                	jal	800006aa <MRV_systick_config>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:114
+    /**************************************************************************
+    * Loop
+    *************************************************************************/
+    do
+    {
+        g_rx_size = UART_get_rx(&g_uart, g_rx_buff, sizeof(g_rx_buff));
+80000c4a:	8a018493          	addi	s1,gp,-1888 # 800040a0 <__sbss_end>
+80000c4e:	8e818413          	addi	s0,gp,-1816 # 800040e8 <g_uart>
+80000c52:	88018913          	addi	s2,gp,-1920 # 80004080 <g_rx_size>
+80000c56:	04000613          	li	a2,64
+80000c5a:	8a018593          	addi	a1,gp,-1888 # 800040a0 <__sbss_end>
+80000c5e:	8522                	mv	a0,s0
+80000c60:	3b85                	jal	800009d0 <UART_get_rx>
+80000c62:	88a18023          	sb	a0,-1920(gp) # 80004080 <g_rx_size>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:116
+
+        if (g_rx_size > 0u)
+80000c66:	00094783          	lbu	a5,0(s2)
+80000c6a:	0ff7f793          	andi	a5,a5,255
+80000c6e:	d7e5                	beqz	a5,80000c56 <main+0x5a>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:119
+        {
+            /* Echo the characters received from the terminal */
+            UART_polled_tx_string(&g_uart, (const uint8_t *)g_rx_buff);
+80000c70:	85a6                	mv	a1,s1
+80000c72:	8522                	mv	a0,s0
+80000c74:	33e9                	jal	80000a3e <UART_polled_tx_string>
+C:\Microchip\SoftConsole-v2022.2-RISC-V-747\extras\workspace.examples\miv-rv32i-systick-blinky\miv32imc-Release/../src/application/main.c:120
+            g_rx_size = 0u;
+80000c76:	88018023          	sb	zero,-1920(gp) # 80004080 <g_rx_size>
+80000c7a:	bff1                	j	80000c56 <main+0x5a>
+
+80000c7c <memset>:
+memset():
+80000c7c:	832a                	mv	t1,a0
+80000c7e:	c611                	beqz	a2,80000c8a <memset+0xe>
+80000c80:	00b30023          	sb	a1,0(t1)
+80000c84:	167d                	addi	a2,a2,-1
+80000c86:	0305                	addi	t1,t1,1
+80000c88:	fe65                	bnez	a2,80000c80 <memset+0x4>
+80000c8a:	8082                	ret
+
+80000c8c <iprintf>:
+printf():
+80000c8c:	7139                	addi	sp,sp,-64
+80000c8e:	da3e                	sw	a5,52(sp)
+80000c90:	d22e                	sw	a1,36(sp)
+80000c92:	d432                	sw	a2,40(sp)
+80000c94:	d636                	sw	a3,44(sp)
+80000c96:	d83a                	sw	a4,48(sp)
+80000c98:	dc42                	sw	a6,56(sp)
+80000c9a:	de46                	sw	a7,60(sp)
+80000c9c:	00003797          	auipc	a5,0x3
+80000ca0:	36c78793          	addi	a5,a5,876 # 80004008 <_impure_ptr>
+80000ca4:	cc22                	sw	s0,24(sp)
+80000ca6:	4380                	lw	s0,0(a5)
+80000ca8:	ca26                	sw	s1,20(sp)
+80000caa:	ce06                	sw	ra,28(sp)
+80000cac:	84aa                	mv	s1,a0
+80000cae:	c409                	beqz	s0,80000cb8 <iprintf+0x2c>
+80000cb0:	4c1c                	lw	a5,24(s0)
+80000cb2:	e399                	bnez	a5,80000cb8 <iprintf+0x2c>
+80000cb4:	8522                	mv	a0,s0
+80000cb6:	28f5                	jal	80000db2 <__sinit>
+80000cb8:	440c                	lw	a1,8(s0)
+80000cba:	1054                	addi	a3,sp,36
+80000cbc:	8626                	mv	a2,s1
+80000cbe:	8522                	mv	a0,s0
+80000cc0:	c636                	sw	a3,12(sp)
+80000cc2:	264d                	jal	80001064 <_vfiprintf_r>
+80000cc4:	40f2                	lw	ra,28(sp)
+80000cc6:	4462                	lw	s0,24(sp)
+80000cc8:	44d2                	lw	s1,20(sp)
+80000cca:	6121                	addi	sp,sp,64
+80000ccc:	8082                	ret
+
+80000cce <isatty>:
+isatty():
+80000cce:	be55                	j	80000882 <_isatty>
+
+80000cd0 <_write_r>:
+_write_r():
+80000cd0:	1141                	addi	sp,sp,-16
+80000cd2:	c422                	sw	s0,8(sp)
+80000cd4:	842a                	mv	s0,a0
+80000cd6:	852e                	mv	a0,a1
+80000cd8:	85b2                	mv	a1,a2
+80000cda:	8636                	mv	a2,a3
+80000cdc:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80000ce0:	c606                	sw	ra,12(sp)
+80000ce2:	3ec9                	jal	800008b4 <_write>
+80000ce4:	57fd                	li	a5,-1
+80000ce6:	00f51763          	bne	a0,a5,80000cf4 <_write_r+0x24>
+80000cea:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80000cee:	439c                	lw	a5,0(a5)
+80000cf0:	c391                	beqz	a5,80000cf4 <_write_r+0x24>
+80000cf2:	c01c                	sw	a5,0(s0)
+80000cf4:	40b2                	lw	ra,12(sp)
+80000cf6:	4422                	lw	s0,8(sp)
+80000cf8:	0141                	addi	sp,sp,16
+80000cfa:	8082                	ret
+
+80000cfc <std>:
+std():
+80000cfc:	1141                	addi	sp,sp,-16
+80000cfe:	c422                	sw	s0,8(sp)
+80000d00:	c606                	sw	ra,12(sp)
+80000d02:	842a                	mv	s0,a0
+80000d04:	00b51623          	sh	a1,12(a0)
+80000d08:	00c51723          	sh	a2,14(a0)
+80000d0c:	00052023          	sw	zero,0(a0)
+80000d10:	00052223          	sw	zero,4(a0)
+80000d14:	00052423          	sw	zero,8(a0)
+80000d18:	06052223          	sw	zero,100(a0)
+80000d1c:	00052823          	sw	zero,16(a0)
+80000d20:	00052a23          	sw	zero,20(a0)
+80000d24:	00052c23          	sw	zero,24(a0)
+80000d28:	4621                	li	a2,8
+80000d2a:	4581                	li	a1,0
+80000d2c:	05c50513          	addi	a0,a0,92
+80000d30:	37b1                	jal	80000c7c <memset>
+80000d32:	00001797          	auipc	a5,0x1
+80000d36:	9a678793          	addi	a5,a5,-1626 # 800016d8 <__sread>
+80000d3a:	d05c                	sw	a5,36(s0)
+80000d3c:	00001797          	auipc	a5,0x1
+80000d40:	9cc78793          	addi	a5,a5,-1588 # 80001708 <__swrite>
+80000d44:	d41c                	sw	a5,40(s0)
+80000d46:	00001797          	auipc	a5,0x1
+80000d4a:	a1278793          	addi	a5,a5,-1518 # 80001758 <__sseek>
+80000d4e:	d45c                	sw	a5,44(s0)
+80000d50:	00001797          	auipc	a5,0x1
+80000d54:	a3e78793          	addi	a5,a5,-1474 # 8000178e <__sclose>
+80000d58:	d000                	sw	s0,32(s0)
+80000d5a:	d81c                	sw	a5,48(s0)
+80000d5c:	40b2                	lw	ra,12(sp)
+80000d5e:	4422                	lw	s0,8(sp)
+80000d60:	0141                	addi	sp,sp,16
+80000d62:	8082                	ret
+
+80000d64 <_cleanup_r>:
+_cleanup_r():
+80000d64:	00001597          	auipc	a1,0x1
+80000d68:	d7858593          	addi	a1,a1,-648 # 80001adc <_fflush_r>
+80000d6c:	a2b9                	j	80000eba <_fwalk_reent>
+
+80000d6e <__sfmoreglue>:
+__sfmoreglue():
+80000d6e:	1141                	addi	sp,sp,-16
+80000d70:	c226                	sw	s1,4(sp)
+80000d72:	06800613          	li	a2,104
+80000d76:	fff58493          	addi	s1,a1,-1
+80000d7a:	02c484b3          	mul	s1,s1,a2
+80000d7e:	c04a                	sw	s2,0(sp)
+80000d80:	892e                	mv	s2,a1
+80000d82:	c422                	sw	s0,8(sp)
+80000d84:	c606                	sw	ra,12(sp)
+80000d86:	07448593          	addi	a1,s1,116
+80000d8a:	2a71                	jal	80000f26 <_malloc_r>
+80000d8c:	842a                	mv	s0,a0
+80000d8e:	c919                	beqz	a0,80000da4 <__sfmoreglue+0x36>
+80000d90:	00052023          	sw	zero,0(a0)
+80000d94:	01252223          	sw	s2,4(a0)
+80000d98:	0531                	addi	a0,a0,12
+80000d9a:	c408                	sw	a0,8(s0)
+80000d9c:	06848613          	addi	a2,s1,104
+80000da0:	4581                	li	a1,0
+80000da2:	3de9                	jal	80000c7c <memset>
+80000da4:	8522                	mv	a0,s0
+80000da6:	40b2                	lw	ra,12(sp)
+80000da8:	4422                	lw	s0,8(sp)
+80000daa:	4492                	lw	s1,4(sp)
+80000dac:	4902                	lw	s2,0(sp)
+80000dae:	0141                	addi	sp,sp,16
+80000db0:	8082                	ret
+
+80000db2 <__sinit>:
+__sinit():
+80000db2:	4d1c                	lw	a5,24(a0)
+80000db4:	e3bd                	bnez	a5,80000e1a <__sinit+0x68>
+80000db6:	1141                	addi	sp,sp,-16
+80000db8:	c606                	sw	ra,12(sp)
+80000dba:	c422                	sw	s0,8(sp)
+80000dbc:	00000797          	auipc	a5,0x0
+80000dc0:	fa878793          	addi	a5,a5,-88 # 80000d64 <_cleanup_r>
+80000dc4:	d51c                	sw	a5,40(a0)
+80000dc6:	00001797          	auipc	a5,0x1
+80000dca:	26a78793          	addi	a5,a5,618 # 80002030 <_global_impure_ptr>
+80000dce:	439c                	lw	a5,0(a5)
+80000dd0:	04052423          	sw	zero,72(a0)
+80000dd4:	04052623          	sw	zero,76(a0)
+80000dd8:	04052823          	sw	zero,80(a0)
+80000ddc:	00f51463          	bne	a0,a5,80000de4 <__sinit+0x32>
+80000de0:	4785                	li	a5,1
+80000de2:	cd1c                	sw	a5,24(a0)
+80000de4:	842a                	mv	s0,a0
+80000de6:	281d                	jal	80000e1c <__sfp>
+80000de8:	c048                	sw	a0,4(s0)
+80000dea:	8522                	mv	a0,s0
+80000dec:	2805                	jal	80000e1c <__sfp>
+80000dee:	c408                	sw	a0,8(s0)
+80000df0:	8522                	mv	a0,s0
+80000df2:	202d                	jal	80000e1c <__sfp>
+80000df4:	c448                	sw	a0,12(s0)
+80000df6:	4048                	lw	a0,4(s0)
+80000df8:	4601                	li	a2,0
+80000dfa:	4591                	li	a1,4
+80000dfc:	3701                	jal	80000cfc <std>
+80000dfe:	4408                	lw	a0,8(s0)
+80000e00:	4605                	li	a2,1
+80000e02:	45a5                	li	a1,9
+80000e04:	3de5                	jal	80000cfc <std>
+80000e06:	4448                	lw	a0,12(s0)
+80000e08:	4609                	li	a2,2
+80000e0a:	45c9                	li	a1,18
+80000e0c:	3dc5                	jal	80000cfc <std>
+80000e0e:	4785                	li	a5,1
+80000e10:	cc1c                	sw	a5,24(s0)
+80000e12:	40b2                	lw	ra,12(sp)
+80000e14:	4422                	lw	s0,8(sp)
+80000e16:	0141                	addi	sp,sp,16
+80000e18:	8082                	ret
+80000e1a:	8082                	ret
+
+80000e1c <__sfp>:
+__sfp():
+80000e1c:	1141                	addi	sp,sp,-16
+80000e1e:	00001797          	auipc	a5,0x1
+80000e22:	21278793          	addi	a5,a5,530 # 80002030 <_global_impure_ptr>
+80000e26:	c226                	sw	s1,4(sp)
+80000e28:	4384                	lw	s1,0(a5)
+80000e2a:	c04a                	sw	s2,0(sp)
+80000e2c:	c606                	sw	ra,12(sp)
+80000e2e:	4c9c                	lw	a5,24(s1)
+80000e30:	c422                	sw	s0,8(sp)
+80000e32:	892a                	mv	s2,a0
+80000e34:	e399                	bnez	a5,80000e3a <__sfp+0x1e>
+80000e36:	8526                	mv	a0,s1
+80000e38:	3fad                	jal	80000db2 <__sinit>
+80000e3a:	04848493          	addi	s1,s1,72
+80000e3e:	4480                	lw	s0,8(s1)
+80000e40:	40dc                	lw	a5,4(s1)
+80000e42:	17fd                	addi	a5,a5,-1
+80000e44:	0007d663          	bgez	a5,80000e50 <__sfp+0x34>
+80000e48:	409c                	lw	a5,0(s1)
+80000e4a:	cfb1                	beqz	a5,80000ea6 <__sfp+0x8a>
+80000e4c:	4084                	lw	s1,0(s1)
+80000e4e:	bfc5                	j	80000e3e <__sfp+0x22>
+80000e50:	00c41703          	lh	a4,12(s0)
+80000e54:	e731                	bnez	a4,80000ea0 <__sfp+0x84>
+80000e56:	77c1                	lui	a5,0xffff0
+80000e58:	0785                	addi	a5,a5,1
+80000e5a:	06042223          	sw	zero,100(s0)
+80000e5e:	00042023          	sw	zero,0(s0)
+80000e62:	00042223          	sw	zero,4(s0)
+80000e66:	00042423          	sw	zero,8(s0)
+80000e6a:	c45c                	sw	a5,12(s0)
+80000e6c:	00042823          	sw	zero,16(s0)
+80000e70:	00042a23          	sw	zero,20(s0)
+80000e74:	00042c23          	sw	zero,24(s0)
+80000e78:	4621                	li	a2,8
+80000e7a:	4581                	li	a1,0
+80000e7c:	05c40513          	addi	a0,s0,92
+80000e80:	3bf5                	jal	80000c7c <memset>
+80000e82:	02042a23          	sw	zero,52(s0)
+80000e86:	02042c23          	sw	zero,56(s0)
+80000e8a:	04042423          	sw	zero,72(s0)
+80000e8e:	04042623          	sw	zero,76(s0)
+80000e92:	8522                	mv	a0,s0
+80000e94:	40b2                	lw	ra,12(sp)
+80000e96:	4422                	lw	s0,8(sp)
+80000e98:	4492                	lw	s1,4(sp)
+80000e9a:	4902                	lw	s2,0(sp)
+80000e9c:	0141                	addi	sp,sp,16
+80000e9e:	8082                	ret
+80000ea0:	06840413          	addi	s0,s0,104
+80000ea4:	bf79                	j	80000e42 <__sfp+0x26>
+80000ea6:	4591                	li	a1,4
+80000ea8:	854a                	mv	a0,s2
+80000eaa:	35d1                	jal	80000d6e <__sfmoreglue>
+80000eac:	c088                	sw	a0,0(s1)
+80000eae:	842a                	mv	s0,a0
+80000eb0:	fd51                	bnez	a0,80000e4c <__sfp+0x30>
+80000eb2:	47b1                	li	a5,12
+80000eb4:	00f92023          	sw	a5,0(s2)
+80000eb8:	bfe9                	j	80000e92 <__sfp+0x76>
+
+80000eba <_fwalk_reent>:
+_fwalk_reent():
+80000eba:	7179                	addi	sp,sp,-48
+80000ebc:	d422                	sw	s0,40(sp)
+80000ebe:	d04a                	sw	s2,32(sp)
+80000ec0:	cc52                	sw	s4,24(sp)
+80000ec2:	ca56                	sw	s5,20(sp)
+80000ec4:	c85a                	sw	s6,16(sp)
+80000ec6:	c65e                	sw	s7,12(sp)
+80000ec8:	d606                	sw	ra,44(sp)
+80000eca:	d226                	sw	s1,36(sp)
+80000ecc:	ce4e                	sw	s3,28(sp)
+80000ece:	8a2a                	mv	s4,a0
+80000ed0:	8aae                	mv	s5,a1
+80000ed2:	04850413          	addi	s0,a0,72
+80000ed6:	4901                	li	s2,0
+80000ed8:	4b05                	li	s6,1
+80000eda:	5bfd                	li	s7,-1
+80000edc:	ec09                	bnez	s0,80000ef6 <_fwalk_reent+0x3c>
+80000ede:	50b2                	lw	ra,44(sp)
+80000ee0:	5422                	lw	s0,40(sp)
+80000ee2:	854a                	mv	a0,s2
+80000ee4:	5492                	lw	s1,36(sp)
+80000ee6:	5902                	lw	s2,32(sp)
+80000ee8:	49f2                	lw	s3,28(sp)
+80000eea:	4a62                	lw	s4,24(sp)
+80000eec:	4ad2                	lw	s5,20(sp)
+80000eee:	4b42                	lw	s6,16(sp)
+80000ef0:	4bb2                	lw	s7,12(sp)
+80000ef2:	6145                	addi	sp,sp,48
+80000ef4:	8082                	ret
+80000ef6:	4404                	lw	s1,8(s0)
+80000ef8:	00442983          	lw	s3,4(s0)
+80000efc:	19fd                	addi	s3,s3,-1
+80000efe:	0009d463          	bgez	s3,80000f06 <_fwalk_reent+0x4c>
+80000f02:	4000                	lw	s0,0(s0)
+80000f04:	bfe1                	j	80000edc <_fwalk_reent+0x22>
+80000f06:	00c4d783          	lhu	a5,12(s1)
+80000f0a:	00fb7b63          	bgeu	s6,a5,80000f20 <_fwalk_reent+0x66>
+80000f0e:	00e49783          	lh	a5,14(s1)
+80000f12:	01778763          	beq	a5,s7,80000f20 <_fwalk_reent+0x66>
+80000f16:	85a6                	mv	a1,s1
+80000f18:	8552                	mv	a0,s4
+80000f1a:	9a82                	jalr	s5
+80000f1c:	00a96933          	or	s2,s2,a0
+80000f20:	06848493          	addi	s1,s1,104
+80000f24:	bfe1                	j	80000efc <_fwalk_reent+0x42>
+
+80000f26 <_malloc_r>:
+_malloc_r():
+80000f26:	1101                	addi	sp,sp,-32
+80000f28:	ca26                	sw	s1,20(sp)
+80000f2a:	00358493          	addi	s1,a1,3
+80000f2e:	98f1                	andi	s1,s1,-4
+80000f30:	ce06                	sw	ra,28(sp)
+80000f32:	cc22                	sw	s0,24(sp)
+80000f34:	c84a                	sw	s2,16(sp)
+80000f36:	c64e                	sw	s3,12(sp)
+80000f38:	04a1                	addi	s1,s1,8
+80000f3a:	47b1                	li	a5,12
+80000f3c:	04f4f363          	bgeu	s1,a5,80000f82 <_malloc_r+0x5c>
+80000f40:	44b1                	li	s1,12
+80000f42:	04b4e263          	bltu	s1,a1,80000f86 <_malloc_r+0x60>
+80000f46:	892a                	mv	s2,a0
+80000f48:	539000ef          	jal	ra,80001c80 <__malloc_lock>
+80000f4c:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+80000f50:	4398                	lw	a4,0(a5)
+80000f52:	843a                	mv	s0,a4
+80000f54:	e039                	bnez	s0,80000f9a <_malloc_r+0x74>
+80000f56:	89018793          	addi	a5,gp,-1904 # 80004090 <__malloc_sbrk_start>
+80000f5a:	439c                	lw	a5,0(a5)
+80000f5c:	e791                	bnez	a5,80000f68 <_malloc_r+0x42>
+80000f5e:	4581                	li	a1,0
+80000f60:	854a                	mv	a0,s2
+80000f62:	27b1                	jal	800016ae <_sbrk_r>
+80000f64:	88a1a823          	sw	a0,-1904(gp) # 80004090 <__malloc_sbrk_start>
+80000f68:	85a6                	mv	a1,s1
+80000f6a:	854a                	mv	a0,s2
+80000f6c:	2789                	jal	800016ae <_sbrk_r>
+80000f6e:	59fd                	li	s3,-1
+80000f70:	07351963          	bne	a0,s3,80000fe2 <_malloc_r+0xbc>
+80000f74:	47b1                	li	a5,12
+80000f76:	00f92023          	sw	a5,0(s2)
+80000f7a:	854a                	mv	a0,s2
+80000f7c:	507000ef          	jal	ra,80001c82 <__malloc_unlock>
+80000f80:	a029                	j	80000f8a <_malloc_r+0x64>
+80000f82:	fc04d0e3          	bgez	s1,80000f42 <_malloc_r+0x1c>
+80000f86:	47b1                	li	a5,12
+80000f88:	c11c                	sw	a5,0(a0)
+80000f8a:	4501                	li	a0,0
+80000f8c:	40f2                	lw	ra,28(sp)
+80000f8e:	4462                	lw	s0,24(sp)
+80000f90:	44d2                	lw	s1,20(sp)
+80000f92:	4942                	lw	s2,16(sp)
+80000f94:	49b2                	lw	s3,12(sp)
+80000f96:	6105                	addi	sp,sp,32
+80000f98:	8082                	ret
+80000f9a:	401c                	lw	a5,0(s0)
+80000f9c:	8f85                	sub	a5,a5,s1
+80000f9e:	0207cf63          	bltz	a5,80000fdc <_malloc_r+0xb6>
+80000fa2:	46ad                	li	a3,11
+80000fa4:	00f6f663          	bgeu	a3,a5,80000fb0 <_malloc_r+0x8a>
+80000fa8:	c01c                	sw	a5,0(s0)
+80000faa:	943e                	add	s0,s0,a5
+80000fac:	c004                	sw	s1,0(s0)
+80000fae:	a031                	j	80000fba <_malloc_r+0x94>
+80000fb0:	405c                	lw	a5,4(s0)
+80000fb2:	02871363          	bne	a4,s0,80000fd8 <_malloc_r+0xb2>
+80000fb6:	88f1a623          	sw	a5,-1908(gp) # 8000408c <__malloc_free_list>
+80000fba:	854a                	mv	a0,s2
+80000fbc:	4c7000ef          	jal	ra,80001c82 <__malloc_unlock>
+80000fc0:	00b40513          	addi	a0,s0,11
+80000fc4:	00440793          	addi	a5,s0,4
+80000fc8:	9961                	andi	a0,a0,-8
+80000fca:	40f50733          	sub	a4,a0,a5
+80000fce:	df5d                	beqz	a4,80000f8c <_malloc_r+0x66>
+80000fd0:	943a                	add	s0,s0,a4
+80000fd2:	8f89                	sub	a5,a5,a0
+80000fd4:	c01c                	sw	a5,0(s0)
+80000fd6:	bf5d                	j	80000f8c <_malloc_r+0x66>
+80000fd8:	c35c                	sw	a5,4(a4)
+80000fda:	b7c5                	j	80000fba <_malloc_r+0x94>
+80000fdc:	8722                	mv	a4,s0
+80000fde:	4040                	lw	s0,4(s0)
+80000fe0:	bf95                	j	80000f54 <_malloc_r+0x2e>
+80000fe2:	00350413          	addi	s0,a0,3
+80000fe6:	9871                	andi	s0,s0,-4
+80000fe8:	fc8502e3          	beq	a0,s0,80000fac <_malloc_r+0x86>
+80000fec:	40a405b3          	sub	a1,s0,a0
+80000ff0:	854a                	mv	a0,s2
+80000ff2:	2d75                	jal	800016ae <_sbrk_r>
+80000ff4:	fb351ce3          	bne	a0,s3,80000fac <_malloc_r+0x86>
+80000ff8:	bfb5                	j	80000f74 <_malloc_r+0x4e>
+
+80000ffa <__sfputc_r>:
+__sfputc_r():
+80000ffa:	461c                	lw	a5,8(a2)
+80000ffc:	17fd                	addi	a5,a5,-1
+80000ffe:	c61c                	sw	a5,8(a2)
+80001000:	0007d963          	bgez	a5,80001012 <__sfputc_r+0x18>
+80001004:	4e18                	lw	a4,24(a2)
+80001006:	00e7c563          	blt	a5,a4,80001010 <__sfputc_r+0x16>
+8000100a:	47a9                	li	a5,10
+8000100c:	00f59363          	bne	a1,a5,80001012 <__sfputc_r+0x18>
+80001010:	a751                	j	80001794 <__swbuf_r>
+80001012:	421c                	lw	a5,0(a2)
+80001014:	852e                	mv	a0,a1
+80001016:	00178713          	addi	a4,a5,1 # ffff0001 <__global_pointer$+0x7ffeb801>
+8000101a:	c218                	sw	a4,0(a2)
+8000101c:	00b78023          	sb	a1,0(a5)
+80001020:	8082                	ret
+
+80001022 <__sfputs_r>:
+__sfputs_r():
+80001022:	1101                	addi	sp,sp,-32
+80001024:	cc22                	sw	s0,24(sp)
+80001026:	ca26                	sw	s1,20(sp)
+80001028:	c84a                	sw	s2,16(sp)
+8000102a:	c64e                	sw	s3,12(sp)
+8000102c:	c452                	sw	s4,8(sp)
+8000102e:	ce06                	sw	ra,28(sp)
+80001030:	892a                	mv	s2,a0
+80001032:	89ae                	mv	s3,a1
+80001034:	8432                	mv	s0,a2
+80001036:	00d604b3          	add	s1,a2,a3
+8000103a:	5a7d                	li	s4,-1
+8000103c:	00941463          	bne	s0,s1,80001044 <__sfputs_r+0x22>
+80001040:	4501                	li	a0,0
+80001042:	a809                	j	80001054 <__sfputs_r+0x32>
+80001044:	00044583          	lbu	a1,0(s0)
+80001048:	864e                	mv	a2,s3
+8000104a:	854a                	mv	a0,s2
+8000104c:	377d                	jal	80000ffa <__sfputc_r>
+8000104e:	0405                	addi	s0,s0,1
+80001050:	ff4516e3          	bne	a0,s4,8000103c <__sfputs_r+0x1a>
+80001054:	40f2                	lw	ra,28(sp)
+80001056:	4462                	lw	s0,24(sp)
+80001058:	44d2                	lw	s1,20(sp)
+8000105a:	4942                	lw	s2,16(sp)
+8000105c:	49b2                	lw	s3,12(sp)
+8000105e:	4a22                	lw	s4,8(sp)
+80001060:	6105                	addi	sp,sp,32
+80001062:	8082                	ret
+
+80001064 <_vfiprintf_r>:
+_vfiprintf_r():
+80001064:	7135                	addi	sp,sp,-160
+80001066:	cd22                	sw	s0,152(sp)
+80001068:	cb26                	sw	s1,148(sp)
+8000106a:	c94a                	sw	s2,144(sp)
+8000106c:	c74e                	sw	s3,140(sp)
+8000106e:	cf06                	sw	ra,156(sp)
+80001070:	c552                	sw	s4,136(sp)
+80001072:	c356                	sw	s5,132(sp)
+80001074:	c15a                	sw	s6,128(sp)
+80001076:	dede                	sw	s7,124(sp)
+80001078:	dce2                	sw	s8,120(sp)
+8000107a:	dae6                	sw	s9,116(sp)
+8000107c:	89aa                	mv	s3,a0
+8000107e:	84ae                	mv	s1,a1
+80001080:	8932                	mv	s2,a2
+80001082:	8436                	mv	s0,a3
+80001084:	c501                	beqz	a0,8000108c <_vfiprintf_r+0x28>
+80001086:	4d1c                	lw	a5,24(a0)
+80001088:	e391                	bnez	a5,8000108c <_vfiprintf_r+0x28>
+8000108a:	3325                	jal	80000db2 <__sinit>
+8000108c:	00001797          	auipc	a5,0x1
+80001090:	f2078793          	addi	a5,a5,-224 # 80001fac <__sf_fake_stdin>
+80001094:	0cf49c63          	bne	s1,a5,8000116c <_vfiprintf_r+0x108>
+80001098:	0049a483          	lw	s1,4(s3)
+8000109c:	00c4d783          	lhu	a5,12(s1)
+800010a0:	8ba1                	andi	a5,a5,8
+800010a2:	c7fd                	beqz	a5,80001190 <_vfiprintf_r+0x12c>
+800010a4:	489c                	lw	a5,16(s1)
+800010a6:	c7ed                	beqz	a5,80001190 <_vfiprintf_r+0x12c>
+800010a8:	02000793          	li	a5,32
+800010ac:	02f104a3          	sb	a5,41(sp)
+800010b0:	03000793          	li	a5,48
+800010b4:	d202                	sw	zero,36(sp)
+800010b6:	02f10523          	sb	a5,42(sp)
+800010ba:	c622                	sw	s0,12(sp)
+800010bc:	02500b93          	li	s7,37
+800010c0:	00001a97          	auipc	s5,0x1
+800010c4:	f2ca8a93          	addi	s5,s5,-212 # 80001fec <__sf_fake_stdout+0x20>
+800010c8:	4c05                	li	s8,1
+800010ca:	4b29                	li	s6,10
+800010cc:	844a                	mv	s0,s2
+800010ce:	00044783          	lbu	a5,0(s0)
+800010d2:	c399                	beqz	a5,800010d8 <_vfiprintf_r+0x74>
+800010d4:	0f779063          	bne	a5,s7,800011b4 <_vfiprintf_r+0x150>
+800010d8:	41240cb3          	sub	s9,s0,s2
+800010dc:	000c8d63          	beqz	s9,800010f6 <_vfiprintf_r+0x92>
+800010e0:	86e6                	mv	a3,s9
+800010e2:	864a                	mv	a2,s2
+800010e4:	85a6                	mv	a1,s1
+800010e6:	854e                	mv	a0,s3
+800010e8:	3f2d                	jal	80001022 <__sfputs_r>
+800010ea:	57fd                	li	a5,-1
+800010ec:	1ef50863          	beq	a0,a5,800012dc <_vfiprintf_r+0x278>
+800010f0:	5692                	lw	a3,36(sp)
+800010f2:	96e6                	add	a3,a3,s9
+800010f4:	d236                	sw	a3,36(sp)
+800010f6:	00044783          	lbu	a5,0(s0)
+800010fa:	1e078163          	beqz	a5,800012dc <_vfiprintf_r+0x278>
+800010fe:	57fd                	li	a5,-1
+80001100:	00140913          	addi	s2,s0,1
+80001104:	c802                	sw	zero,16(sp)
+80001106:	ce02                	sw	zero,28(sp)
+80001108:	ca3e                	sw	a5,20(sp)
+8000110a:	cc02                	sw	zero,24(sp)
+8000110c:	040109a3          	sb	zero,83(sp)
+80001110:	d482                	sw	zero,104(sp)
+80001112:	00094583          	lbu	a1,0(s2)
+80001116:	4615                	li	a2,5
+80001118:	8556                	mv	a0,s5
+8000111a:	34d000ef          	jal	ra,80001c66 <memchr>
+8000111e:	00190413          	addi	s0,s2,1
+80001122:	47c2                	lw	a5,16(sp)
+80001124:	e951                	bnez	a0,800011b8 <_vfiprintf_r+0x154>
+80001126:	0107f713          	andi	a4,a5,16
+8000112a:	c709                	beqz	a4,80001134 <_vfiprintf_r+0xd0>
+8000112c:	02000713          	li	a4,32
+80001130:	04e109a3          	sb	a4,83(sp)
+80001134:	0087f713          	andi	a4,a5,8
+80001138:	c709                	beqz	a4,80001142 <_vfiprintf_r+0xde>
+8000113a:	02b00713          	li	a4,43
+8000113e:	04e109a3          	sb	a4,83(sp)
+80001142:	00094683          	lbu	a3,0(s2)
+80001146:	02a00713          	li	a4,42
+8000114a:	06e68f63          	beq	a3,a4,800011c8 <_vfiprintf_r+0x164>
+8000114e:	47f2                	lw	a5,28(sp)
+80001150:	844a                	mv	s0,s2
+80001152:	4681                	li	a3,0
+80001154:	4625                	li	a2,9
+80001156:	00044703          	lbu	a4,0(s0)
+8000115a:	00140593          	addi	a1,s0,1
+8000115e:	fd070713          	addi	a4,a4,-48 # 5fd0 <STACK_SIZE+0x5bd0>
+80001162:	0ae67863          	bgeu	a2,a4,80001212 <_vfiprintf_r+0x1ae>
+80001166:	caad                	beqz	a3,800011d8 <_vfiprintf_r+0x174>
+80001168:	ce3e                	sw	a5,28(sp)
+8000116a:	a0bd                	j	800011d8 <_vfiprintf_r+0x174>
+8000116c:	00001797          	auipc	a5,0x1
+80001170:	e6078793          	addi	a5,a5,-416 # 80001fcc <__sf_fake_stdout>
+80001174:	00f49563          	bne	s1,a5,8000117e <_vfiprintf_r+0x11a>
+80001178:	0089a483          	lw	s1,8(s3)
+8000117c:	b705                	j	8000109c <_vfiprintf_r+0x38>
+8000117e:	00001797          	auipc	a5,0x1
+80001182:	e0e78793          	addi	a5,a5,-498 # 80001f8c <__sf_fake_stderr>
+80001186:	f0f49be3          	bne	s1,a5,8000109c <_vfiprintf_r+0x38>
+8000118a:	00c9a483          	lw	s1,12(s3)
+8000118e:	b739                	j	8000109c <_vfiprintf_r+0x38>
+80001190:	85a6                	mv	a1,s1
+80001192:	854e                	mv	a0,s3
+80001194:	25c9                	jal	80001856 <__swsetup_r>
+80001196:	d909                	beqz	a0,800010a8 <_vfiprintf_r+0x44>
+80001198:	557d                	li	a0,-1
+8000119a:	40fa                	lw	ra,156(sp)
+8000119c:	446a                	lw	s0,152(sp)
+8000119e:	44da                	lw	s1,148(sp)
+800011a0:	494a                	lw	s2,144(sp)
+800011a2:	49ba                	lw	s3,140(sp)
+800011a4:	4a2a                	lw	s4,136(sp)
+800011a6:	4a9a                	lw	s5,132(sp)
+800011a8:	4b0a                	lw	s6,128(sp)
+800011aa:	5bf6                	lw	s7,124(sp)
+800011ac:	5c66                	lw	s8,120(sp)
+800011ae:	5cd6                	lw	s9,116(sp)
+800011b0:	610d                	addi	sp,sp,160
+800011b2:	8082                	ret
+800011b4:	0405                	addi	s0,s0,1
+800011b6:	bf21                	j	800010ce <_vfiprintf_r+0x6a>
+800011b8:	41550533          	sub	a0,a0,s5
+800011bc:	00ac1533          	sll	a0,s8,a0
+800011c0:	8fc9                	or	a5,a5,a0
+800011c2:	c83e                	sw	a5,16(sp)
+800011c4:	8922                	mv	s2,s0
+800011c6:	b7b1                	j	80001112 <_vfiprintf_r+0xae>
+800011c8:	4732                	lw	a4,12(sp)
+800011ca:	00470693          	addi	a3,a4,4
+800011ce:	4318                	lw	a4,0(a4)
+800011d0:	c636                	sw	a3,12(sp)
+800011d2:	02074963          	bltz	a4,80001204 <_vfiprintf_r+0x1a0>
+800011d6:	ce3a                	sw	a4,28(sp)
+800011d8:	00044703          	lbu	a4,0(s0)
+800011dc:	02e00793          	li	a5,46
+800011e0:	04f71f63          	bne	a4,a5,8000123e <_vfiprintf_r+0x1da>
+800011e4:	00144703          	lbu	a4,1(s0)
+800011e8:	02a00793          	li	a5,42
+800011ec:	02f71b63          	bne	a4,a5,80001222 <_vfiprintf_r+0x1be>
+800011f0:	47b2                	lw	a5,12(sp)
+800011f2:	0409                	addi	s0,s0,2
+800011f4:	00478713          	addi	a4,a5,4
+800011f8:	439c                	lw	a5,0(a5)
+800011fa:	c63a                	sw	a4,12(sp)
+800011fc:	0207c163          	bltz	a5,8000121e <_vfiprintf_r+0x1ba>
+80001200:	ca3e                	sw	a5,20(sp)
+80001202:	a835                	j	8000123e <_vfiprintf_r+0x1da>
+80001204:	40e00733          	neg	a4,a4
+80001208:	0027e793          	ori	a5,a5,2
+8000120c:	ce3a                	sw	a4,28(sp)
+8000120e:	c83e                	sw	a5,16(sp)
+80001210:	b7e1                	j	800011d8 <_vfiprintf_r+0x174>
+80001212:	036787b3          	mul	a5,a5,s6
+80001216:	4685                	li	a3,1
+80001218:	842e                	mv	s0,a1
+8000121a:	97ba                	add	a5,a5,a4
+8000121c:	bf2d                	j	80001156 <_vfiprintf_r+0xf2>
+8000121e:	57fd                	li	a5,-1
+80001220:	b7c5                	j	80001200 <_vfiprintf_r+0x19c>
+80001222:	0405                	addi	s0,s0,1
+80001224:	ca02                	sw	zero,20(sp)
+80001226:	4681                	li	a3,0
+80001228:	4781                	li	a5,0
+8000122a:	4625                	li	a2,9
+8000122c:	00044703          	lbu	a4,0(s0)
+80001230:	00140593          	addi	a1,s0,1
+80001234:	fd070713          	addi	a4,a4,-48
+80001238:	06e67863          	bgeu	a2,a4,800012a8 <_vfiprintf_r+0x244>
+8000123c:	f2f1                	bnez	a3,80001200 <_vfiprintf_r+0x19c>
+8000123e:	00044583          	lbu	a1,0(s0)
+80001242:	460d                	li	a2,3
+80001244:	00001517          	auipc	a0,0x1
+80001248:	db050513          	addi	a0,a0,-592 # 80001ff4 <__sf_fake_stdout+0x28>
+8000124c:	21b000ef          	jal	ra,80001c66 <memchr>
+80001250:	cd11                	beqz	a0,8000126c <_vfiprintf_r+0x208>
+80001252:	00001797          	auipc	a5,0x1
+80001256:	da278793          	addi	a5,a5,-606 # 80001ff4 <__sf_fake_stdout+0x28>
+8000125a:	8d1d                	sub	a0,a0,a5
+8000125c:	04000793          	li	a5,64
+80001260:	00a797b3          	sll	a5,a5,a0
+80001264:	4542                	lw	a0,16(sp)
+80001266:	0405                	addi	s0,s0,1
+80001268:	8d5d                	or	a0,a0,a5
+8000126a:	c82a                	sw	a0,16(sp)
+8000126c:	00044583          	lbu	a1,0(s0)
+80001270:	4619                	li	a2,6
+80001272:	00001517          	auipc	a0,0x1
+80001276:	d8650513          	addi	a0,a0,-634 # 80001ff8 <__sf_fake_stdout+0x2c>
+8000127a:	00140913          	addi	s2,s0,1
+8000127e:	02b10423          	sb	a1,40(sp)
+80001282:	1e5000ef          	jal	ra,80001c66 <memchr>
+80001286:	c13d                	beqz	a0,800012ec <_vfiprintf_r+0x288>
+80001288:	7ffff797          	auipc	a5,0x7ffff
+8000128c:	d7878793          	addi	a5,a5,-648 # 0 <__global_pointer$+0x7fffb800>
+80001290:	e795                	bnez	a5,800012bc <_vfiprintf_r+0x258>
+80001292:	4742                	lw	a4,16(sp)
+80001294:	47b2                	lw	a5,12(sp)
+80001296:	10077713          	andi	a4,a4,256
+8000129a:	cf09                	beqz	a4,800012b4 <_vfiprintf_r+0x250>
+8000129c:	0791                	addi	a5,a5,4
+8000129e:	c63e                	sw	a5,12(sp)
+800012a0:	5792                	lw	a5,36(sp)
+800012a2:	97d2                	add	a5,a5,s4
+800012a4:	d23e                	sw	a5,36(sp)
+800012a6:	b51d                	j	800010cc <_vfiprintf_r+0x68>
+800012a8:	036787b3          	mul	a5,a5,s6
+800012ac:	4685                	li	a3,1
+800012ae:	842e                	mv	s0,a1
+800012b0:	97ba                	add	a5,a5,a4
+800012b2:	bfad                	j	8000122c <_vfiprintf_r+0x1c8>
+800012b4:	079d                	addi	a5,a5,7
+800012b6:	9be1                	andi	a5,a5,-8
+800012b8:	07a1                	addi	a5,a5,8
+800012ba:	b7d5                	j	8000129e <_vfiprintf_r+0x23a>
+800012bc:	0078                	addi	a4,sp,12
+800012be:	00000697          	auipc	a3,0x0
+800012c2:	d6468693          	addi	a3,a3,-668 # 80001022 <__sfputs_r>
+800012c6:	8626                	mv	a2,s1
+800012c8:	080c                	addi	a1,sp,16
+800012ca:	854e                	mv	a0,s3
+800012cc:	00000097          	auipc	ra,0x0
+800012d0:	000000e7          	jalr	zero # 0 <HEAP_SIZE>
+800012d4:	57fd                	li	a5,-1
+800012d6:	8a2a                	mv	s4,a0
+800012d8:	fcf514e3          	bne	a0,a5,800012a0 <_vfiprintf_r+0x23c>
+800012dc:	00c4d783          	lhu	a5,12(s1)
+800012e0:	0407f793          	andi	a5,a5,64
+800012e4:	ea079ae3          	bnez	a5,80001198 <_vfiprintf_r+0x134>
+800012e8:	5512                	lw	a0,36(sp)
+800012ea:	bd45                	j	8000119a <_vfiprintf_r+0x136>
+800012ec:	0078                	addi	a4,sp,12
+800012ee:	00000697          	auipc	a3,0x0
+800012f2:	d3468693          	addi	a3,a3,-716 # 80001022 <__sfputs_r>
+800012f6:	8626                	mv	a2,s1
+800012f8:	080c                	addi	a1,sp,16
+800012fa:	854e                	mv	a0,s3
+800012fc:	2a01                	jal	8000140c <_printf_i>
+800012fe:	bfd9                	j	800012d4 <_vfiprintf_r+0x270>
+
+80001300 <_printf_common>:
+_printf_common():
+80001300:	7179                	addi	sp,sp,-48
+80001302:	ca56                	sw	s5,20(sp)
+80001304:	499c                	lw	a5,16(a1)
+80001306:	8aba                	mv	s5,a4
+80001308:	4598                	lw	a4,8(a1)
+8000130a:	d422                	sw	s0,40(sp)
+8000130c:	d226                	sw	s1,36(sp)
+8000130e:	ce4e                	sw	s3,28(sp)
+80001310:	cc52                	sw	s4,24(sp)
+80001312:	d606                	sw	ra,44(sp)
+80001314:	d04a                	sw	s2,32(sp)
+80001316:	c85a                	sw	s6,16(sp)
+80001318:	c65e                	sw	s7,12(sp)
+8000131a:	89aa                	mv	s3,a0
+8000131c:	842e                	mv	s0,a1
+8000131e:	84b2                	mv	s1,a2
+80001320:	8a36                	mv	s4,a3
+80001322:	00e7d363          	bge	a5,a4,80001328 <_printf_common+0x28>
+80001326:	87ba                	mv	a5,a4
+80001328:	c09c                	sw	a5,0(s1)
+8000132a:	04344703          	lbu	a4,67(s0)
+8000132e:	c319                	beqz	a4,80001334 <_printf_common+0x34>
+80001330:	0785                	addi	a5,a5,1
+80001332:	c09c                	sw	a5,0(s1)
+80001334:	401c                	lw	a5,0(s0)
+80001336:	0207f793          	andi	a5,a5,32
+8000133a:	c781                	beqz	a5,80001342 <_printf_common+0x42>
+8000133c:	409c                	lw	a5,0(s1)
+8000133e:	0789                	addi	a5,a5,2
+80001340:	c09c                	sw	a5,0(s1)
+80001342:	00042903          	lw	s2,0(s0)
+80001346:	00697913          	andi	s2,s2,6
+8000134a:	00091a63          	bnez	s2,8000135e <_printf_common+0x5e>
+8000134e:	01940b13          	addi	s6,s0,25
+80001352:	5bfd                	li	s7,-1
+80001354:	445c                	lw	a5,12(s0)
+80001356:	4098                	lw	a4,0(s1)
+80001358:	8f99                	sub	a5,a5,a4
+8000135a:	04f94c63          	blt	s2,a5,800013b2 <_printf_common+0xb2>
+8000135e:	401c                	lw	a5,0(s0)
+80001360:	04344683          	lbu	a3,67(s0)
+80001364:	0207f793          	andi	a5,a5,32
+80001368:	00d036b3          	snez	a3,a3
+8000136c:	eba5                	bnez	a5,800013dc <_printf_common+0xdc>
+8000136e:	04340613          	addi	a2,s0,67
+80001372:	85d2                	mv	a1,s4
+80001374:	854e                	mv	a0,s3
+80001376:	9a82                	jalr	s5
+80001378:	57fd                	li	a5,-1
+8000137a:	04f50363          	beq	a0,a5,800013c0 <_printf_common+0xc0>
+8000137e:	401c                	lw	a5,0(s0)
+80001380:	4611                	li	a2,4
+80001382:	4098                	lw	a4,0(s1)
+80001384:	8b99                	andi	a5,a5,6
+80001386:	4454                	lw	a3,12(s0)
+80001388:	4481                	li	s1,0
+8000138a:	00c79763          	bne	a5,a2,80001398 <_printf_common+0x98>
+8000138e:	40e684b3          	sub	s1,a3,a4
+80001392:	0004d363          	bgez	s1,80001398 <_printf_common+0x98>
+80001396:	4481                	li	s1,0
+80001398:	441c                	lw	a5,8(s0)
+8000139a:	4818                	lw	a4,16(s0)
+8000139c:	00f75463          	bge	a4,a5,800013a4 <_printf_common+0xa4>
+800013a0:	8f99                	sub	a5,a5,a4
+800013a2:	94be                	add	s1,s1,a5
+800013a4:	4901                	li	s2,0
+800013a6:	0469                	addi	s0,s0,26
+800013a8:	5b7d                	li	s6,-1
+800013aa:	05249863          	bne	s1,s2,800013fa <_printf_common+0xfa>
+800013ae:	4501                	li	a0,0
+800013b0:	a809                	j	800013c2 <_printf_common+0xc2>
+800013b2:	4685                	li	a3,1
+800013b4:	865a                	mv	a2,s6
+800013b6:	85d2                	mv	a1,s4
+800013b8:	854e                	mv	a0,s3
+800013ba:	9a82                	jalr	s5
+800013bc:	01751e63          	bne	a0,s7,800013d8 <_printf_common+0xd8>
+800013c0:	557d                	li	a0,-1
+800013c2:	50b2                	lw	ra,44(sp)
+800013c4:	5422                	lw	s0,40(sp)
+800013c6:	5492                	lw	s1,36(sp)
+800013c8:	5902                	lw	s2,32(sp)
+800013ca:	49f2                	lw	s3,28(sp)
+800013cc:	4a62                	lw	s4,24(sp)
+800013ce:	4ad2                	lw	s5,20(sp)
+800013d0:	4b42                	lw	s6,16(sp)
+800013d2:	4bb2                	lw	s7,12(sp)
+800013d4:	6145                	addi	sp,sp,48
+800013d6:	8082                	ret
+800013d8:	0905                	addi	s2,s2,1
+800013da:	bfad                	j	80001354 <_printf_common+0x54>
+800013dc:	00d40733          	add	a4,s0,a3
+800013e0:	03000613          	li	a2,48
+800013e4:	04c701a3          	sb	a2,67(a4)
+800013e8:	04544703          	lbu	a4,69(s0)
+800013ec:	00168793          	addi	a5,a3,1
+800013f0:	97a2                	add	a5,a5,s0
+800013f2:	0689                	addi	a3,a3,2
+800013f4:	04e781a3          	sb	a4,67(a5)
+800013f8:	bf9d                	j	8000136e <_printf_common+0x6e>
+800013fa:	4685                	li	a3,1
+800013fc:	8622                	mv	a2,s0
+800013fe:	85d2                	mv	a1,s4
+80001400:	854e                	mv	a0,s3
+80001402:	9a82                	jalr	s5
+80001404:	fb650ee3          	beq	a0,s6,800013c0 <_printf_common+0xc0>
+80001408:	0905                	addi	s2,s2,1
+8000140a:	b745                	j	800013aa <_printf_common+0xaa>
+
+8000140c <_printf_i>:
+_printf_i():
+8000140c:	7179                	addi	sp,sp,-48
+8000140e:	d422                	sw	s0,40(sp)
+80001410:	d226                	sw	s1,36(sp)
+80001412:	d04a                	sw	s2,32(sp)
+80001414:	ce4e                	sw	s3,28(sp)
+80001416:	d606                	sw	ra,44(sp)
+80001418:	cc52                	sw	s4,24(sp)
+8000141a:	ca56                	sw	s5,20(sp)
+8000141c:	c85a                	sw	s6,16(sp)
+8000141e:	89b6                	mv	s3,a3
+80001420:	0185c683          	lbu	a3,24(a1)
+80001424:	06e00793          	li	a5,110
+80001428:	8932                	mv	s2,a2
+8000142a:	84aa                	mv	s1,a0
+8000142c:	842e                	mv	s0,a1
+8000142e:	04358613          	addi	a2,a1,67
+80001432:	1ef68063          	beq	a3,a5,80001612 <_printf_i+0x206>
+80001436:	06d7e263          	bltu	a5,a3,8000149a <_printf_i+0x8e>
+8000143a:	06300793          	li	a5,99
+8000143e:	0af68263          	beq	a3,a5,800014e2 <_printf_i+0xd6>
+80001442:	00d7ed63          	bltu	a5,a3,8000145c <_printf_i+0x50>
+80001446:	1e068a63          	beqz	a3,8000163a <_printf_i+0x22e>
+8000144a:	05800793          	li	a5,88
+8000144e:	16f68663          	beq	a3,a5,800015ba <_printf_i+0x1ae>
+80001452:	04240a93          	addi	s5,s0,66
+80001456:	04d40123          	sb	a3,66(s0)
+8000145a:	a869                	j	800014f4 <_printf_i+0xe8>
+8000145c:	06400793          	li	a5,100
+80001460:	00f68663          	beq	a3,a5,8000146c <_printf_i+0x60>
+80001464:	06900793          	li	a5,105
+80001468:	fef695e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+8000146c:	401c                	lw	a5,0(s0)
+8000146e:	4308                	lw	a0,0(a4)
+80001470:	0807f693          	andi	a3,a5,128
+80001474:	00450593          	addi	a1,a0,4
+80001478:	c2c1                	beqz	a3,800014f8 <_printf_i+0xec>
+8000147a:	411c                	lw	a5,0(a0)
+8000147c:	c30c                	sw	a1,0(a4)
+8000147e:	0007d863          	bgez	a5,8000148e <_printf_i+0x82>
+80001482:	02d00713          	li	a4,45
+80001486:	40f007b3          	neg	a5,a5
+8000148a:	04e401a3          	sb	a4,67(s0)
+8000148e:	00001697          	auipc	a3,0x1
+80001492:	b7268693          	addi	a3,a3,-1166 # 80002000 <__sf_fake_stdout+0x34>
+80001496:	4729                	li	a4,10
+80001498:	a065                	j	80001540 <_printf_i+0x134>
+8000149a:	07300793          	li	a5,115
+8000149e:	1af68263          	beq	a3,a5,80001642 <_printf_i+0x236>
+800014a2:	00d7ef63          	bltu	a5,a3,800014c0 <_printf_i+0xb4>
+800014a6:	06f00793          	li	a5,111
+800014aa:	04f68f63          	beq	a3,a5,80001508 <_printf_i+0xfc>
+800014ae:	07000793          	li	a5,112
+800014b2:	faf690e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+800014b6:	419c                	lw	a5,0(a1)
+800014b8:	0207e793          	ori	a5,a5,32
+800014bc:	c19c                	sw	a5,0(a1)
+800014be:	a809                	j	800014d0 <_printf_i+0xc4>
+800014c0:	07500793          	li	a5,117
+800014c4:	04f68263          	beq	a3,a5,80001508 <_printf_i+0xfc>
+800014c8:	07800793          	li	a5,120
+800014cc:	f8f693e3          	bne	a3,a5,80001452 <_printf_i+0x46>
+800014d0:	07800793          	li	a5,120
+800014d4:	04f402a3          	sb	a5,69(s0)
+800014d8:	00001697          	auipc	a3,0x1
+800014dc:	b3c68693          	addi	a3,a3,-1220 # 80002014 <__sf_fake_stdout+0x48>
+800014e0:	a0dd                	j	800015c6 <_printf_i+0x1ba>
+800014e2:	431c                	lw	a5,0(a4)
+800014e4:	04258a93          	addi	s5,a1,66
+800014e8:	00478693          	addi	a3,a5,4
+800014ec:	439c                	lw	a5,0(a5)
+800014ee:	c314                	sw	a3,0(a4)
+800014f0:	04f58123          	sb	a5,66(a1)
+800014f4:	4785                	li	a5,1
+800014f6:	a2ad                	j	80001660 <_printf_i+0x254>
+800014f8:	0407f693          	andi	a3,a5,64
+800014fc:	411c                	lw	a5,0(a0)
+800014fe:	c30c                	sw	a1,0(a4)
+80001500:	debd                	beqz	a3,8000147e <_printf_i+0x72>
+80001502:	07c2                	slli	a5,a5,0x10
+80001504:	87c1                	srai	a5,a5,0x10
+80001506:	bfa5                	j	8000147e <_printf_i+0x72>
+80001508:	400c                	lw	a1,0(s0)
+8000150a:	431c                	lw	a5,0(a4)
+8000150c:	0805f813          	andi	a6,a1,128
+80001510:	00478513          	addi	a0,a5,4
+80001514:	00080563          	beqz	a6,8000151e <_printf_i+0x112>
+80001518:	c308                	sw	a0,0(a4)
+8000151a:	439c                	lw	a5,0(a5)
+8000151c:	a039                	j	8000152a <_printf_i+0x11e>
+8000151e:	0405f593          	andi	a1,a1,64
+80001522:	c308                	sw	a0,0(a4)
+80001524:	d9fd                	beqz	a1,8000151a <_printf_i+0x10e>
+80001526:	0007d783          	lhu	a5,0(a5)
+8000152a:	06f00713          	li	a4,111
+8000152e:	0ce68a63          	beq	a3,a4,80001602 <_printf_i+0x1f6>
+80001532:	00001697          	auipc	a3,0x1
+80001536:	ace68693          	addi	a3,a3,-1330 # 80002000 <__sf_fake_stdout+0x34>
+8000153a:	4729                	li	a4,10
+8000153c:	040401a3          	sb	zero,67(s0)
+80001540:	404c                	lw	a1,4(s0)
+80001542:	c40c                	sw	a1,8(s0)
+80001544:	0005c563          	bltz	a1,8000154e <_printf_i+0x142>
+80001548:	4008                	lw	a0,0(s0)
+8000154a:	996d                	andi	a0,a0,-5
+8000154c:	c008                	sw	a0,0(s0)
+8000154e:	e399                	bnez	a5,80001554 <_printf_i+0x148>
+80001550:	8ab2                	mv	s5,a2
+80001552:	cd91                	beqz	a1,8000156e <_printf_i+0x162>
+80001554:	8ab2                	mv	s5,a2
+80001556:	02e7f5b3          	remu	a1,a5,a4
+8000155a:	1afd                	addi	s5,s5,-1
+8000155c:	95b6                	add	a1,a1,a3
+8000155e:	0005c583          	lbu	a1,0(a1)
+80001562:	00ba8023          	sb	a1,0(s5)
+80001566:	02e7d5b3          	divu	a1,a5,a4
+8000156a:	0ae7f263          	bgeu	a5,a4,8000160e <_printf_i+0x202>
+8000156e:	47a1                	li	a5,8
+80001570:	00f71e63          	bne	a4,a5,8000158c <_printf_i+0x180>
+80001574:	401c                	lw	a5,0(s0)
+80001576:	8b85                	andi	a5,a5,1
+80001578:	cb91                	beqz	a5,8000158c <_printf_i+0x180>
+8000157a:	4058                	lw	a4,4(s0)
+8000157c:	481c                	lw	a5,16(s0)
+8000157e:	00e7c763          	blt	a5,a4,8000158c <_printf_i+0x180>
+80001582:	03000793          	li	a5,48
+80001586:	fefa8fa3          	sb	a5,-1(s5)
+8000158a:	1afd                	addi	s5,s5,-1
+8000158c:	41560633          	sub	a2,a2,s5
+80001590:	c810                	sw	a2,16(s0)
+80001592:	874e                	mv	a4,s3
+80001594:	86ca                	mv	a3,s2
+80001596:	0070                	addi	a2,sp,12
+80001598:	85a2                	mv	a1,s0
+8000159a:	8526                	mv	a0,s1
+8000159c:	3395                	jal	80001300 <_printf_common>
+8000159e:	5a7d                	li	s4,-1
+800015a0:	0d451463          	bne	a0,s4,80001668 <_printf_i+0x25c>
+800015a4:	557d                	li	a0,-1
+800015a6:	50b2                	lw	ra,44(sp)
+800015a8:	5422                	lw	s0,40(sp)
+800015aa:	5492                	lw	s1,36(sp)
+800015ac:	5902                	lw	s2,32(sp)
+800015ae:	49f2                	lw	s3,28(sp)
+800015b0:	4a62                	lw	s4,24(sp)
+800015b2:	4ad2                	lw	s5,20(sp)
+800015b4:	4b42                	lw	s6,16(sp)
+800015b6:	6145                	addi	sp,sp,48
+800015b8:	8082                	ret
+800015ba:	04d582a3          	sb	a3,69(a1)
+800015be:	00001697          	auipc	a3,0x1
+800015c2:	a4268693          	addi	a3,a3,-1470 # 80002000 <__sf_fake_stdout+0x34>
+800015c6:	400c                	lw	a1,0(s0)
+800015c8:	4308                	lw	a0,0(a4)
+800015ca:	0805f813          	andi	a6,a1,128
+800015ce:	411c                	lw	a5,0(a0)
+800015d0:	0511                	addi	a0,a0,4
+800015d2:	02080063          	beqz	a6,800015f2 <_printf_i+0x1e6>
+800015d6:	c308                	sw	a0,0(a4)
+800015d8:	0015f713          	andi	a4,a1,1
+800015dc:	c701                	beqz	a4,800015e4 <_printf_i+0x1d8>
+800015de:	0205e593          	ori	a1,a1,32
+800015e2:	c00c                	sw	a1,0(s0)
+800015e4:	4741                	li	a4,16
+800015e6:	fbb9                	bnez	a5,8000153c <_printf_i+0x130>
+800015e8:	400c                	lw	a1,0(s0)
+800015ea:	fdf5f593          	andi	a1,a1,-33
+800015ee:	c00c                	sw	a1,0(s0)
+800015f0:	b7b1                	j	8000153c <_printf_i+0x130>
+800015f2:	0405f813          	andi	a6,a1,64
+800015f6:	c308                	sw	a0,0(a4)
+800015f8:	fe0800e3          	beqz	a6,800015d8 <_printf_i+0x1cc>
+800015fc:	07c2                	slli	a5,a5,0x10
+800015fe:	83c1                	srli	a5,a5,0x10
+80001600:	bfe1                	j	800015d8 <_printf_i+0x1cc>
+80001602:	00001697          	auipc	a3,0x1
+80001606:	9fe68693          	addi	a3,a3,-1538 # 80002000 <__sf_fake_stdout+0x34>
+8000160a:	4721                	li	a4,8
+8000160c:	bf05                	j	8000153c <_printf_i+0x130>
+8000160e:	87ae                	mv	a5,a1
+80001610:	b799                	j	80001556 <_printf_i+0x14a>
+80001612:	4194                	lw	a3,0(a1)
+80001614:	431c                	lw	a5,0(a4)
+80001616:	49cc                	lw	a1,20(a1)
+80001618:	0806f813          	andi	a6,a3,128
+8000161c:	00478513          	addi	a0,a5,4
+80001620:	00080663          	beqz	a6,8000162c <_printf_i+0x220>
+80001624:	c308                	sw	a0,0(a4)
+80001626:	439c                	lw	a5,0(a5)
+80001628:	c38c                	sw	a1,0(a5)
+8000162a:	a801                	j	8000163a <_printf_i+0x22e>
+8000162c:	c308                	sw	a0,0(a4)
+8000162e:	0406f693          	andi	a3,a3,64
+80001632:	439c                	lw	a5,0(a5)
+80001634:	daf5                	beqz	a3,80001628 <_printf_i+0x21c>
+80001636:	00b79023          	sh	a1,0(a5)
+8000163a:	00042823          	sw	zero,16(s0)
+8000163e:	8ab2                	mv	s5,a2
+80001640:	bf89                	j	80001592 <_printf_i+0x186>
+80001642:	431c                	lw	a5,0(a4)
+80001644:	41d0                	lw	a2,4(a1)
+80001646:	4581                	li	a1,0
+80001648:	00478693          	addi	a3,a5,4
+8000164c:	c314                	sw	a3,0(a4)
+8000164e:	0007aa83          	lw	s5,0(a5)
+80001652:	8556                	mv	a0,s5
+80001654:	2d09                	jal	80001c66 <memchr>
+80001656:	c501                	beqz	a0,8000165e <_printf_i+0x252>
+80001658:	41550533          	sub	a0,a0,s5
+8000165c:	c048                	sw	a0,4(s0)
+8000165e:	405c                	lw	a5,4(s0)
+80001660:	c81c                	sw	a5,16(s0)
+80001662:	040401a3          	sb	zero,67(s0)
+80001666:	b735                	j	80001592 <_printf_i+0x186>
+80001668:	4814                	lw	a3,16(s0)
+8000166a:	8656                	mv	a2,s5
+8000166c:	85ca                	mv	a1,s2
+8000166e:	8526                	mv	a0,s1
+80001670:	9982                	jalr	s3
+80001672:	f34509e3          	beq	a0,s4,800015a4 <_printf_i+0x198>
+80001676:	401c                	lw	a5,0(s0)
+80001678:	8b89                	andi	a5,a5,2
+8000167a:	e78d                	bnez	a5,800016a4 <_printf_i+0x298>
+8000167c:	47b2                	lw	a5,12(sp)
+8000167e:	4448                	lw	a0,12(s0)
+80001680:	f2f553e3          	bge	a0,a5,800015a6 <_printf_i+0x19a>
+80001684:	853e                	mv	a0,a5
+80001686:	b705                	j	800015a6 <_printf_i+0x19a>
+80001688:	4685                	li	a3,1
+8000168a:	8656                	mv	a2,s5
+8000168c:	85ca                	mv	a1,s2
+8000168e:	8526                	mv	a0,s1
+80001690:	9982                	jalr	s3
+80001692:	f16509e3          	beq	a0,s6,800015a4 <_printf_i+0x198>
+80001696:	0a05                	addi	s4,s4,1
+80001698:	445c                	lw	a5,12(s0)
+8000169a:	4732                	lw	a4,12(sp)
+8000169c:	8f99                	sub	a5,a5,a4
+8000169e:	fefa45e3          	blt	s4,a5,80001688 <_printf_i+0x27c>
+800016a2:	bfe9                	j	8000167c <_printf_i+0x270>
+800016a4:	4a01                	li	s4,0
+800016a6:	01940a93          	addi	s5,s0,25
+800016aa:	5b7d                	li	s6,-1
+800016ac:	b7f5                	j	80001698 <_printf_i+0x28c>
+
+800016ae <_sbrk_r>:
+_sbrk_r():
+800016ae:	1141                	addi	sp,sp,-16
+800016b0:	c422                	sw	s0,8(sp)
+800016b2:	842a                	mv	s0,a0
+800016b4:	852e                	mv	a0,a1
+800016b6:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+800016ba:	c606                	sw	ra,12(sp)
+800016bc:	99aff0ef          	jal	ra,80000856 <_sbrk>
+800016c0:	57fd                	li	a5,-1
+800016c2:	00f51763          	bne	a0,a5,800016d0 <_sbrk_r+0x22>
+800016c6:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+800016ca:	439c                	lw	a5,0(a5)
+800016cc:	c391                	beqz	a5,800016d0 <_sbrk_r+0x22>
+800016ce:	c01c                	sw	a5,0(s0)
+800016d0:	40b2                	lw	ra,12(sp)
+800016d2:	4422                	lw	s0,8(sp)
+800016d4:	0141                	addi	sp,sp,16
+800016d6:	8082                	ret
+
+800016d8 <__sread>:
+__sread():
+800016d8:	1141                	addi	sp,sp,-16
+800016da:	c422                	sw	s0,8(sp)
+800016dc:	842e                	mv	s0,a1
+800016de:	00e59583          	lh	a1,14(a1)
+800016e2:	c606                	sw	ra,12(sp)
+800016e4:	2591                	jal	80001d28 <_read_r>
+800016e6:	00054963          	bltz	a0,800016f8 <__sread+0x20>
+800016ea:	487c                	lw	a5,84(s0)
+800016ec:	97aa                	add	a5,a5,a0
+800016ee:	c87c                	sw	a5,84(s0)
+800016f0:	40b2                	lw	ra,12(sp)
+800016f2:	4422                	lw	s0,8(sp)
+800016f4:	0141                	addi	sp,sp,16
+800016f6:	8082                	ret
+800016f8:	00c45783          	lhu	a5,12(s0)
+800016fc:	777d                	lui	a4,0xfffff
+800016fe:	177d                	addi	a4,a4,-1
+80001700:	8ff9                	and	a5,a5,a4
+80001702:	00f41623          	sh	a5,12(s0)
+80001706:	b7ed                	j	800016f0 <__sread+0x18>
+
+80001708 <__swrite>:
+__swrite():
+80001708:	00c5d783          	lhu	a5,12(a1)
+8000170c:	1101                	addi	sp,sp,-32
+8000170e:	cc22                	sw	s0,24(sp)
+80001710:	ca26                	sw	s1,20(sp)
+80001712:	c84a                	sw	s2,16(sp)
+80001714:	c64e                	sw	s3,12(sp)
+80001716:	ce06                	sw	ra,28(sp)
+80001718:	1007f793          	andi	a5,a5,256
+8000171c:	84aa                	mv	s1,a0
+8000171e:	842e                	mv	s0,a1
+80001720:	8932                	mv	s2,a2
+80001722:	89b6                	mv	s3,a3
+80001724:	c791                	beqz	a5,80001730 <__swrite+0x28>
+80001726:	00e59583          	lh	a1,14(a1)
+8000172a:	4689                	li	a3,2
+8000172c:	4601                	li	a2,0
+8000172e:	2911                	jal	80001b42 <_lseek_r>
+80001730:	00c45783          	lhu	a5,12(s0)
+80001734:	777d                	lui	a4,0xfffff
+80001736:	177d                	addi	a4,a4,-1
+80001738:	8ff9                	and	a5,a5,a4
+8000173a:	00f41623          	sh	a5,12(s0)
+8000173e:	00e41583          	lh	a1,14(s0)
+80001742:	4462                	lw	s0,24(sp)
+80001744:	40f2                	lw	ra,28(sp)
+80001746:	86ce                	mv	a3,s3
+80001748:	864a                	mv	a2,s2
+8000174a:	49b2                	lw	s3,12(sp)
+8000174c:	4942                	lw	s2,16(sp)
+8000174e:	8526                	mv	a0,s1
+80001750:	44d2                	lw	s1,20(sp)
+80001752:	6105                	addi	sp,sp,32
+80001754:	d7cff06f          	j	80000cd0 <_write_r>
+
+80001758 <__sseek>:
+__sseek():
+80001758:	1141                	addi	sp,sp,-16
+8000175a:	c422                	sw	s0,8(sp)
+8000175c:	842e                	mv	s0,a1
+8000175e:	00e59583          	lh	a1,14(a1)
+80001762:	c606                	sw	ra,12(sp)
+80001764:	2ef9                	jal	80001b42 <_lseek_r>
+80001766:	57fd                	li	a5,-1
+80001768:	00c45703          	lhu	a4,12(s0)
+8000176c:	00f51b63          	bne	a0,a5,80001782 <__sseek+0x2a>
+80001770:	77fd                	lui	a5,0xfffff
+80001772:	17fd                	addi	a5,a5,-1
+80001774:	8ff9                	and	a5,a5,a4
+80001776:	00f41623          	sh	a5,12(s0)
+8000177a:	40b2                	lw	ra,12(sp)
+8000177c:	4422                	lw	s0,8(sp)
+8000177e:	0141                	addi	sp,sp,16
+80001780:	8082                	ret
+80001782:	6785                	lui	a5,0x1
+80001784:	8fd9                	or	a5,a5,a4
+80001786:	00f41623          	sh	a5,12(s0)
+8000178a:	c868                	sw	a0,84(s0)
+8000178c:	b7fd                	j	8000177a <__sseek+0x22>
+
+8000178e <__sclose>:
+__sclose():
+8000178e:	00e59583          	lh	a1,14(a1)
+80001792:	aad9                	j	80001968 <_close_r>
+
+80001794 <__swbuf_r>:
+__swbuf_r():
+80001794:	1101                	addi	sp,sp,-32
+80001796:	cc22                	sw	s0,24(sp)
+80001798:	ca26                	sw	s1,20(sp)
+8000179a:	c84a                	sw	s2,16(sp)
+8000179c:	ce06                	sw	ra,28(sp)
+8000179e:	c64e                	sw	s3,12(sp)
+800017a0:	84aa                	mv	s1,a0
+800017a2:	892e                	mv	s2,a1
+800017a4:	8432                	mv	s0,a2
+800017a6:	c509                	beqz	a0,800017b0 <__swbuf_r+0x1c>
+800017a8:	4d1c                	lw	a5,24(a0)
+800017aa:	e399                	bnez	a5,800017b0 <__swbuf_r+0x1c>
+800017ac:	e06ff0ef          	jal	ra,80000db2 <__sinit>
+800017b0:	00000797          	auipc	a5,0x0
+800017b4:	7fc78793          	addi	a5,a5,2044 # 80001fac <__sf_fake_stdin>
+800017b8:	06f41963          	bne	s0,a5,8000182a <__swbuf_r+0x96>
+800017bc:	40c0                	lw	s0,4(s1)
+800017be:	4c1c                	lw	a5,24(s0)
+800017c0:	c41c                	sw	a5,8(s0)
+800017c2:	00c45783          	lhu	a5,12(s0)
+800017c6:	8ba1                	andi	a5,a5,8
+800017c8:	c3c9                	beqz	a5,8000184a <__swbuf_r+0xb6>
+800017ca:	481c                	lw	a5,16(s0)
+800017cc:	cfbd                	beqz	a5,8000184a <__swbuf_r+0xb6>
+800017ce:	481c                	lw	a5,16(s0)
+800017d0:	4008                	lw	a0,0(s0)
+800017d2:	0ff97993          	andi	s3,s2,255
+800017d6:	0ff97913          	andi	s2,s2,255
+800017da:	8d1d                	sub	a0,a0,a5
+800017dc:	485c                	lw	a5,20(s0)
+800017de:	00f54663          	blt	a0,a5,800017ea <__swbuf_r+0x56>
+800017e2:	85a2                	mv	a1,s0
+800017e4:	8526                	mv	a0,s1
+800017e6:	2cdd                	jal	80001adc <_fflush_r>
+800017e8:	e52d                	bnez	a0,80001852 <__swbuf_r+0xbe>
+800017ea:	441c                	lw	a5,8(s0)
+800017ec:	0505                	addi	a0,a0,1
+800017ee:	17fd                	addi	a5,a5,-1
+800017f0:	c41c                	sw	a5,8(s0)
+800017f2:	401c                	lw	a5,0(s0)
+800017f4:	00178713          	addi	a4,a5,1
+800017f8:	c018                	sw	a4,0(s0)
+800017fa:	01378023          	sb	s3,0(a5)
+800017fe:	485c                	lw	a5,20(s0)
+80001800:	00a78963          	beq	a5,a0,80001812 <__swbuf_r+0x7e>
+80001804:	00c45783          	lhu	a5,12(s0)
+80001808:	8b85                	andi	a5,a5,1
+8000180a:	cb81                	beqz	a5,8000181a <__swbuf_r+0x86>
+8000180c:	47a9                	li	a5,10
+8000180e:	00f91663          	bne	s2,a5,8000181a <__swbuf_r+0x86>
+80001812:	85a2                	mv	a1,s0
+80001814:	8526                	mv	a0,s1
+80001816:	24d9                	jal	80001adc <_fflush_r>
+80001818:	ed0d                	bnez	a0,80001852 <__swbuf_r+0xbe>
+8000181a:	40f2                	lw	ra,28(sp)
+8000181c:	4462                	lw	s0,24(sp)
+8000181e:	854a                	mv	a0,s2
+80001820:	44d2                	lw	s1,20(sp)
+80001822:	4942                	lw	s2,16(sp)
+80001824:	49b2                	lw	s3,12(sp)
+80001826:	6105                	addi	sp,sp,32
+80001828:	8082                	ret
+8000182a:	00000797          	auipc	a5,0x0
+8000182e:	7a278793          	addi	a5,a5,1954 # 80001fcc <__sf_fake_stdout>
+80001832:	00f41463          	bne	s0,a5,8000183a <__swbuf_r+0xa6>
+80001836:	4480                	lw	s0,8(s1)
+80001838:	b759                	j	800017be <__swbuf_r+0x2a>
+8000183a:	00000797          	auipc	a5,0x0
+8000183e:	75278793          	addi	a5,a5,1874 # 80001f8c <__sf_fake_stderr>
+80001842:	f6f41ee3          	bne	s0,a5,800017be <__swbuf_r+0x2a>
+80001846:	44c0                	lw	s0,12(s1)
+80001848:	bf9d                	j	800017be <__swbuf_r+0x2a>
+8000184a:	85a2                	mv	a1,s0
+8000184c:	8526                	mv	a0,s1
+8000184e:	2021                	jal	80001856 <__swsetup_r>
+80001850:	dd3d                	beqz	a0,800017ce <__swbuf_r+0x3a>
+80001852:	597d                	li	s2,-1
+80001854:	b7d9                	j	8000181a <__swbuf_r+0x86>
+
+80001856 <__swsetup_r>:
+__swsetup_r():
+80001856:	1141                	addi	sp,sp,-16
+80001858:	00002797          	auipc	a5,0x2
+8000185c:	7b078793          	addi	a5,a5,1968 # 80004008 <_impure_ptr>
+80001860:	c226                	sw	s1,4(sp)
+80001862:	4384                	lw	s1,0(a5)
+80001864:	c422                	sw	s0,8(sp)
+80001866:	c04a                	sw	s2,0(sp)
+80001868:	c606                	sw	ra,12(sp)
+8000186a:	892a                	mv	s2,a0
+8000186c:	842e                	mv	s0,a1
+8000186e:	c491                	beqz	s1,8000187a <__swsetup_r+0x24>
+80001870:	4c9c                	lw	a5,24(s1)
+80001872:	e781                	bnez	a5,8000187a <__swsetup_r+0x24>
+80001874:	8526                	mv	a0,s1
+80001876:	d3cff0ef          	jal	ra,80000db2 <__sinit>
+8000187a:	00000797          	auipc	a5,0x0
+8000187e:	73278793          	addi	a5,a5,1842 # 80001fac <__sf_fake_stdin>
+80001882:	02f41c63          	bne	s0,a5,800018ba <__swsetup_r+0x64>
+80001886:	40c0                	lw	s0,4(s1)
+80001888:	00c41703          	lh	a4,12(s0)
+8000188c:	01071793          	slli	a5,a4,0x10
+80001890:	83c1                	srli	a5,a5,0x10
+80001892:	0087f693          	andi	a3,a5,8
+80001896:	eeb5                	bnez	a3,80001912 <__swsetup_r+0xbc>
+80001898:	0107f693          	andi	a3,a5,16
+8000189c:	ee9d                	bnez	a3,800018da <__swsetup_r+0x84>
+8000189e:	47a5                	li	a5,9
+800018a0:	00f92023          	sw	a5,0(s2)
+800018a4:	04076713          	ori	a4,a4,64
+800018a8:	00e41623          	sh	a4,12(s0)
+800018ac:	557d                	li	a0,-1
+800018ae:	40b2                	lw	ra,12(sp)
+800018b0:	4422                	lw	s0,8(sp)
+800018b2:	4492                	lw	s1,4(sp)
+800018b4:	4902                	lw	s2,0(sp)
+800018b6:	0141                	addi	sp,sp,16
+800018b8:	8082                	ret
+800018ba:	00000797          	auipc	a5,0x0
+800018be:	71278793          	addi	a5,a5,1810 # 80001fcc <__sf_fake_stdout>
+800018c2:	00f41463          	bne	s0,a5,800018ca <__swsetup_r+0x74>
+800018c6:	4480                	lw	s0,8(s1)
+800018c8:	b7c1                	j	80001888 <__swsetup_r+0x32>
+800018ca:	00000797          	auipc	a5,0x0
+800018ce:	6c278793          	addi	a5,a5,1730 # 80001f8c <__sf_fake_stderr>
+800018d2:	faf41be3          	bne	s0,a5,80001888 <__swsetup_r+0x32>
+800018d6:	44c0                	lw	s0,12(s1)
+800018d8:	bf45                	j	80001888 <__swsetup_r+0x32>
+800018da:	8b91                	andi	a5,a5,4
+800018dc:	c78d                	beqz	a5,80001906 <__swsetup_r+0xb0>
+800018de:	584c                	lw	a1,52(s0)
+800018e0:	c989                	beqz	a1,800018f2 <__swsetup_r+0x9c>
+800018e2:	04440793          	addi	a5,s0,68
+800018e6:	00f58463          	beq	a1,a5,800018ee <__swsetup_r+0x98>
+800018ea:	854a                	mv	a0,s2
+800018ec:	2e61                	jal	80001c84 <_free_r>
+800018ee:	02042a23          	sw	zero,52(s0)
+800018f2:	00c45783          	lhu	a5,12(s0)
+800018f6:	00042223          	sw	zero,4(s0)
+800018fa:	fdb7f793          	andi	a5,a5,-37
+800018fe:	00f41623          	sh	a5,12(s0)
+80001902:	481c                	lw	a5,16(s0)
+80001904:	c01c                	sw	a5,0(s0)
+80001906:	00c45783          	lhu	a5,12(s0)
+8000190a:	0087e793          	ori	a5,a5,8
+8000190e:	00f41623          	sh	a5,12(s0)
+80001912:	481c                	lw	a5,16(s0)
+80001914:	ef81                	bnez	a5,8000192c <__swsetup_r+0xd6>
+80001916:	00c45783          	lhu	a5,12(s0)
+8000191a:	20000713          	li	a4,512
+8000191e:	2807f793          	andi	a5,a5,640
+80001922:	00e78563          	beq	a5,a4,8000192c <__swsetup_r+0xd6>
+80001926:	85a2                	mv	a1,s0
+80001928:	854a                	mv	a0,s2
+8000192a:	2c79                	jal	80001bc8 <__smakebuf_r>
+8000192c:	00c45783          	lhu	a5,12(s0)
+80001930:	0017f713          	andi	a4,a5,1
+80001934:	c705                	beqz	a4,8000195c <__swsetup_r+0x106>
+80001936:	485c                	lw	a5,20(s0)
+80001938:	00042423          	sw	zero,8(s0)
+8000193c:	40f007b3          	neg	a5,a5
+80001940:	cc1c                	sw	a5,24(s0)
+80001942:	481c                	lw	a5,16(s0)
+80001944:	4501                	li	a0,0
+80001946:	f7a5                	bnez	a5,800018ae <__swsetup_r+0x58>
+80001948:	00c41783          	lh	a5,12(s0)
+8000194c:	0807f713          	andi	a4,a5,128
+80001950:	df39                	beqz	a4,800018ae <__swsetup_r+0x58>
+80001952:	0407e793          	ori	a5,a5,64
+80001956:	00f41623          	sh	a5,12(s0)
+8000195a:	bf89                	j	800018ac <__swsetup_r+0x56>
+8000195c:	8b89                	andi	a5,a5,2
+8000195e:	4701                	li	a4,0
+80001960:	e391                	bnez	a5,80001964 <__swsetup_r+0x10e>
+80001962:	4858                	lw	a4,20(s0)
+80001964:	c418                	sw	a4,8(s0)
+80001966:	bff1                	j	80001942 <__swsetup_r+0xec>
+
+80001968 <_close_r>:
+_close_r():
+80001968:	1141                	addi	sp,sp,-16
+8000196a:	c422                	sw	s0,8(sp)
+8000196c:	842a                	mv	s0,a0
+8000196e:	852e                	mv	a0,a1
+80001970:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001974:	c606                	sw	ra,12(sp)
+80001976:	f13fe0ef          	jal	ra,80000888 <_close>
+8000197a:	57fd                	li	a5,-1
+8000197c:	00f51763          	bne	a0,a5,8000198a <_close_r+0x22>
+80001980:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001984:	439c                	lw	a5,0(a5)
+80001986:	c391                	beqz	a5,8000198a <_close_r+0x22>
+80001988:	c01c                	sw	a5,0(s0)
+8000198a:	40b2                	lw	ra,12(sp)
+8000198c:	4422                	lw	s0,8(sp)
+8000198e:	0141                	addi	sp,sp,16
+80001990:	8082                	ret
+
+80001992 <__sflush_r>:
+__sflush_r():
+80001992:	00c5d783          	lhu	a5,12(a1)
+80001996:	1101                	addi	sp,sp,-32
+80001998:	cc22                	sw	s0,24(sp)
+8000199a:	ca26                	sw	s1,20(sp)
+8000199c:	ce06                	sw	ra,28(sp)
+8000199e:	c84a                	sw	s2,16(sp)
+800019a0:	c64e                	sw	s3,12(sp)
+800019a2:	0087f713          	andi	a4,a5,8
+800019a6:	84aa                	mv	s1,a0
+800019a8:	842e                	mv	s0,a1
+800019aa:	e765                	bnez	a4,80001a92 <__sflush_r+0x100>
+800019ac:	41d8                	lw	a4,4(a1)
+800019ae:	00e04763          	bgtz	a4,800019bc <__sflush_r+0x2a>
+800019b2:	41b8                	lw	a4,64(a1)
+800019b4:	00e04463          	bgtz	a4,800019bc <__sflush_r+0x2a>
+800019b8:	4501                	li	a0,0
+800019ba:	a0c1                	j	80001a7a <__sflush_r+0xe8>
+800019bc:	5458                	lw	a4,44(s0)
+800019be:	df6d                	beqz	a4,800019b8 <__sflush_r+0x26>
+800019c0:	0004a903          	lw	s2,0(s1)
+800019c4:	01379693          	slli	a3,a5,0x13
+800019c8:	0004a023          	sw	zero,0(s1)
+800019cc:	0606de63          	bgez	a3,80001a48 <__sflush_r+0xb6>
+800019d0:	4868                	lw	a0,84(s0)
+800019d2:	00c45783          	lhu	a5,12(s0)
+800019d6:	8b91                	andi	a5,a5,4
+800019d8:	c799                	beqz	a5,800019e6 <__sflush_r+0x54>
+800019da:	405c                	lw	a5,4(s0)
+800019dc:	8d1d                	sub	a0,a0,a5
+800019de:	585c                	lw	a5,52(s0)
+800019e0:	c399                	beqz	a5,800019e6 <__sflush_r+0x54>
+800019e2:	403c                	lw	a5,64(s0)
+800019e4:	8d1d                	sub	a0,a0,a5
+800019e6:	545c                	lw	a5,44(s0)
+800019e8:	500c                	lw	a1,32(s0)
+800019ea:	862a                	mv	a2,a0
+800019ec:	4681                	li	a3,0
+800019ee:	8526                	mv	a0,s1
+800019f0:	9782                	jalr	a5
+800019f2:	57fd                	li	a5,-1
+800019f4:	00c45703          	lhu	a4,12(s0)
+800019f8:	00f51d63          	bne	a0,a5,80001a12 <__sflush_r+0x80>
+800019fc:	4094                	lw	a3,0(s1)
+800019fe:	47f5                	li	a5,29
+80001a00:	08d7e463          	bltu	a5,a3,80001a88 <__sflush_r+0xf6>
+80001a04:	204007b7          	lui	a5,0x20400
+80001a08:	0785                	addi	a5,a5,1
+80001a0a:	00d7d7b3          	srl	a5,a5,a3
+80001a0e:	8b85                	andi	a5,a5,1
+80001a10:	cfa5                	beqz	a5,80001a88 <__sflush_r+0xf6>
+80001a12:	481c                	lw	a5,16(s0)
+80001a14:	00042223          	sw	zero,4(s0)
+80001a18:	c01c                	sw	a5,0(s0)
+80001a1a:	01371793          	slli	a5,a4,0x13
+80001a1e:	0007d863          	bgez	a5,80001a2e <__sflush_r+0x9c>
+80001a22:	57fd                	li	a5,-1
+80001a24:	00f51463          	bne	a0,a5,80001a2c <__sflush_r+0x9a>
+80001a28:	409c                	lw	a5,0(s1)
+80001a2a:	e391                	bnez	a5,80001a2e <__sflush_r+0x9c>
+80001a2c:	c868                	sw	a0,84(s0)
+80001a2e:	584c                	lw	a1,52(s0)
+80001a30:	0124a023          	sw	s2,0(s1)
+80001a34:	d1d1                	beqz	a1,800019b8 <__sflush_r+0x26>
+80001a36:	04440793          	addi	a5,s0,68
+80001a3a:	00f58463          	beq	a1,a5,80001a42 <__sflush_r+0xb0>
+80001a3e:	8526                	mv	a0,s1
+80001a40:	2491                	jal	80001c84 <_free_r>
+80001a42:	02042a23          	sw	zero,52(s0)
+80001a46:	bf8d                	j	800019b8 <__sflush_r+0x26>
+80001a48:	500c                	lw	a1,32(s0)
+80001a4a:	4685                	li	a3,1
+80001a4c:	4601                	li	a2,0
+80001a4e:	8526                	mv	a0,s1
+80001a50:	9702                	jalr	a4
+80001a52:	57fd                	li	a5,-1
+80001a54:	f6f51fe3          	bne	a0,a5,800019d2 <__sflush_r+0x40>
+80001a58:	409c                	lw	a5,0(s1)
+80001a5a:	dfa5                	beqz	a5,800019d2 <__sflush_r+0x40>
+80001a5c:	4775                	li	a4,29
+80001a5e:	00e78563          	beq	a5,a4,80001a68 <__sflush_r+0xd6>
+80001a62:	4759                	li	a4,22
+80001a64:	00e79563          	bne	a5,a4,80001a6e <__sflush_r+0xdc>
+80001a68:	0124a023          	sw	s2,0(s1)
+80001a6c:	b7b1                	j	800019b8 <__sflush_r+0x26>
+80001a6e:	00c45783          	lhu	a5,12(s0)
+80001a72:	0407e793          	ori	a5,a5,64
+80001a76:	00f41623          	sh	a5,12(s0)
+80001a7a:	40f2                	lw	ra,28(sp)
+80001a7c:	4462                	lw	s0,24(sp)
+80001a7e:	44d2                	lw	s1,20(sp)
+80001a80:	4942                	lw	s2,16(sp)
+80001a82:	49b2                	lw	s3,12(sp)
+80001a84:	6105                	addi	sp,sp,32
+80001a86:	8082                	ret
+80001a88:	04076713          	ori	a4,a4,64
+80001a8c:	00e41623          	sh	a4,12(s0)
+80001a90:	b7ed                	j	80001a7a <__sflush_r+0xe8>
+80001a92:	0105a983          	lw	s3,16(a1)
+80001a96:	f20981e3          	beqz	s3,800019b8 <__sflush_r+0x26>
+80001a9a:	0005a903          	lw	s2,0(a1)
+80001a9e:	8b8d                	andi	a5,a5,3
+80001aa0:	0135a023          	sw	s3,0(a1)
+80001aa4:	41390933          	sub	s2,s2,s3
+80001aa8:	4701                	li	a4,0
+80001aaa:	e391                	bnez	a5,80001aae <__sflush_r+0x11c>
+80001aac:	49d8                	lw	a4,20(a1)
+80001aae:	c418                	sw	a4,8(s0)
+80001ab0:	f12054e3          	blez	s2,800019b8 <__sflush_r+0x26>
+80001ab4:	541c                	lw	a5,40(s0)
+80001ab6:	500c                	lw	a1,32(s0)
+80001ab8:	86ca                	mv	a3,s2
+80001aba:	864e                	mv	a2,s3
+80001abc:	8526                	mv	a0,s1
+80001abe:	9782                	jalr	a5
+80001ac0:	00a04a63          	bgtz	a0,80001ad4 <__sflush_r+0x142>
+80001ac4:	00c45783          	lhu	a5,12(s0)
+80001ac8:	557d                	li	a0,-1
+80001aca:	0407e793          	ori	a5,a5,64
+80001ace:	00f41623          	sh	a5,12(s0)
+80001ad2:	b765                	j	80001a7a <__sflush_r+0xe8>
+80001ad4:	99aa                	add	s3,s3,a0
+80001ad6:	40a90933          	sub	s2,s2,a0
+80001ada:	bfd9                	j	80001ab0 <__sflush_r+0x11e>
+
+80001adc <_fflush_r>:
+_fflush_r():
+80001adc:	499c                	lw	a5,16(a1)
+80001ade:	c3a5                	beqz	a5,80001b3e <_fflush_r+0x62>
+80001ae0:	1101                	addi	sp,sp,-32
+80001ae2:	cc22                	sw	s0,24(sp)
+80001ae4:	ce06                	sw	ra,28(sp)
+80001ae6:	842a                	mv	s0,a0
+80001ae8:	c519                	beqz	a0,80001af6 <_fflush_r+0x1a>
+80001aea:	4d1c                	lw	a5,24(a0)
+80001aec:	e789                	bnez	a5,80001af6 <_fflush_r+0x1a>
+80001aee:	c62e                	sw	a1,12(sp)
+80001af0:	ac2ff0ef          	jal	ra,80000db2 <__sinit>
+80001af4:	45b2                	lw	a1,12(sp)
+80001af6:	00000797          	auipc	a5,0x0
+80001afa:	4b678793          	addi	a5,a5,1206 # 80001fac <__sf_fake_stdin>
+80001afe:	00f59b63          	bne	a1,a5,80001b14 <_fflush_r+0x38>
+80001b02:	404c                	lw	a1,4(s0)
+80001b04:	00c59783          	lh	a5,12(a1)
+80001b08:	c795                	beqz	a5,80001b34 <_fflush_r+0x58>
+80001b0a:	8522                	mv	a0,s0
+80001b0c:	4462                	lw	s0,24(sp)
+80001b0e:	40f2                	lw	ra,28(sp)
+80001b10:	6105                	addi	sp,sp,32
+80001b12:	b541                	j	80001992 <__sflush_r>
+80001b14:	00000797          	auipc	a5,0x0
+80001b18:	4b878793          	addi	a5,a5,1208 # 80001fcc <__sf_fake_stdout>
+80001b1c:	00f59463          	bne	a1,a5,80001b24 <_fflush_r+0x48>
+80001b20:	440c                	lw	a1,8(s0)
+80001b22:	b7cd                	j	80001b04 <_fflush_r+0x28>
+80001b24:	00000797          	auipc	a5,0x0
+80001b28:	46878793          	addi	a5,a5,1128 # 80001f8c <__sf_fake_stderr>
+80001b2c:	fcf59ce3          	bne	a1,a5,80001b04 <_fflush_r+0x28>
+80001b30:	444c                	lw	a1,12(s0)
+80001b32:	bfc9                	j	80001b04 <_fflush_r+0x28>
+80001b34:	40f2                	lw	ra,28(sp)
+80001b36:	4462                	lw	s0,24(sp)
+80001b38:	4501                	li	a0,0
+80001b3a:	6105                	addi	sp,sp,32
+80001b3c:	8082                	ret
+80001b3e:	4501                	li	a0,0
+80001b40:	8082                	ret
+
+80001b42 <_lseek_r>:
+_lseek_r():
+80001b42:	1141                	addi	sp,sp,-16
+80001b44:	c422                	sw	s0,8(sp)
+80001b46:	842a                	mv	s0,a0
+80001b48:	852e                	mv	a0,a1
+80001b4a:	85b2                	mv	a1,a2
+80001b4c:	8636                	mv	a2,a3
+80001b4e:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001b52:	c606                	sw	ra,12(sp)
+80001b54:	d55fe0ef          	jal	ra,800008a8 <_lseek>
+80001b58:	57fd                	li	a5,-1
+80001b5a:	00f51763          	bne	a0,a5,80001b68 <_lseek_r+0x26>
+80001b5e:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001b62:	439c                	lw	a5,0(a5)
+80001b64:	c391                	beqz	a5,80001b68 <_lseek_r+0x26>
+80001b66:	c01c                	sw	a5,0(s0)
+80001b68:	40b2                	lw	ra,12(sp)
+80001b6a:	4422                	lw	s0,8(sp)
+80001b6c:	0141                	addi	sp,sp,16
+80001b6e:	8082                	ret
+
+80001b70 <__swhatbuf_r>:
+__swhatbuf_r():
+80001b70:	7119                	addi	sp,sp,-128
+80001b72:	daa6                	sw	s1,116(sp)
+80001b74:	84ae                	mv	s1,a1
+80001b76:	00e59583          	lh	a1,14(a1)
+80001b7a:	dca2                	sw	s0,120(sp)
+80001b7c:	de86                	sw	ra,124(sp)
+80001b7e:	8432                	mv	s0,a2
+80001b80:	0005dc63          	bgez	a1,80001b98 <__swhatbuf_r+0x28>
+80001b84:	00c4d783          	lhu	a5,12(s1)
+80001b88:	0006a023          	sw	zero,0(a3)
+80001b8c:	0807f793          	andi	a5,a5,128
+80001b90:	e39d                	bnez	a5,80001bb6 <__swhatbuf_r+0x46>
+80001b92:	40000793          	li	a5,1024
+80001b96:	a015                	j	80001bba <__swhatbuf_r+0x4a>
+80001b98:	0830                	addi	a2,sp,24
+80001b9a:	c636                	sw	a3,12(sp)
+80001b9c:	2a6d                	jal	80001d56 <_fstat_r>
+80001b9e:	46b2                	lw	a3,12(sp)
+80001ba0:	fe0542e3          	bltz	a0,80001b84 <__swhatbuf_r+0x14>
+80001ba4:	4772                	lw	a4,28(sp)
+80001ba6:	67bd                	lui	a5,0xf
+80001ba8:	8ff9                	and	a5,a5,a4
+80001baa:	7779                	lui	a4,0xffffe
+80001bac:	97ba                	add	a5,a5,a4
+80001bae:	0017b793          	seqz	a5,a5
+80001bb2:	c29c                	sw	a5,0(a3)
+80001bb4:	bff9                	j	80001b92 <__swhatbuf_r+0x22>
+80001bb6:	04000793          	li	a5,64
+80001bba:	c01c                	sw	a5,0(s0)
+80001bbc:	50f6                	lw	ra,124(sp)
+80001bbe:	5466                	lw	s0,120(sp)
+80001bc0:	54d6                	lw	s1,116(sp)
+80001bc2:	4501                	li	a0,0
+80001bc4:	6109                	addi	sp,sp,128
+80001bc6:	8082                	ret
+
+80001bc8 <__smakebuf_r>:
+__smakebuf_r():
+80001bc8:	00c5d783          	lhu	a5,12(a1)
+80001bcc:	1101                	addi	sp,sp,-32
+80001bce:	cc22                	sw	s0,24(sp)
+80001bd0:	ce06                	sw	ra,28(sp)
+80001bd2:	ca26                	sw	s1,20(sp)
+80001bd4:	c84a                	sw	s2,16(sp)
+80001bd6:	8b89                	andi	a5,a5,2
+80001bd8:	842e                	mv	s0,a1
+80001bda:	cf89                	beqz	a5,80001bf4 <__smakebuf_r+0x2c>
+80001bdc:	04740793          	addi	a5,s0,71
+80001be0:	c01c                	sw	a5,0(s0)
+80001be2:	c81c                	sw	a5,16(s0)
+80001be4:	4785                	li	a5,1
+80001be6:	c85c                	sw	a5,20(s0)
+80001be8:	40f2                	lw	ra,28(sp)
+80001bea:	4462                	lw	s0,24(sp)
+80001bec:	44d2                	lw	s1,20(sp)
+80001bee:	4942                	lw	s2,16(sp)
+80001bf0:	6105                	addi	sp,sp,32
+80001bf2:	8082                	ret
+80001bf4:	0074                	addi	a3,sp,12
+80001bf6:	0030                	addi	a2,sp,8
+80001bf8:	84aa                	mv	s1,a0
+80001bfa:	3f9d                	jal	80001b70 <__swhatbuf_r>
+80001bfc:	45a2                	lw	a1,8(sp)
+80001bfe:	892a                	mv	s2,a0
+80001c00:	8526                	mv	a0,s1
+80001c02:	b24ff0ef          	jal	ra,80000f26 <_malloc_r>
+80001c06:	ed01                	bnez	a0,80001c1e <__smakebuf_r+0x56>
+80001c08:	00c41783          	lh	a5,12(s0)
+80001c0c:	2007f713          	andi	a4,a5,512
+80001c10:	ff61                	bnez	a4,80001be8 <__smakebuf_r+0x20>
+80001c12:	9bf1                	andi	a5,a5,-4
+80001c14:	0027e793          	ori	a5,a5,2
+80001c18:	00f41623          	sh	a5,12(s0)
+80001c1c:	b7c1                	j	80001bdc <__smakebuf_r+0x14>
+80001c1e:	fffff797          	auipc	a5,0xfffff
+80001c22:	14678793          	addi	a5,a5,326 # 80000d64 <_cleanup_r>
+80001c26:	d49c                	sw	a5,40(s1)
+80001c28:	00c45783          	lhu	a5,12(s0)
+80001c2c:	c008                	sw	a0,0(s0)
+80001c2e:	c808                	sw	a0,16(s0)
+80001c30:	0807e793          	ori	a5,a5,128
+80001c34:	00f41623          	sh	a5,12(s0)
+80001c38:	47a2                	lw	a5,8(sp)
+80001c3a:	c85c                	sw	a5,20(s0)
+80001c3c:	47b2                	lw	a5,12(sp)
+80001c3e:	cf89                	beqz	a5,80001c58 <__smakebuf_r+0x90>
+80001c40:	00e41583          	lh	a1,14(s0)
+80001c44:	8526                	mv	a0,s1
+80001c46:	2a35                	jal	80001d82 <_isatty_r>
+80001c48:	c901                	beqz	a0,80001c58 <__smakebuf_r+0x90>
+80001c4a:	00c45783          	lhu	a5,12(s0)
+80001c4e:	9bf1                	andi	a5,a5,-4
+80001c50:	0017e793          	ori	a5,a5,1
+80001c54:	00f41623          	sh	a5,12(s0)
+80001c58:	00c45783          	lhu	a5,12(s0)
+80001c5c:	00f96933          	or	s2,s2,a5
+80001c60:	01241623          	sh	s2,12(s0)
+80001c64:	b751                	j	80001be8 <__smakebuf_r+0x20>
+
+80001c66 <memchr>:
+memchr():
+80001c66:	0ff5f593          	andi	a1,a1,255
+80001c6a:	962a                	add	a2,a2,a0
+80001c6c:	00c51463          	bne	a0,a2,80001c74 <memchr+0xe>
+80001c70:	4501                	li	a0,0
+80001c72:	8082                	ret
+80001c74:	00054783          	lbu	a5,0(a0)
+80001c78:	feb78de3          	beq	a5,a1,80001c72 <memchr+0xc>
+80001c7c:	0505                	addi	a0,a0,1
+80001c7e:	b7fd                	j	80001c6c <memchr+0x6>
+
+80001c80 <__malloc_lock>:
+__malloc_lock():
+80001c80:	8082                	ret
+
+80001c82 <__malloc_unlock>:
+__malloc_unlock():
+80001c82:	8082                	ret
+
+80001c84 <_free_r>:
+_free_r():
+80001c84:	c1cd                	beqz	a1,80001d26 <_free_r+0xa2>
+80001c86:	ffc5a783          	lw	a5,-4(a1)
+80001c8a:	1141                	addi	sp,sp,-16
+80001c8c:	c422                	sw	s0,8(sp)
+80001c8e:	c606                	sw	ra,12(sp)
+80001c90:	c226                	sw	s1,4(sp)
+80001c92:	ffc58413          	addi	s0,a1,-4
+80001c96:	0007d363          	bgez	a5,80001c9c <_free_r+0x18>
+80001c9a:	943e                	add	s0,s0,a5
+80001c9c:	84aa                	mv	s1,a0
+80001c9e:	37cd                	jal	80001c80 <__malloc_lock>
+80001ca0:	88c18793          	addi	a5,gp,-1908 # 8000408c <__malloc_free_list>
+80001ca4:	439c                	lw	a5,0(a5)
+80001ca6:	eb99                	bnez	a5,80001cbc <_free_r+0x38>
+80001ca8:	00042223          	sw	zero,4(s0)
+80001cac:	8881a623          	sw	s0,-1908(gp) # 8000408c <__malloc_free_list>
+80001cb0:	4422                	lw	s0,8(sp)
+80001cb2:	40b2                	lw	ra,12(sp)
+80001cb4:	8526                	mv	a0,s1
+80001cb6:	4492                	lw	s1,4(sp)
+80001cb8:	0141                	addi	sp,sp,16
+80001cba:	b7e1                	j	80001c82 <__malloc_unlock>
+80001cbc:	00f47e63          	bgeu	s0,a5,80001cd8 <_free_r+0x54>
+80001cc0:	4014                	lw	a3,0(s0)
+80001cc2:	00d40733          	add	a4,s0,a3
+80001cc6:	00e79663          	bne	a5,a4,80001cd2 <_free_r+0x4e>
+80001cca:	4398                	lw	a4,0(a5)
+80001ccc:	43dc                	lw	a5,4(a5)
+80001cce:	9736                	add	a4,a4,a3
+80001cd0:	c018                	sw	a4,0(s0)
+80001cd2:	c05c                	sw	a5,4(s0)
+80001cd4:	bfe1                	j	80001cac <_free_r+0x28>
+80001cd6:	87ba                	mv	a5,a4
+80001cd8:	43d8                	lw	a4,4(a5)
+80001cda:	c319                	beqz	a4,80001ce0 <_free_r+0x5c>
+80001cdc:	fee47de3          	bgeu	s0,a4,80001cd6 <_free_r+0x52>
+80001ce0:	4394                	lw	a3,0(a5)
+80001ce2:	00d78633          	add	a2,a5,a3
+80001ce6:	00861f63          	bne	a2,s0,80001d04 <_free_r+0x80>
+80001cea:	4010                	lw	a2,0(s0)
+80001cec:	96b2                	add	a3,a3,a2
+80001cee:	c394                	sw	a3,0(a5)
+80001cf0:	00d78633          	add	a2,a5,a3
+80001cf4:	fac71ee3          	bne	a4,a2,80001cb0 <_free_r+0x2c>
+80001cf8:	4310                	lw	a2,0(a4)
+80001cfa:	4358                	lw	a4,4(a4)
+80001cfc:	96b2                	add	a3,a3,a2
+80001cfe:	c394                	sw	a3,0(a5)
+80001d00:	c3d8                	sw	a4,4(a5)
+80001d02:	b77d                	j	80001cb0 <_free_r+0x2c>
+80001d04:	00c47563          	bgeu	s0,a2,80001d0e <_free_r+0x8a>
+80001d08:	47b1                	li	a5,12
+80001d0a:	c09c                	sw	a5,0(s1)
+80001d0c:	b755                	j	80001cb0 <_free_r+0x2c>
+80001d0e:	4010                	lw	a2,0(s0)
+80001d10:	00c406b3          	add	a3,s0,a2
+80001d14:	00d71663          	bne	a4,a3,80001d20 <_free_r+0x9c>
+80001d18:	4314                	lw	a3,0(a4)
+80001d1a:	4358                	lw	a4,4(a4)
+80001d1c:	96b2                	add	a3,a3,a2
+80001d1e:	c014                	sw	a3,0(s0)
+80001d20:	c058                	sw	a4,4(s0)
+80001d22:	c3c0                	sw	s0,4(a5)
+80001d24:	b771                	j	80001cb0 <_free_r+0x2c>
+80001d26:	8082                	ret
+
+80001d28 <_read_r>:
+_read_r():
+80001d28:	1141                	addi	sp,sp,-16
+80001d2a:	c422                	sw	s0,8(sp)
+80001d2c:	842a                	mv	s0,a0
+80001d2e:	852e                	mv	a0,a1
+80001d30:	85b2                	mv	a1,a2
+80001d32:	8636                	mv	a2,a3
+80001d34:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d38:	c606                	sw	ra,12(sp)
+80001d3a:	b77fe0ef          	jal	ra,800008b0 <_read>
+80001d3e:	57fd                	li	a5,-1
+80001d40:	00f51763          	bne	a0,a5,80001d4e <_read_r+0x26>
+80001d44:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d48:	439c                	lw	a5,0(a5)
+80001d4a:	c391                	beqz	a5,80001d4e <_read_r+0x26>
+80001d4c:	c01c                	sw	a5,0(s0)
+80001d4e:	40b2                	lw	ra,12(sp)
+80001d50:	4422                	lw	s0,8(sp)
+80001d52:	0141                	addi	sp,sp,16
+80001d54:	8082                	ret
+
+80001d56 <_fstat_r>:
+_fstat_r():
+80001d56:	1141                	addi	sp,sp,-16
+80001d58:	c422                	sw	s0,8(sp)
+80001d5a:	842a                	mv	s0,a0
+80001d5c:	852e                	mv	a0,a1
+80001d5e:	85b2                	mv	a1,a2
+80001d60:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d64:	c606                	sw	ra,12(sp)
+80001d66:	b27fe0ef          	jal	ra,8000088c <_fstat>
+80001d6a:	57fd                	li	a5,-1
+80001d6c:	00f51763          	bne	a0,a5,80001d7a <_fstat_r+0x24>
+80001d70:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d74:	439c                	lw	a5,0(a5)
+80001d76:	c391                	beqz	a5,80001d7a <_fstat_r+0x24>
+80001d78:	c01c                	sw	a5,0(s0)
+80001d7a:	40b2                	lw	ra,12(sp)
+80001d7c:	4422                	lw	s0,8(sp)
+80001d7e:	0141                	addi	sp,sp,16
+80001d80:	8082                	ret
+
+80001d82 <_isatty_r>:
+_isatty_r():
+80001d82:	1141                	addi	sp,sp,-16
+80001d84:	c422                	sw	s0,8(sp)
+80001d86:	842a                	mv	s0,a0
+80001d88:	852e                	mv	a0,a1
+80001d8a:	8e01a823          	sw	zero,-1808(gp) # 800040f0 <errno>
+80001d8e:	c606                	sw	ra,12(sp)
+80001d90:	af3fe0ef          	jal	ra,80000882 <_isatty>
+80001d94:	57fd                	li	a5,-1
+80001d96:	00f51763          	bne	a0,a5,80001da4 <_isatty_r+0x22>
+80001d9a:	8f018793          	addi	a5,gp,-1808 # 800040f0 <errno>
+80001d9e:	439c                	lw	a5,0(a5)
+80001da0:	c391                	beqz	a5,80001da4 <_isatty_r+0x22>
+80001da2:	c01c                	sw	a5,0(s0)
+80001da4:	40b2                	lw	ra,12(sp)
+80001da6:	4422                	lw	s0,8(sp)
+80001da8:	0141                	addi	sp,sp,16
+80001daa:	8082                	ret
+80001dac:	0000                	unimp
+	...
+
+80001db0 <local_irq_handler_table>:
+80001db0:	083c 8000 083a 8000 083e 8000 0852 8000     <...:...>...R...
+80001dc0:	084c 8000 084c 8000 084c 8000 084c 8000     L...L...L...L...
+80001dd0:	0840 8000 0842 8000 0844 8000 0846 8000     @...B...D...F...
+80001de0:	0848 8000 084a 8000 084e 8000 0850 8000     H...J...N...P...
+80001df0:	0a0d 6e49 6574 6e72 6c61 5320 7379 6574     ..Internal Syste
+80001e00:	206d 6954 656d 2072 6e49 6574 7272 7075     m Timer Interrup
+80001e10:	2074 6f43 6e75 6574 2072 203d 6425 0000     t Counter = %d..
+80001e20:	0a0d 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ..**************
+80001e30:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e40:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e50:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e60:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001e70:	0a0d 2a0a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ...*************
+80001e80:	2a2a 2a2a 2a2a 202a 2020 4d20 2d69 2056     *******    Mi-V 
+80001e90:	7953 7473 6d65 5420 6d69 7265 4220 696c     System Timer Bli
+80001ea0:	6b6e 2079 7845 6d61 6c70 2065 2020 2a20     nky Example    *
+80001eb0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ec0:	2a2a 2a2a 2a2a 0a0d 2a0a 2a2a 2a2a 2a2a     ******...*******
+80001ed0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ee0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001ef0:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001f00:	2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a 2a2a     ****************
+80001f10:	2a2a 2a2a 2a2a 0d2a 0d0a 4f0a 7362 7265     *******....Obser
+80001f20:	6576 7420 6568 4c20 4445 2073 6c62 6e69     ve the LEDs blin
+80001f30:	696b 676e 6f20 206e 6874 2065 6f62 7261     king on the boar
+80001f40:	2e64 5420 6568 4c20 4445 7020 7461 6574     d. The LED patte
+80001f50:	6e72 6320 6168 676e 7365 6520 6576 7972     rn changes every
+80001f60:	7420 6d69 2065 2061 7973 7473 6d65 7420      time a system t
+80001f70:	6d69 7265 6920 746e 7265 7572 7470 6f20     imer interrupt o
+80001f80:	6363 7275 2e73 0a0d 0000 0000               ccurs.......
+
+80001f8c <__sf_fake_stderr>:
+	...
+
+80001fac <__sf_fake_stdin>:
+	...
+
+80001fcc <__sf_fake_stdout>:
+	...
+80001fec:	2d23 2b30 0020 0000 6c68 004c 6665 4567     #-0+ ...hlL.efgE
+80001ffc:	4746 0000 3130 3332 3534 3736 3938 4241     FG..0123456789AB
+8000200c:	4443 4645 0000 0000 3130 3332 3534 3736     CDEF....01234567
+8000201c:	3938 6261 6463 6665 0000 0000 0000 0000     89abcdef........
+8000202c:	0000 0000                                   ....
diff --git a/README.md b/README.md
index 0ec7d13..782baa4 100644
--- a/README.md
+++ b/README.md
@@ -20,7 +20,7 @@ To download or clone the repository:
 
 
 # Libero Projects
-The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2023.1. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/PolarFire-Eval-Kit/releases) in this repository.
+The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2023.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/PolarFire-Eval-Kit/releases) in this repository.
 
 ## Design Features
 The Libero designs include the following features:
@@ -40,7 +40,7 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file
 # Design Tools
 The following design tools are required.
 
-## Libero SoC v2023.1
+## Libero SoC v2023.2
 [Libero SoC](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#downloads) is Microchip's FPGA design software.
 
 ## FlashPro Express
diff --git a/docs/design_dgc1/README.md b/docs/design_dgc1/README.md
index 5023adc..3322ed3 100644
--- a/docs/design_dgc1/README.md
+++ b/docs/design_dgc1/README.md
@@ -1,6 +1,6 @@
 ## Mi-V Extended Subsystem Design Guide Configuration 1: SPI Write & Boot
-This folder contains Tcl scripts that build Libero SoC v2023.1 MIV_ESS DGC1 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
-> This design is compatible with Libero SoC v2023.1. Using older versions of Libero SoC will result in errors.
+This folder contains Tcl scripts that build Libero SoC v2023.2 MIV_ESS DGC1 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
+> This design is compatible with Libero SoC v2023.2. Using older versions of Libero SoC will result in errors.
 
 #### PF_Eval_Kit_MIV_RV32_BaseDesign
 
diff --git a/docs/design_dgc3/README.md b/docs/design_dgc3/README.md
index cf74301..caaf305 100644
--- a/docs/design_dgc3/README.md
+++ b/docs/design_dgc3/README.md
@@ -1,6 +1,6 @@
 ## Mi-V Extended Subsystem Design Guide Configuration 3: PF uPROM Boot
-This folder contains Tcl scripts that build Libero SoC v2023.1 MIV_ESS DGC3 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
-> This design is compatible with Libero SoC v2023.1. Using older versions of Libero SoC will result in errors.
+This folder contains Tcl scripts that build Libero SoC v2023.2 MIV_ESS DGC3 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
+> This design is compatible with Libero SoC v2023.2. Using older versions of Libero SoC will result in errors.
 
 #### PF_Eval_Kit_MIV_RV32_BaseDesign
 
diff --git a/docs/design_dgc4/README.md b/docs/design_dgc4/README.md
index 2a7de81..5532285 100644
--- a/docs/design_dgc4/README.md
+++ b/docs/design_dgc4/README.md
@@ -1,6 +1,6 @@
 ## Mi-V Extended Subsystem Design Guide Configuration 4: Basic Peripherals
-This folder contains Tcl scripts that build Libero SoC v2023.1 MIV_ESS DGC4 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
-> This design is compatible with Libero SoC v2023.1. Using older versions of Libero SoC will result in errors.
+This folder contains Tcl scripts that build Libero SoC v2023.2 MIV_ESS DGC4 design project for the PolarFire Eval Kit. The script is executed in Libero SoC to generate the sample design. 
+> This design is compatible with Libero SoC v2023.2. Using older versions of Libero SoC will result in errors.
 
 #### PF_Eval_Kit_MIV_RV32_BaseDesign