Skip to content

Libero SoC 2022.1 designs - v1.0
Compare
Choose a tag to compare
@kevinscully100 kevinscully100 released this 03 Jun 11:38
· 31 commits to main since this release
2022.1-v1.0
d3a4b72
This commit was created on GitHub.com and signed with GitHub’s verified signature. The key has expired.
GPG key ID: 4AEE18F83AFDEB23
Expired
Learn about vigilant mode.

Updated to support Libero SoC v2022.1

Features of this release:

  • A 3rd argument has been added to the scripts which could be passed in
    to specify the board's die type.
  • Top level scripts for 'ES' die type targets have been merged with 'PS'
    die type scripts. A 3rd argument is now used to specify desired die type for
    building a design.
  • Improved script execution log messaging
  • 'ES' bitstreams now supplied for DGC1, DGC3 and DGC4 design configs
  • CoreAHBLite DirectCore updated from v5.5.105 to 5.6.105
  • A missing connection was added in CFG designs for "FPGA_POR_ON" signal,
    between PF_INIT_MONITOR and CoreRESET_PF.
  • Designs now auto-arrange SmartDesign layout after building
  • New bitstreams/programming files that have been generated in Libero SoC v2022.1
  • Readmes updated (including DGC1, DGC3 & DGC4)
Assets 2
Loading