Merge pull request #5 from Mi-V-Soft-RISC-V/develop

Update README.md

README.md

@@ -24,7 +24,7 @@ The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A soft RISC-V processor
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
 * Target memory is SRAM (32kB)