From 26b2cdd94d71e9f8ecf5c51cc7425f257f666105 Mon Sep 17 00:00:00 2001
From: CLappin <ciaran.lappin@microsemi.com>
Date: Tue, 9 Nov 2021 10:46:27 +0000
Subject: [PATCH] Update README.md

removed hyperlink.
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 2040ad5..d48d67f 100644
--- a/README.md
+++ b/README.md
@@ -24,7 +24,7 @@ The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A soft RISC-V processor
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
 * Target memory is SRAM (32kB)