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Merge pull request #12 from Mi-V-Soft-RISC-V/develop
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Merging Develop into main.
Features of this release:

Updated .job files to v2022.2
Removed Engineering Samples .job files
CFG1, CFG2 and CFG3 with the MIV_RV32 in it now have the MIV_ESS incorporated
The MIV_ESS tcl file was added to the shared components folder
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CLappin authored Dec 13, 2022
2 parents 952f78b + 3c6d92a commit 27236c7
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48 changes: 35 additions & 13 deletions FlashPro_Express_Projects/README.md
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# PolarFire FPGA Splash-Kit FPGA Programming Files

This folder contains FlashPro Express v2022.1 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.
This folder contains FlashPro Express v2022.2 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs.

## FlashPro Express
The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
Expand All @@ -21,19 +21,41 @@ The programming files contained under this folder were exported from the designs

## Design Features
The Libero designs include the following features:
* A soft RISC-V processor
* A soft RISC-V processor operating at 50 MHz
* A RISC-V debug block allowing on-target debug using SoftConsole
* The operating frequency of the design is 50MHz
* Target memory is SRAM (32kB)
* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
* An Extended Subsystem with integrated peripherals
* Target SRAM/TCM memory (32kB)
* User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)


The peripherals in this design are located at the following addresses.
#### MIV_RV32 based configurations
| Peripheral (MIV_ESS) | Address Start | Address End |
| ------------------------------: |:-------------:|:--------------:|
| PLIC | 0x7000_0000 | 0x70FF_FFFF |
| UART | 0x7100_0000 | 0x71FF_FFFF |
| Timer | 0x7200_0000 | 0x72FF_FFFF |
| CoreTimer_0 / MIV_ESS_APBSLOT3 | 0x7300_0000 | 0x73FF_FFFF |
| CoreTimer_1 / MIV_ESS_APBSLOT4 | 0x7400_0000 | 0x74FF_FFFF |
| GPIO | 0x7500_0000 | 0x75FF_FFFF |
| SPI | 0x7600_0000 | 0x76FF_FFFF |
| uDMA | 0x7800_0000 | 0x78FF_FFFF |
| WDOG | 0x7900_0000 | 0x79FF_FFFF |
| I2C | 0x7A00_0000 | 0x7AFF_FFFF |
| MIV_ESS_APBSLOTB_BASE | 0x7B00_0000 | 0x7BFF_FFFF |
| MIV_ESS_APBSLOTC_BASE | 0x7C00_0000 | 0x7CFF_FFFF |
| MIV_ESS_APBSLOTD_BASE | 0x7D00_0000 | 0x7DFF_FFFF |
| MIV_ESS_APBSLOTE_BASE | 0x7E00_0000 | 0x7EFF_FFFF |
| MIV_ESS_APBSLOTF_BASE | 0x7F00_0000 | 0x7FFF_FFFF |
| SRAM/TCM | 0x8000_0000 | 0x8000_7FFF |


| Peripheral | Address |
| ------------- |:-------------:|
| CoreUARTapb | 0x7000_1000 |
| CoreGPIO_IN | 0x7000_2000 |
| CoreTimer_0 | 0x7000_3000 |
| CoreTimer_1 | 0x7000_4000 |
| CoreGPIO_OUT | 0x7000_5000 |
| SRAM| 0x8000_0000|
#### Legacy core based configurations:
| Peripheral (Standalone)| Address |
| ----------------------:|:-------------:|
| CoreUARTapb | 0x7000_1000 |
| CoreGPIO_IN | 0x7000_2000 |
| CoreTimer_0 | 0x7000_3000 |
| CoreTimer_1 | 0x7000_4000 |
| CoreGPIO_OUT | 0x7000_5000 |
| SRAM | 0x8000_0000 |
6 changes: 3 additions & 3 deletions Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -70,13 +70,13 @@ proc base_design_built { } {
}

proc download_required_direct_cores { } {
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
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56 changes: 39 additions & 17 deletions Libero_Projects/README.md
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
# PolarFire FPGA Splash-Kit Mi-V Sample FPGA Designs
This folder contains Tcl scripts that build Libero SoC v2022.1 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
This folder contains Tcl scripts that build Libero SoC v2022.2 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.


#### PF_Splash_Kit_MIV_RV32_BaseDesign

| Config | Description|
| :------:|:----------------------------------------|
| CFG1 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
| CFG2 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
| CFG3 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
| CFG1 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
| CFG2 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|
| CFG3 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 1</li><li>TCM: enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: Enabled</li></ul>|


#### PF_Splash_Kit_MIV_RV32IMA_BaseDesign
Expand Down Expand Up @@ -79,19 +79,41 @@ In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE PS" were entered

## Design Features
The Libero designs include the following features:
* A soft RISC-V processor
* A soft RISC-V processor operating at 50 MHz
* A RISC-V debug block allowing on-target debug using SoftConsole
* The operating frequency of the design is 50MHz
* Target memory is SRAM (32kB)
* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)
* An Extended Subsystem with integrated peripherals
* Target SRAM/TCM memory (32kB)
* User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization)

The peripherals in this design are located at the following addresses.

| Peripheral | Address |
| ------------- |:-------------:|
| CoreUARTapb | 0x7000_1000 |
| CoreGPIO_IN | 0x7000_2000 |
| CoreTimer_0 | 0x7000_3000 |
| CoreTimer_1 | 0x7000_4000 |
| CoreGPIO_OUT | 0x7000_5000 |
| SRAM| 0x8000_0000|
The peripherals in this design are located at the following addresses.
#### MIV_RV32 based configurations
| Peripheral (MIV_ESS) | Address Start | Address End |
| ------------------------------: |:-------------:|:--------------:|
| PLIC | 0x7000_0000 | 0x70FF_FFFF |
| UART | 0x7100_0000 | 0x71FF_FFFF |
| Timer | 0x7200_0000 | 0x72FF_FFFF |
| CoreTimer_0 / MIV_ESS_APBSLOT3 | 0x7300_0000 | 0x73FF_FFFF |
| CoreTimer_1 / MIV_ESS_APBSLOT4 | 0x7400_0000 | 0x74FF_FFFF |
| GPIO | 0x7500_0000 | 0x75FF_FFFF |
| SPI | 0x7600_0000 | 0x76FF_FFFF |
| uDMA | 0x7800_0000 | 0x78FF_FFFF |
| WDOG | 0x7900_0000 | 0x79FF_FFFF |
| I2C | 0x7A00_0000 | 0x7AFF_FFFF |
| MIV_ESS_APBSLOTB_BASE | 0x7B00_0000 | 0x7BFF_FFFF |
| MIV_ESS_APBSLOTC_BASE | 0x7C00_0000 | 0x7CFF_FFFF |
| MIV_ESS_APBSLOTD_BASE | 0x7D00_0000 | 0x7DFF_FFFF |
| MIV_ESS_APBSLOTE_BASE | 0x7E00_0000 | 0x7EFF_FFFF |
| MIV_ESS_APBSLOTF_BASE | 0x7F00_0000 | 0x7FFF_FFFF |
| SRAM/TCM | 0x8000_0000 | 0x8000_7FFF |


#### Legacy core based configurations:
| Peripheral (Standalone)| Address |
| ----------------------:|:-------------:|
| CoreUARTapb | 0x7000_1000 |
| CoreGPIO_IN | 0x7000_2000 |
| CoreTimer_0 | 0x7000_3000 |
| CoreTimer_1 | 0x7000_4000 |
| CoreGPIO_OUT | 0x7000_5000 |
| SRAM | 0x8000_0000 |
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