diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMAF_CFG1_BaseDesign.job deleted file mode 100644 index 25f9ca9..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMAF_CFG1_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMA_CFG1_BaseDesign.job deleted file mode 100644 index eaecd7a..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMA_CFG1_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32IMA_CFG2_BaseDesign.job deleted file mode 100644 index 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b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32_CFG3_BaseDesign.job deleted file mode 100644 index f7d75d2..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_ES_MIV_RV32_CFG3_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job index b892769..9fd22bc 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job index 8c284f3..fd932f7 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job index af50090..456c700 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG1_BaseDesign.job index 97cabfa..9e351e8 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG1_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG2_BaseDesign.job index 586b1bd..c61a911 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG2_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG2_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG3_BaseDesign.job index 200336d..ebf861f 100644 Binary files a/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG3_BaseDesign.job and b/FlashPro_Express_Projects/Programming_Files/PF_Splash_Kit_PS_MIV_RV32_CFG3_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md index e3a3550..d61d491 100644 --- a/FlashPro_Express_Projects/README.md +++ b/FlashPro_Express_Projects/README.md @@ -1,6 +1,6 @@ # PolarFire FPGA Splash-Kit FPGA Programming Files -This folder contains FlashPro Express v2022.1 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs. +This folder contains FlashPro Express v2022.2 projects for the PolarFire FPGA Splash-Kit Mi-V sample designs. ## FlashPro Express The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express. @@ -21,19 +21,41 @@ The programming files contained under this folder were exported from the designs ## Design Features The Libero designs include the following features: -* A soft RISC-V processor +* A soft RISC-V processor operating at 50 MHz * A RISC-V debug block allowing on-target debug using SoftConsole -* The operating frequency of the design is 50MHz -* Target memory is SRAM (32kB) -* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) +* An Extended Subsystem with integrated peripherals +* Target SRAM/TCM memory (32kB) +* User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) + The peripherals in this design are located at the following addresses. +#### MIV_RV32 based configurations +| Peripheral (MIV_ESS) | Address Start | Address End | +| ------------------------------: |:-------------:|:--------------:| +| PLIC | 0x7000_0000 | 0x70FF_FFFF | +| UART | 0x7100_0000 | 0x71FF_FFFF | +| Timer | 0x7200_0000 | 0x72FF_FFFF | +| CoreTimer_0 / MIV_ESS_APBSLOT3 | 0x7300_0000 | 0x73FF_FFFF | +| CoreTimer_1 / MIV_ESS_APBSLOT4 | 0x7400_0000 | 0x74FF_FFFF | +| GPIO | 0x7500_0000 | 0x75FF_FFFF | +| SPI | 0x7600_0000 | 0x76FF_FFFF | +| uDMA | 0x7800_0000 | 0x78FF_FFFF | +| WDOG | 0x7900_0000 | 0x79FF_FFFF | +| I2C | 0x7A00_0000 | 0x7AFF_FFFF | +| MIV_ESS_APBSLOTB_BASE | 0x7B00_0000 | 0x7BFF_FFFF | +| MIV_ESS_APBSLOTC_BASE | 0x7C00_0000 | 0x7CFF_FFFF | +| MIV_ESS_APBSLOTD_BASE | 0x7D00_0000 | 0x7DFF_FFFF | +| MIV_ESS_APBSLOTE_BASE | 0x7E00_0000 | 0x7EFF_FFFF | +| MIV_ESS_APBSLOTF_BASE | 0x7F00_0000 | 0x7FFF_FFFF | +| SRAM/TCM | 0x8000_0000 | 0x8000_7FFF | + -| Peripheral | Address | -| ------------- |:-------------:| -| CoreUARTapb | 0x7000_1000 | -| CoreGPIO_IN | 0x7000_2000 | -| CoreTimer_0 | 0x7000_3000 | -| CoreTimer_1 | 0x7000_4000 | -| CoreGPIO_OUT | 0x7000_5000 | -| SRAM| 0x8000_0000| +#### Legacy core based configurations: +| Peripheral (Standalone)| Address | +| ----------------------:|:-------------:| +| CoreUARTapb | 0x7000_1000 | +| CoreGPIO_IN | 0x7000_2000 | +| CoreTimer_0 | 0x7000_3000 | +| CoreTimer_1 | 0x7000_4000 | +| CoreGPIO_OUT | 0x7000_5000 | +| SRAM | 0x8000_0000 | \ No newline at end of file diff --git a/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl index cd18f33..379cfda 100644 --- a/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl +++ b/Libero_Projects/PF_Splash_Kit_MIV_RV32_BaseDesign.tcl @@ -70,13 +70,13 @@ proc base_design_built { } { } proc download_required_direct_cores { } { - download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} + #download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} + #download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} + #download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md index b1edfdf..5f4842d 100644 --- a/Libero_Projects/README.md +++ b/Libero_Projects/README.md @@ -1,14 +1,14 @@ # PolarFire FPGA Splash-Kit Mi-V Sample FPGA Designs -This folder contains Tcl scripts that build Libero SoC v2022.1 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. +This folder contains Tcl scripts that build Libero SoC v2022.2 design projects for the PolarFire FPGA Splash-Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. #### PF_Splash_Kit_MIV_RV32_BaseDesign | Config | Description| | :------:|:----------------------------------------| -| CFG1 | This design uses the MIV_RV32 core configured as follows: | -| CFG2 | This design uses the MIV_RV32 core configured as follows: | -| CFG3 | This design uses the MIV_RV32 core configured as follows: | +| CFG1 | This design uses the MIV_RV32 core configured as follows: | +| CFG2 | This design uses the MIV_RV32 core configured as follows: | +| CFG3 | This design uses the MIV_RV32 core configured as follows: | #### PF_Splash_Kit_MIV_RV32IMA_BaseDesign @@ -79,19 +79,41 @@ In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE PS" were entered ## Design Features The Libero designs include the following features: -* A soft RISC-V processor +* A soft RISC-V processor operating at 50 MHz * A RISC-V debug block allowing on-target debug using SoftConsole -* The operating frequency of the design is 50MHz -* Target memory is SRAM (32kB) -* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) +* An Extended Subsystem with integrated peripherals +* Target SRAM/TCM memory (32kB) +* User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) -The peripherals in this design are located at the following addresses. -| Peripheral | Address | -| ------------- |:-------------:| -| CoreUARTapb | 0x7000_1000 | -| CoreGPIO_IN | 0x7000_2000 | -| CoreTimer_0 | 0x7000_3000 | -| CoreTimer_1 | 0x7000_4000 | -| CoreGPIO_OUT | 0x7000_5000 | -| SRAM| 0x8000_0000| +The peripherals in this design are located at the following addresses. +#### MIV_RV32 based configurations +| Peripheral (MIV_ESS) | Address Start | Address End | +| ------------------------------: |:-------------:|:--------------:| +| PLIC | 0x7000_0000 | 0x70FF_FFFF | +| UART | 0x7100_0000 | 0x71FF_FFFF | +| Timer | 0x7200_0000 | 0x72FF_FFFF | +| CoreTimer_0 / MIV_ESS_APBSLOT3 | 0x7300_0000 | 0x73FF_FFFF | +| CoreTimer_1 / MIV_ESS_APBSLOT4 | 0x7400_0000 | 0x74FF_FFFF | +| GPIO | 0x7500_0000 | 0x75FF_FFFF | +| SPI | 0x7600_0000 | 0x76FF_FFFF | +| uDMA | 0x7800_0000 | 0x78FF_FFFF | +| WDOG | 0x7900_0000 | 0x79FF_FFFF | +| I2C | 0x7A00_0000 | 0x7AFF_FFFF | +| MIV_ESS_APBSLOTB_BASE | 0x7B00_0000 | 0x7BFF_FFFF | +| MIV_ESS_APBSLOTC_BASE | 0x7C00_0000 | 0x7CFF_FFFF | +| MIV_ESS_APBSLOTD_BASE | 0x7D00_0000 | 0x7DFF_FFFF | +| MIV_ESS_APBSLOTE_BASE | 0x7E00_0000 | 0x7EFF_FFFF | +| MIV_ESS_APBSLOTF_BASE | 0x7F00_0000 | 0x7FFF_FFFF | +| SRAM/TCM | 0x8000_0000 | 0x8000_7FFF | + + +#### Legacy core based configurations: +| Peripheral (Standalone)| Address | +| ----------------------:|:-------------:| +| CoreUARTapb | 0x7000_1000 | +| CoreGPIO_IN | 0x7000_2000 | +| CoreTimer_0 | 0x7000_3000 | +| CoreTimer_1 | 0x7000_4000 | +| CoreGPIO_OUT | 0x7000_5000 | +| SRAM | 0x8000_0000 | \ No newline at end of file diff --git a/Libero_Projects/import/components/IMC_CFG1/build_sd_imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/build_sd_imc_cfg1.tcl index 89a34be..2edb6c8 100644 --- a/Libero_Projects/import/components/IMC_CFG1/build_sd_imc_cfg1.tcl +++ b/Libero_Projects/import/components/IMC_CFG1/build_sd_imc_cfg1.tcl @@ -1,4 +1,3 @@ -#Hardware : Arrow Everest Board (rev A or rev B) #MIV Cores : MIV_RV32 # #Libero's TCL top level script @@ -6,19 +5,16 @@ #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion #Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl source ./import/components/SHARED_COMPONENTS/CoreRESET_PF_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG1_0.tcl source ./import/components/SHARED_COMPONENTS/PF_CCC_0.tcl source ./import/components/SHARED_COMPONENTS/PF_INIT_MONITOR_0.tcl source ./import/components/SHARED_COMPONENTS/PF_OSC_0.tcl source ./import/components/SHARED_COMPONENTS/PF_SRAM_0.tcl +source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl # Creating SmartDesign BaseDesign set sd_name {BaseDesign} @@ -44,30 +40,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OU sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - - # Add CoreJTAGDebug_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} @@ -94,16 +66,6 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -inst -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - - # Add MIV_RV32_CFG1_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG1_0} -instance_name {MIV_RV32_CFG1_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1_0:TIME_COUNT_OUT} @@ -112,6 +74,20 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1_0:EXT_RESETN} +# Add MIV_ESS_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} + + + # Add PF_CCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_0} -instance_name {PF_CCC_0} @@ -146,43 +122,42 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_0} -instan # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MIV_RV32_CFG1_0:JTAG_TCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MIV_RV32_CFG1_0:JTAG_TDI" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG1_0:JTAG_TDO" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MIV_RV32_CFG1_0:JTAG_TMS" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTN_0" "MIV_RV32_CFG1_0:JTAG_TRSTN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "CoreRESET_PF_0:FABRIC_RESET_N" "PF_SRAM_0:HRESETN" "MIV_RV32_CFG1_0:RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreRESET_PF_0:FABRIC_RESET_N" "PF_SRAM_0:HRESETN" "MIV_RV32_CFG1_0:RESETN" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG1_0:MSYS_EI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32_CFG1_0:EXT_IRQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG1_0:JTAG_TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:OUT0_FABCLK_0" "CoreGPIO_IN:PCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "CoreRESET_PF_0:CLK" "PF_SRAM_0:HCLK" "MIV_RV32_CFG1_0:CLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:OUT0_FABCLK_0" "MIV_ESS_0:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreRESET_PF_0:CLK" "PF_SRAM_0:HCLK" "MIV_RV32_CFG1_0:CLK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:PLL_LOCK_0" "CoreRESET_PF_0:PLL_LOCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:INIT_DONE" "PF_INIT_MONITOR_0:DEVICE_INIT_DONE" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:REF_CLK_0" "PF_OSC_0:RCOSC_160MHZ_GL" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:EXT_RST_N" "USER_RST" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_INIT_MONITOR_0:FABRIC_POR_N" "CoreRESET_PF_0:FPGA_POR_N"} + # Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "SW_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "SW_4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "SW_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "SW_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } # Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SRAM_0:AHBSlaveInterface" "MIV_RV32_CFG1_0:AHBL_M_SLV" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "MIV_RV32_CFG1_0:APB_MSTR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_3_mTARGET" "CoreTimer_0:APBslave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_4_mTARGET" "CoreTimer_1:APBslave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG1_0:APB_MSTR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG1_0:AHBL_M_SLV" "PF_SRAM_0:AHBSlaveInterface" } + # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 diff --git a/Libero_Projects/import/components/IMC_CFG2/build_sd_imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/build_sd_imc_cfg2.tcl index f81da4f..21b5735 100644 --- a/Libero_Projects/import/components/IMC_CFG2/build_sd_imc_cfg2.tcl +++ b/Libero_Projects/import/components/IMC_CFG2/build_sd_imc_cfg2.tcl @@ -1,4 +1,3 @@ -#Hardware : Arrow Everest Board (rev A or rev B) #MIV Cores : MIV_RV32 # #Libero's TCL top level script @@ -6,19 +5,16 @@ #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion #Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl source ./import/components/SHARED_COMPONENTS/CoreRESET_PF_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG2_0.tcl source ./import/components/SHARED_COMPONENTS/PF_CCC_0.tcl source ./import/components/SHARED_COMPONENTS/PF_INIT_MONITOR_0.tcl source ./import/components/SHARED_COMPONENTS/PF_OSC_0.tcl source ./import/components/SHARED_COMPONENTS/PF_SRAM_AXI4_0.tcl +source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl # Creating SmartDesign BaseDesign set sd_name {BaseDesign} @@ -44,29 +40,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OU sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_0 instance @@ -94,16 +67,6 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -inst -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - - # Add MIV_RV32_CFG2_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG2_0} -instance_name {MIV_RV32_CFG2_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:TIME_COUNT_OUT} @@ -111,6 +74,19 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:JTAG_TDO_DR} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:EXT_RESETN} +# Add MIV_ESS_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} + + # Add PF_CCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_0} -instance_name {PF_CCC_0} @@ -146,43 +122,42 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PF_SRAM_AXI4_0} -i # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MIV_RV32_CFG2_0:JTAG_TCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MIV_RV32_CFG2_0:JTAG_TDI" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG2_0:JTAG_TDO" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MIV_RV32_CFG2_0:JTAG_TMS" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTN_0" "MIV_RV32_CFG2_0:JTAG_TRSTN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:FABRIC_RESET_N" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_1:PRESETn" "PF_SRAM_AXI4_0:ARESETN" "MIV_RV32_CFG2_0:RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:CLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "MIV_ESS_0:PCLK" "MIV_RV32_CFG2_0:CLK" "PF_CCC_0:OUT0_FABCLK_0" "PF_SRAM_AXI4_0:ACLK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:FABRIC_RESET_N" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "MIV_ESS_0:PRESETN" "MIV_RV32_CFG2_0:RESETN" "PF_SRAM_AXI4_0:ARESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:INIT_DONE" "PF_INIT_MONITOR_0:DEVICE_INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:PLL_LOCK" "PF_CCC_0:PLL_LOCK_0" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG2_0:MSYS_EI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32_CFG2_0:EXT_IRQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG2_0:JTAG_TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:OUT0_FABCLK_0" "CoreRESET_PF_0:CLK" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_1:PCLK" "PF_SRAM_AXI4_0:ACLK" "MIV_RV32_CFG2_0:CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:PLL_LOCK_0" "CoreRESET_PF_0:PLL_LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:INIT_DONE" "PF_INIT_MONITOR_0:DEVICE_INIT_DONE" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:REF_CLK_0" "PF_OSC_0:RCOSC_160MHZ_GL" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:EXT_RST_N" "USER_RST" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_RST" "CoreRESET_PF_0:EXT_RST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_INIT_MONITOR_0:FABRIC_POR_N" "CoreRESET_PF_0:FPGA_POR_N"} + # Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "SW_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "SW_4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "SW_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "SW_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } # Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "MIV_RV32_CFG2_0:APB_MSTR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_SRAM_AXI4_0:AXI4_Slave" "MIV_RV32_CFG2_0:AXI4_M_SLV" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "MIV_ESS_0:APB_3_mTARGET" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "MIV_ESS_0:APB_4_mTARGET" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG2_0:APB_MSTR" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG2_0:AXI4_M_SLV" "PF_SRAM_AXI4_0:AXI4_Slave" } + # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 diff --git a/Libero_Projects/import/components/IMC_CFG3/build_sd_imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/build_sd_imc_cfg3.tcl index 3056361..ef91ac4 100644 --- a/Libero_Projects/import/components/IMC_CFG3/build_sd_imc_cfg3.tcl +++ b/Libero_Projects/import/components/IMC_CFG3/build_sd_imc_cfg3.tcl @@ -1,4 +1,3 @@ -#Hardware : Arrow Everest Board (rev A or rev B) #MIV Cores : MIV_RV32 # #Libero's TCL top level script @@ -6,18 +5,15 @@ #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion #Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl source ./import/components/SHARED_COMPONENTS/CoreRESET_PF_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG3_0.tcl source ./import/components/SHARED_COMPONENTS/PF_CCC_0.tcl source ./import/components/SHARED_COMPONENTS/PF_INIT_MONITOR_0.tcl source ./import/components/SHARED_COMPONENTS/PF_OSC_0.tcl +source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl # Creating SmartDesign BaseDesign set sd_name {BaseDesign} @@ -43,29 +39,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OU sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_0 instance @@ -93,16 +66,6 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -inst -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - - # Add MIV_RV32_CFG3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG3_0} -instance_name {MIV_RV32_CFG3_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3_0:TIME_COUNT_OUT} @@ -111,6 +74,21 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3_0:EXT_RESETN} +# Add MIV_ESS_0 instance +sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} +sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} +sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} +sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} + + + + # Add PF_CCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {PF_CCC_0} -instance_name {PF_CCC_0} @@ -138,44 +116,43 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {PF_OSC_0} -instanc # Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TCK" "CoreJTAGDebug_0:TGT_TCK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TDI" "CoreJTAGDebug_0:TGT_TDI_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TMS" "CoreJTAGDebug_0:TGT_TMS_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TRSTN" "CoreJTAGDebug_0:TGT_TRSTN_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:RESETN" "CoreGPIO_IN:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreRESET_PF_0:FABRIC_RESET_N" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MIV_RV32_CFG3_0:JTAG_TCK" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MIV_RV32_CFG3_0:JTAG_TDI" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG3_0:JTAG_TDO" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MIV_RV32_CFG3_0:JTAG_TMS" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTN_0" "MIV_RV32_CFG3_0:JTAG_TRSTN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:CLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "MIV_ESS_0:PCLK" "MIV_RV32_CFG3_0:CLK" "PF_CCC_0:OUT0_FABCLK_0" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:FABRIC_RESET_N" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "MIV_ESS_0:PRESETN" "MIV_RV32_CFG3_0:RESETN" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:INIT_DONE" "PF_INIT_MONITOR_0:DEVICE_INIT_DONE" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:PLL_LOCK" "PF_CCC_0:PLL_LOCK_0" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG3_0:MSYS_EI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32_CFG3_0:EXT_IRQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TDO" "CoreJTAGDebug_0:TGT_TDO_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:OUT0_FABCLK_0" "MIV_RV32_CFG3_0:CLK" "CoreGPIO_IN:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_OUT:PCLK" "CoreRESET_PF_0:CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:PLL_LOCK_0" "CoreRESET_PF_0:PLL_LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_INIT_MONITOR_0:DEVICE_INIT_DONE" "CoreRESET_PF_0:INIT_DONE" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_CCC_0:REF_CLK_0" "PF_OSC_0:RCOSC_160MHZ_GL" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreRESET_PF_0:EXT_RST_N" "USER_RST" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"USER_RST" "CoreRESET_PF_0:EXT_RST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"PF_INIT_MONITOR_0:FABRIC_POR_N" "CoreRESET_PF_0:FPGA_POR_N"} + # Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "SW_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "SW_4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "SW_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "SW_4" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } # Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:APB_MSTR" "CoreAPB3_0:APB3mmaster" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_3_mTARGET" "CoreTimer_0:APBslave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_4_mTARGET" "CoreTimer_1:APBslave" } +sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG3_0:APB_MSTR" } + # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl new file mode 100644 index 0000000..07267e6 --- /dev/null +++ b/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl @@ -0,0 +1,208 @@ +# Exporting Component Description of MIV_ESS_0 to TCL +# Family: PolarFire +# Part Number: MPF300TS-FCG484I +# Create and Configure the core component MIV_ESS_0 +create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -component_name {MIV_ESS_0} -download_core -params {\ +"APBSLOT11ENABLE:false" \ +"APBSLOT12ENABLE:false" \ +"APBSLOT13ENABLE:false" \ +"APBSLOT14ENABLE:false" \ +"APBSLOT15ENABLE:false" \ +"APBSLOT3ENABLE:true" \ +"APBSLOT4ENABLE:true" \ +"APB_DST_ADDR_LOWER:0x0" \ +"APB_DST_ADDR_UPPER:0x4000" \ +"APB_DWIDTH:32" \ +"APB_INITIATOR_0_MIRROR:true" \ +"APB_WIDTH:32" \ +"BAUD_VALUE:1" \ +"BAUD_VAL_FRCTN:0" \ +"BAUD_VAL_FRCTN_EN:false" \ +"BOOTLOAD_EN:false" \ +"BOOTLOAD_SOURCE:1" \ +"BUSY_SIGNAL:true" \ +"CFG_CLK:7" \ +"CFG_FIFO_DEPTH:32" \ +"CFG_FRAME_SIZE:8" \ +"CFG_MODE:0" \ +"CFG_MOT_MODE:0" \ +"CFG_MOT_SSEL:false" \ +"CFG_NSC_OPERATION:0" \ +"CFG_TI_JMB_FRAMES:false" \ +"CFG_TI_NSC_CUSTOM:0" \ +"CFG_TI_NSC_FRC:false" \ +"DATA_WORD_CNT:8192" \ +"FAMILY_TARGET:26" \ +"FIXEDMODE:0" \ +"FIXED_CONFIG_0:true" \ +"FIXED_CONFIG_1:true" \ +"FIXED_CONFIG_10:false" \ +"FIXED_CONFIG_11:false" \ +"FIXED_CONFIG_12:false" \ +"FIXED_CONFIG_13:false" \ +"FIXED_CONFIG_14:false" \ +"FIXED_CONFIG_15:false" \ +"FIXED_CONFIG_16:false" \ +"FIXED_CONFIG_17:false" \ +"FIXED_CONFIG_18:false" \ +"FIXED_CONFIG_19:false" \ +"FIXED_CONFIG_2:true" \ +"FIXED_CONFIG_20:false" \ +"FIXED_CONFIG_21:false" \ +"FIXED_CONFIG_22:false" \ +"FIXED_CONFIG_23:false" \ +"FIXED_CONFIG_24:false" \ +"FIXED_CONFIG_25:false" \ +"FIXED_CONFIG_26:false" \ +"FIXED_CONFIG_27:false" \ +"FIXED_CONFIG_28:false" \ +"FIXED_CONFIG_29:false" \ +"FIXED_CONFIG_3:true" \ +"FIXED_CONFIG_30:false" \ +"FIXED_CONFIG_31:false" \ +"FIXED_CONFIG_4:false" \ +"FIXED_CONFIG_5:false" \ +"FIXED_CONFIG_6:false" \ +"FIXED_CONFIG_7:false" \ +"FIXED_CONFIG_8:false" \ +"FIXED_CONFIG_9:false" \ +"GPIO_EN:true" \ +"GUI_ALIGN_0:true" \ +"I2C_CLK_DIVISOR:99" \ +"I2C_EN:false" \ +"I2C_MULTI_ADDR_BYTES:1" \ +"I2C_SLV_ADDR:0x50" \ +"I2C_START_ADDR_LOWER:0x0" \ +"I2C_START_ADDR_UPPER:0x0" \ +"INTERNAL_MTIME_IRQ:true" \ +"INT_BUS:0" \ +"IO_INT_TYPE_0:7" \ +"IO_INT_TYPE_1:7" \ +"IO_INT_TYPE_10:7" \ +"IO_INT_TYPE_11:7" \ +"IO_INT_TYPE_12:7" \ +"IO_INT_TYPE_13:7" \ +"IO_INT_TYPE_14:7" \ +"IO_INT_TYPE_15:7" \ +"IO_INT_TYPE_16:7" \ +"IO_INT_TYPE_17:7" \ +"IO_INT_TYPE_18:7" \ +"IO_INT_TYPE_19:7" \ +"IO_INT_TYPE_2:7" \ +"IO_INT_TYPE_20:7" \ +"IO_INT_TYPE_21:7" \ +"IO_INT_TYPE_22:7" \ +"IO_INT_TYPE_23:7" \ +"IO_INT_TYPE_24:7" \ +"IO_INT_TYPE_25:7" \ +"IO_INT_TYPE_26:7" \ +"IO_INT_TYPE_27:7" \ +"IO_INT_TYPE_28:7" \ +"IO_INT_TYPE_29:7" \ +"IO_INT_TYPE_3:7" \ +"IO_INT_TYPE_30:7" \ +"IO_INT_TYPE_31:7" \ +"IO_INT_TYPE_4:7" \ +"IO_INT_TYPE_5:7" \ +"IO_INT_TYPE_6:7" \ +"IO_INT_TYPE_7:7" \ +"IO_INT_TYPE_8:7" \ +"IO_INT_TYPE_9:7" \ +"IO_NUM:4" \ +"IO_TYPE_0:2" \ +"IO_TYPE_1:2" \ +"IO_TYPE_10:0" \ +"IO_TYPE_11:0" \ +"IO_TYPE_12:0" \ +"IO_TYPE_13:0" \ +"IO_TYPE_14:0" \ +"IO_TYPE_15:0" \ +"IO_TYPE_16:0" \ +"IO_TYPE_17:0" \ +"IO_TYPE_18:0" \ +"IO_TYPE_19:0" \ +"IO_TYPE_2:2" \ +"IO_TYPE_20:0" \ +"IO_TYPE_21:0" \ +"IO_TYPE_22:0" \ +"IO_TYPE_23:0" \ +"IO_TYPE_24:0" \ +"IO_TYPE_25:0" \ +"IO_TYPE_26:0" \ +"IO_TYPE_27:0" \ +"IO_TYPE_28:0" \ +"IO_TYPE_29:0" \ +"IO_TYPE_3:2" \ +"IO_TYPE_30:0" \ +"IO_TYPE_31:0" \ +"IO_TYPE_4:0" \ +"IO_TYPE_5:0" \ +"IO_TYPE_6:0" \ +"IO_TYPE_7:0" \ +"IO_TYPE_8:0" \ +"IO_TYPE_9:0" \ +"IO_VAL_0:0" \ +"IO_VAL_1:0" \ +"IO_VAL_10:0" \ +"IO_VAL_11:0" \ +"IO_VAL_12:0" \ +"IO_VAL_13:0" \ +"IO_VAL_14:0" \ +"IO_VAL_15:0" \ +"IO_VAL_16:0" \ +"IO_VAL_17:0" \ +"IO_VAL_18:0" \ +"IO_VAL_19:0" \ +"IO_VAL_2:0" \ +"IO_VAL_20:0" \ +"IO_VAL_21:0" \ +"IO_VAL_22:0" \ +"IO_VAL_23:0" \ +"IO_VAL_24:0" \ +"IO_VAL_25:0" \ +"IO_VAL_26:0" \ +"IO_VAL_27:0" \ +"IO_VAL_28:0" \ +"IO_VAL_29:0" \ +"IO_VAL_3:0" \ +"IO_VAL_30:0" \ +"IO_VAL_31:0" \ +"IO_VAL_4:0" \ +"IO_VAL_5:0" \ +"IO_VAL_6:0" \ +"IO_VAL_7:0" \ +"IO_VAL_8:0" \ +"IO_VAL_9:0" \ +"IRQ_EN_SIGNAL:true" \ +"MTIME_PRESCALER:1000" \ +"MTIME_RTC_CLOCK:false" \ +"OE_TYPE:1" \ +"PLIC_EN:false" \ +"PLIC_IRQS:8" \ +"PRG_BIT8:0" \ +"PRG_PARITY:0" \ +"READ_4BYTE_ADDR:0" \ +"READ_MIRROR:false" \ +"READ_STATUS_TYPE:false" \ +"RST_EXTPROC_DURATION:1000" \ +"RST_RECOVERY_DURATION:8" \ +"RX_FIFO:0" \ +"RX_LEGACY_MODE:0" \ +"SPI_CLK_RATIO:8" \ +"SPI_EN:false" \ +"SPI_SRC_ADDR_LOWER:0x0" \ +"SPI_SRC_ADDR_UPPER:0x0" \ +"SS_DESELECT_DURATION:8" \ +"SW_RESET_TYPE:0" \ +"SYS_TIMER_EN:false" \ +"TX_FIFO:0" \ +"UART_EN:true" \ +"UART_STATUS_FLAGS:false" \ +"UPROM_SRC_ADDR_LOWER:0x0" \ +"UPROM_SRC_ADDR_UPPER:0x0" \ +"USE_SOFT_FIFO:0" \ +"WDT_EN:false" \ +"WRITE_MIRROR:false" \ +"WRITE_PORT:1" \ +"uDMA_EN:false" } +# Exporting Component Description of MIV_ESS_0 to TCL done diff --git a/README.md b/README.md index 2b548d7..bd1c5b5 100644 --- a/README.md +++ b/README.md @@ -20,19 +20,19 @@ To download or clone the repository: # Libero Projects -The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2022.1. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/PolarFire-FPGA-Splash-Kit/releases) in this repository. +The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2022.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/PolarFire-FPGA-Splash-Kit/releases) in this repository. ## Design Features The Libero designs include the following features: -* A soft RISC-V processor +* A soft RISC-V processor operating at 50 MHz * A RISC-V debug block allowing on-target debug using SoftConsole -* The operating frequency of the design is 50MHz -* Target memory is SRAM (32kB) -* User peripherals: 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) +* An Extended Subsystem with integrated peripherals +* Target SRAM/TCM memory (32kB) +* User peripherals: MIV_ESS, 2 Timers, UART, 2 GPIO Inputs and 4 GPIO Outputs (GPIOs use fixed configs for simplicity and better resource utilization) ## Target Hardware Details of the PolarFire FPGA Splash-Kit and it's features can be found: -* [PolarFire-Splash-Kit](https://www.microsemi.com/existing-parts/parts/144001) (MPF300TS_ES) +* [MPF300-SPLASH-KIT](https://www.microchip.com/en-us/development-tool/MPF300-SPLASH-KIT) # FlashPro Express The FlashPro_Express_Projects folder contains the pre-generated programming files, which can be downloaded directly to the target board using FlashPro Express. @@ -40,19 +40,19 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file # Design Tools The following design tools are required. -## Libero SoC v2022.1 -[Libero SoC](https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads) is Microchip's FPGA design software. +## Libero SoC v2022.2 +[Libero SoC](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#downloads) is Microchip's FPGA design software. ## FlashPro Express -[FlashPro Express](http://www.microsemi.com/products/fpga-soc/design-resources/programming/flashpro#software) is Microchip's Programming and debug tool. It is included in the Libero SoC software and is also +[FlashPro Express](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/programming-and-debug/flashpro-and-flashpro-express#software) is Microchip's Programming and debug tool. It is included in the Libero SoC software and is also available as a standalone application. Please note, that if Libero SoC is already on your system, you do not need the standalone version. # Software ## SoftConsole -[SoftConsole](https://www.microsemi.com/product-directory/design-tools/4879-softconsole) is Microchip’s free software development environment facilitating the rapid development of bare-metal and RTOS based C/C++ software for Microchip CPU and SoC based FPGAs. It provides development and debug support for all Microchip SoC FPGAs and 32-bit soft IP CPUs. SoftConsole can be downloaded. +[SoftConsole](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/soc-fpga/softconsole) is Microchip’s free software development environment facilitating the rapid development of bare-metal and RTOS based C/C++ software for Microchip CPU and SoC based FPGAs. It provides development and debug support for all Microchip SoC FPGAs and 32-bit soft IP CPUs. SoftConsole can be downloaded. ## Mi-V Soft processor Bare Metal Examples -A [Firmware](https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples) +A [Firmware](https://mi-v-ecosystem.github.io/redirects/miv-soft/miv-rv32-bare-metal-examples.md) repository that provides bare metal embedded software example projects built with Microchip's SoftConsole IDE.