diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md
index fa0ba61..f13b7b1 100644
--- a/FlashPro_Express_Projects/README.md
+++ b/FlashPro_Express_Projects/README.md
@@ -21,7 +21,7 @@ The programming files contained under this folder were exported from the designs
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A soft RISC-V processor
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
 * Target memory is SRAM (32kB)
diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md
index 5b46c15..5a4c3cf 100644
--- a/Libero_Projects/README.md
+++ b/Libero_Projects/README.md
@@ -74,7 +74,7 @@ In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE" were entered. T
 
 ## Design Features
 The Libero designs include the following features:
-* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs)
+* A soft RISC-V processor
 * A RISC-V debug block allowing on-target debug using SoftConsole
 * The operating frequency of the design is 50MHz
 * Target memory is SRAM (32kB)