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Libero SoC 2023.1 designs - v1.0
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@CLappin CLappin released this 13 Jul 09:47
· 6 commits to main since this release
2023.1-v1.0
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Updated to support Libero SoC v2023.1

  • Notice added to Libero_Project and FlashPro_Express_Projects regarding the work around for the MTVEC issue for FreeRTOS and the Fast Interrupt issue in the latest release of the MIV_RV32. Please read the readme files in each of those folders to see if you are effected.

Features of this release:

  • Updated .job files to v2023.1.
  • Engineering Samples .job files not included.
  • MIV_RV32 and support components update to latest release.
  • Refactored TCL script library, updated for modularity, parameterization and input handling
    • New dynamic paths added, should allow for better performance on non-Windows based OS systems.
    • Design components are now downloaded dynamically for each design configuration
    • Removed glitches which may have been seen when adapting the designs for VHDL
    • Project folders for ES designs have been uniquified for traceability
    • Project folders for MIV_RV32, MIV_RV32IMAF and MIV_RV32IMA have been uniquified for clarity and traceability
  • Improved TCL output messaging with regards to the design building and design flow progression
  • An example software program has been added to LSRAM-based configurations. After programming the bitstream, software boots out of the box from the LSRAM.
  • The clocking circuitry in all of the designs has been improved. A new 50MHz clock reference for the CCC has been added by replacing the RC Oscillator. Timing has been improved across the designs
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