From 3ef6aa838a25b24a57371aa27d2a336efa966e88 Mon Sep 17 00:00:00 2001 From: CLappin Date: Tue, 9 Nov 2021 10:42:29 +0000 Subject: [PATCH 1/2] Update README.md removed hyperlink. --- FlashPro_Express_Projects/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md index 4dd7001..54a1052 100644 --- a/FlashPro_Express_Projects/README.md +++ b/FlashPro_Express_Projects/README.md @@ -21,7 +21,7 @@ The programming files contained under this folder were exported from the designs ## Design Features The Libero designs include the following features: -* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs) +* A soft RISC-V processor * A RISC-V debug block allowing on-target debug using SoftConsole * The operating frequency of the design is 50MHz * Target memory is SRAM (32kB) From 49e2c22a1864950dc887fee78478cb15ae01ef07 Mon Sep 17 00:00:00 2001 From: CLappin Date: Tue, 9 Nov 2021 10:43:03 +0000 Subject: [PATCH 2/2] Update README.md removed hyperlink. --- Libero_Projects/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md index 39bde96..8c8e85a 100644 --- a/Libero_Projects/README.md +++ b/Libero_Projects/README.md @@ -71,7 +71,7 @@ In the examples above the arguments "CFG1" and "CFG1 SYNTHESIZE" were entered. T ## Design Features The Libero designs include the following features: -* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs) +* A soft RISC-V processor * A RISC-V debug block allowing on-target debug using SoftConsole * The operating frequency of the design is 40MHz **(The hw_platform.h file in the SoftConsole project will require the SYS_CLK_FREQ parameter to be set to #define SYS_CLK_FREQ 40000000UL)** * Target memory is SRAM (32kB)