From f2eecc52df3d97f814995a9f7050040a6293b6b1 Mon Sep 17 00:00:00 2001 From: CLappin Date: Tue, 9 Nov 2021 09:38:01 +0000 Subject: [PATCH] Update README.md Updated hyperlinks. --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 7da1ca7..15f8826 100644 --- a/README.md +++ b/README.md @@ -12,7 +12,7 @@ FlashPro Express projects containing pre-generated programming files are also av To download or clone the repository: - $ git clone https://github.com/RISCV-on-Microsemi-FPGA/RTG4-Development-Kit.git + $ git clone https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit.git $ Running from the zipped sources 1. Download the zipped sources via the "Code" button using "Download Zip" button @@ -20,11 +20,11 @@ To download or clone the repository: # Libero Projects -The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2021.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/RISCV-on-Microsemi-FPGA/Future-Avalanche-Board/releases) in this repository. +The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2021.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository. ## Design Features The Libero designs include the following features: -* A soft RISC-V [processor](https://github.com/RISCV-on-Microsemi-FPGA/CPUs) +* A soft RISC-V processor. * A RISC-V debug block allowing on-target debug using SoftConsole * The operating frequency of the design is 50MHz * Target memory is SRAM (32kB)