diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMAF_CFG1_BaseDesign.job new file mode 100644 index 0000000..aee3467 Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMAF_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG1_BaseDesign.job new file mode 100644 index 0000000..c8cc331 Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG2_BaseDesign.job new file mode 100644 index 0000000..2c2d3f3 Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32IMA_CFG2_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG1_BaseDesign.job new file mode 100644 index 0000000..638b6d9 Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG1_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG2_BaseDesign.job new file mode 100644 index 0000000..aa474ed Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG2_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG3_BaseDesign.job new file mode 100644 index 0000000..d862ab1 Binary files /dev/null and b/FlashPro_Express_Projects/Programming_Files/RTG4_DEV_MIV_RV32_CFG3_BaseDesign.job differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job deleted file mode 100644 index 753d8d5..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMAF_CFG1_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job deleted file mode 100644 index a305e91..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG1_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job deleted file mode 100644 index e4b41ad..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32IMA_CFG2_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG1_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG1_BaseDesign.job deleted file mode 100644 index 0e1cf0e..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG1_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG2_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG2_BaseDesign.job deleted file mode 100644 index 286583e..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG2_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG3_BaseDesign.job b/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG3_BaseDesign.job deleted file mode 100644 index c034865..0000000 Binary files a/FlashPro_Express_Projects/Programming_Files/RTG4_Dev_Kit_PS_MIV_RV32_CFG3_BaseDesign.job and /dev/null differ diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md index 5560da3..b2fda8e 100644 --- a/FlashPro_Express_Projects/README.md +++ b/FlashPro_Express_Projects/README.md @@ -1,6 +1,22 @@ # RTG4 Development Kit FPGA Programming Files -This folder contains FlashPro Express v2022.2 projects for the RTG4 Development Kit Mi-V sample designs. +This folder contains FlashPro Express v2023.1 projects for the RTG4 Development Kit Mi-V sample designs. + +## Notice +1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. + +2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP. + +.macro STORE_CONTEXT +addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES +SREG x1, 0 * REGBYTES(sp) +SREG x1, 0 * REGBYTES(sp) // re-write the return address to workaround +SREG x2, 1 * REGBYTES(sp) +SREG x3, 2 * REGBYTES(sp) + +Please see the latest MIV_RV32 HAL available [here](https://github.com/Mi-V-Soft-RISC-V/platform/tree/main/miv_rv32_hal). + +A new version of the MIV_RV32 will be released to fix both the issues mentioned above. ## FlashPro Express The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express. diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md index 3fa64c7..f69b7d2 100644 --- a/Libero_Projects/README.md +++ b/Libero_Projects/README.md @@ -1,15 +1,32 @@ # RTG4 Development Kit Mi-V Sample FPGA Designs -This folder contains Tcl scripts that build Libero SoC v2022.2 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. +This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. > This design only supports the production silicon (PS) die +## Notice +1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples. + +2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP. + +.macro STORE_CONTEXT +addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES +SREG x1, 0 * REGBYTES(sp) +SREG x1, 0 * REGBYTES(sp) // re-write the return address to workaround +SREG x2, 1 * REGBYTES(sp) +SREG x3, 2 * REGBYTES(sp) + +Please see the latest MIV_RV32 HAL available [here](https://github.com/Mi-V-Soft-RISC-V/platform/tree/main/miv_rv32_hal). + +A new version of the MIV_RV32 will be released to fix both the issues mentioned above. + + #### RTG4_Dev_Kit_MIV_RV32_BaseDesign | Config | Description| | :------:|:----------------------------------------| -| CFG1 | This design uses the MIV_RV32 core configured as follows: | -| CFG2 | This design uses the MIV_RV32 core configured as follows: | -| CFG3 | This design uses the MIV_RV32 core configured as follows: | +| CFG1 | This design uses the MIV_RV32 core configured as follows: | +| CFG2 | This design uses the MIV_RV32 core configured as follows: | +| CFG3 | This design uses the MIV_RV32 core configured as follows: | #### RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl index 73e603f..5b94a4e 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl @@ -1,251 +1,137 @@ +# Parse user arguments set config [string toupper [lindex $argv 0]] -set design_flow_stage [string toupper [lindex $argv 1]] -set die_variant [string toupper [lindex $argv 2]] - -set hw_platform RTG4_Dev_Kit -set soft_cpu MIV_RV32IMAF -set sd_reference BaseDesign - -#ES device is not supported in these scripts - -# -# Procedure blocks start -proc create_new_project_label { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nCreating a new project for the 'RTG4_Dev_Kit' board. \ - \r\n-------------------------------------------------------------------------------" -} - -proc project_exists { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: A project exists for the 'RTG4_Dev_Kit' with this configuration. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_first_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 1st Argument has been entered. \ - \r\nInfo: Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' \ - \r\nInfo: Default 'CFG1' design has been selected. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_first_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 1st Argument has been entered. No valid configuration detected. \ - \r\nInfo: Make sure you enter a valid first argument -'CFG1..CFGn'. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_second_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 2nd Argument has been entered. \ - \r\nInfo: Enter the 2nd Argument after the 1st to be taken further in the Design Flow. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_second_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 2nd Argument has been entered. \ - \r\nInfo: Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'.\ - \r\n-------------------------------------------------------------------------------" -} - -proc no_third_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 3rd Argument has been entered. \ - \r\nInfo: Assuming the default 'PS' die type as target \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_third_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 3rd Argument has been entered. \ - \r\nInfo: Only valid 3rd Argument is 'PS' or ''. \ - \r\n-------------------------------------------------------------------------------" -} - -proc base_design_built { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: BaseDesign built. \ - \r\n-------------------------------------------------------------------------------" -} - -proc es_device_not_supported { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Engineering Sample (ES) die not supported in these scripts. \ - \r\n-------------------------------------------------------------------------------" -} - -proc legacy_core_msg { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nWarning: This Libero design uses a legacy Mi-V soft processor core. \ - \r\nWarning: Legacy Mi-V soft processors are not recommended for new designs. \ - \r\nInfo: MIV_RV32 is recommended for new designs. \ - \r\n-------------------------------------------------------------------------------" -} - -proc download_required_direct_cores { } { - download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} -} - -proc pre_configure_place_and_route { } { - configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:false} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:false} -} - -proc run_verify_timing { } { - run_tool -name {VERIFYTIMING} -} -# Procedure blocks end -# - -#Filter for argument argv0: config -if {$config == ""} then { - set config "CFG1" - no_first_argument_entered -} elseif {$config != "CFG1"} then { - puts "config is: $config" - invalid_first_argument - exit 1 -} else { - puts "Info: Configuration selected: $config" -} - -#Filter for argument argv1: design flow -if {$design_flow_stage == ""} then { - no_second_argument_entered -} elseif {$design_flow_stage == "SYNTHESIZE" - || $design_flow_stage == "PLACE_AND_ROUTE" - || $design_flow_stage == "GENERATE_BITSTREAM" - || $design_flow_stage == "EXPORT_PROGRAMMING_FILE"} then { - puts "Info: Design flow run tool selected: $design_flow_stage" -} elseif {$design_flow_stage == "ES" - || $design_flow_stage == "PS"} then { - set die_variant "$design_flow_stage" -} else { - invalid_second_argument - exit 1 -} - -#Filter for argument argv2: die type -if {$die_variant == ""} { - set die_variant "PS" - no_third_argument_entered -} elseif {$die_variant == "PS"} { - puts "Info: Die type selected: $die_variant" -} elseif {$die_variant == "ES"} { - es_device_not_supported - exit 1 -} else { - invalid_third_argument - exit 1 -} - -append target_board $hw_platform _ $die_variant -append project_folder_name MIV_ $config _BD -set project_dir "./$project_folder_name" -append project_name $target_board _ $soft_cpu _ $config _ $sd_reference - -if {"$config" == "CFG1"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" != "PS"} then { - invalid_third_argument - } else { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - } - download_required_direct_cores - source ./import/components/IMAF_CFG1/import_sd_and_constraints_rtg4_imaf_cfg1.tcl - save_project - base_design_built - } +set designFlow [string toupper [lindex $argv 1]] +set dieType [string toupper [lindex $argv 2]] + +# Get the path of the currently executing script and set execution directory +set scriptPath [info script] +set scriptDir [file dirname $scriptPath] + +# Load the TCL file with all of the procedural blocks +source $scriptDir/import/proc_blocks.tcl + +# Set valid configurations +set hwPlatform "RTG4_DEV" +set hwFamily "POLARFIRE" +set cpuRef "MIV_RV32IMAF" +set validConfigs [list "CFG1"] +set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"] +set validDieTypes [list "PS" ""] +set sdName {BaseDesign} +set exProgramHex "miv-rv32i-systick-blinky.hex" + +# Call procedures to validate user arguments +set config [verify_config $config] +set designFlow [verify_designFlow $designFlow] +set dieType [verify_dieType $dieType] + +# Prime the TCL builder script for desired build settings +set softCpu [get_legacy_core_name $config $cpuRef] +set cpuGroup [expr {$softCpu eq "MIV_RV32" ? "MIV_RV32" : "MIV_Legacy"}] +set sdBuildScript [get_config_builder $config $validConfigs $cpuGroup] +get_die_configuration $hwPlatform $dieType +print_message "Runnig script: $scriptPath \nDesign Arguments: $config $designFlow $dieType \nDesign Build Script: $sdBuildScript" + +# Configure Libero project files and directories +set projectName "${hwPlatform}[expr {$dieType eq "ES" ? "_${dieType}" : ""}]_${cpuRef}_${config}_${sdName}" ; # projectName only reflects dieType if dieType is "ES" +append projectFolderName "${cpuRef}_${config}_BD" +set projectDir $scriptDir/$projectFolderName +puts "Info: projectName: $projectName" +puts "Info: projectFolderName: $projectFolderName" +puts "Info: projectDir: $projectDir" + +# Build Libero design project for selected configuration and hardware +if {[file exists $projectDir] == 1} then { + print_message "Error: A project with '$config' configuration already exists for the '$hwPlatform'." } else { - invalid_first_argument - exit 1 -} - + print_message "Creating a new project for the '$hwPlatform' board." + new_project \ + -location $projectDir \ + -name $projectName \ + -project_description {} \ + -block_mode 0 \ + -standalone_peripheral_initialization 0 \ + -instantiate_in_smartdesign 1 \ + -ondemand_build_dh 1 \ + -hdl {VERILOG} \ + -family {RTG4} \ + -die $diePackage \ + -package $dieSize \ + -speed $dieSpeed \ + -die_voltage {1.2} \ + -part_range $tempGrade \ + -adv_options {IO_DEFT_STD:LVCMOS 2.5V} \ + -adv_options {RESTRICTPROBEPINS:1} \ + -adv_options {RESTRICTSPIPINS:0} \ + -adv_options "TEMPR:$tempGrade" \ + -adv_options "VCCI_1.2_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.8_VOLTR:$tempGrade" \ + -adv_options "VCCI_2.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_3.3_VOLTR:$tempGrade" \ + -adv_options "VOLTR:$tempGrade" + project_settings -enable_set_mitigation 0 +} + +# Download the required direct cores +#download_required_direct_cores "$hwPlatform" "$softCpu" "$config" + +# Copy the example software program into the project directory +# file copy -force $scriptDir/import/software_example/$cpuGroup/$config/hex $projectDir + +# Import and build the design's SmartDesign +print_message "Building the $sdName..." +source $scriptDir/import/build_smartdesign/$sdBuildScript +print_message "$sdName Built." + +# Optimizations - add constraints, modify package files if needed +print_message "Applying Design Optimizations and Constraints..." +source $scriptDir/import/design_optimization.tcl +print_message "Optimization and Constraints Applied." + +# Configure 'Place & Route' tool pre_configure_place_and_route -if {"$design_flow_stage" == "SYNTHESIZE"} then { - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Synthesis... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Synthesize' from the design flow +if {"$designFlow" == "SYNTHESIZE"} then { + print_message "Starting Synthesis..." run_tool -name {SYNTHESIZE} save_project + print_message "Synthesis Complete." - puts "\n------------------------------------------------------------------------------- \ - \r\nSynthesis Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Place and Route... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Place & Route' from the design flow +} elseif {"$designFlow" == "PLACE_AND_ROUTE"} then { + print_message "Starting Place and Route..." run_verify_timing save_project + print_message "Place and Route Completed successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nPlace and Route Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nGenerating Bitstream... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Generate Bitstream' from the design flow +} elseif {"$designFlow" == "GENERATE_BITSTREAM"} then { + print_message "Generating Bitstream..." run_verify_timing run_tool -name {GENERATEPROGRAMMINGDATA} run_tool -name {GENERATEPROGRAMMINGFILE} save_project + print_message "Bitstream Generated successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nBitstream Generated. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nExporting Programming Files... \ - \r\n-------------------------------------------------------------------------------" +# Run 'Export Programming Job File' from the design flow (into default location) +} elseif {"$designFlow" == "EXPORT_PROGRAMMING_FILE"} then { + print_message "Exporting Programming Files..." run_verify_timing + run_tool -name {GENERATEPROGRAMMINGFILE} - export_prog_job \ - -job_file_name $project_name \ - -export_dir $project_dir/designer/BaseDesign/export \ + -job_file_name $projectName \ + -export_dir $projectDir/designer/$sdName/export \ -force_rtg4_otp 0 \ -design_bitstream_format {PPD} save_project - - - puts "\n------------------------------------------------------------------------------- \ - \r\nProgramming Files Exported. \ - \r\n-------------------------------------------------------------------------------" + print_message "Programming Files Exported." } else { - puts "Info: No design flow tool run." + print_message "Info: No design flow tool run." } -legacy_core_msg +# Done \ No newline at end of file diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl index a104c66..1bddf20 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl @@ -1,266 +1,137 @@ +# Parse user arguments set config [string toupper [lindex $argv 0]] -set design_flow_stage [string toupper [lindex $argv 1]] -set die_variant [string toupper [lindex $argv 2]] - -set hw_platform RTG4_Dev_Kit -set soft_cpu MIV_RV32IMA -set sd_reference BaseDesign - -#ES device is not supported in these scripts - -# -# Procedure blocks start -proc create_new_project_label { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nCreating a new project for the 'RTG4_Dev_Kit' board. \ - \r\n-------------------------------------------------------------------------------" -} - -proc project_exists { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: A project exists for the 'RTG4_Dev_Kit' with this configuration. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_first_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 1st Argument has been entered. \ - \r\nInfo: Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' \ - \r\nInfo: Default 'CFG1' design has been selected. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_first_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 1st Argument has been entered. No valid configuration detected. \ - \r\nInfo: Make sure you enter a valid first argument -'CFG1..CFGn'. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_second_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 2nd Argument has been entered. \ - \r\nInfo: Enter the 2nd Argument after the 1st to be taken further in the Design Flow. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_second_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 2nd Argument has been entered. \ - \r\nInfo: Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'.\ - \r\n-------------------------------------------------------------------------------" -} - -proc no_third_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 3rd Argument has been entered. \ - \r\nInfo: Assuming the default 'PS' die type as target \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_third_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 3rd Argument has been entered. \ - \r\nInfo: Only valid 3rd Argument is 'PS' or ''. \ - \r\n-------------------------------------------------------------------------------" -} - -proc base_design_built { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: BaseDesign built. \ - \r\n-------------------------------------------------------------------------------" -} - -proc es_device_not_supported { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Engineering Sample (ES) die not supported in these scripts. \ - \r\n-------------------------------------------------------------------------------" -} - -proc legacy_core_msg { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nWarning: This Libero design uses a legacy Mi-V soft processor core. \ - \r\nWarning: Legacy Mi-V soft processors are not recommended for new designs. \ - \r\nInfo: MIV_RV32 is recommended for new designs. \ - \r\n-------------------------------------------------------------------------------" -} - -proc download_required_direct_cores { } { - download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} -} - -proc pre_configure_place_and_route { } { - configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:false} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:false} -} - -proc run_verify_timing { } { - run_tool -name {VERIFYTIMING} -} -# Procedure blocks end -# - -#Filter for argument argv0: config -if {$config == ""} then { - set config "CFG1" - no_first_argument_entered -} elseif {$config != "CFG1" - && $config != "CFG2"} then { - puts "config is: $config" - invalid_first_argument - exit 1 -} else { - puts "Info: Configuration selected: $config" -} - -#Filter for argument argv1: design flow -if {$design_flow_stage == ""} then { - no_second_argument_entered -} elseif {$design_flow_stage == "SYNTHESIZE" - || $design_flow_stage == "PLACE_AND_ROUTE" - || $design_flow_stage == "GENERATE_BITSTREAM" - || $design_flow_stage == "EXPORT_PROGRAMMING_FILE"} then { - puts "Info: Design flow run tool selected: $design_flow_stage" -} elseif {$design_flow_stage == "ES" - || $design_flow_stage == "PS"} then { - set die_variant "$design_flow_stage" -} else { - invalid_second_argument - exit 1 -} - -#Filter for argument argv2: die type -if {$die_variant == ""} { - set die_variant "PS" - no_third_argument_entered -} elseif {$die_variant == "PS"} { - puts "Info: Die type selected: $die_variant" -} elseif {$die_variant == "ES"} { - es_device_not_supported - exit 1 +set designFlow [string toupper [lindex $argv 1]] +set dieType [string toupper [lindex $argv 2]] + +# Get the path of the currently executing script and set execution directory +set scriptPath [info script] +set scriptDir [file dirname $scriptPath] + +# Load the TCL file with all of the procedural blocks +source $scriptDir/import/proc_blocks.tcl + +# Set valid configurations +set hwPlatform "RTG4_DEV" +set hwFamily "POLARFIRE" +set cpuRef "MIV_RV32IMA" +set validConfigs [list "CFG1" "CFG2"] +set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"] +set validDieTypes [list "PS" ""] +set sdName {BaseDesign} +# set exProgramHex "miv-rv32i-systick-blinky.hex" + +# Call procedures to validate user arguments +set config [verify_config $config] +set designFlow [verify_designFlow $designFlow] +set dieType [verify_dieType $dieType] + +# Prime the TCL builder script for desired build settings +set softCpu [get_legacy_core_name $config $cpuRef] +set cpuGroup [expr {$softCpu eq "MIV_RV32" ? "MIV_RV32" : "MIV_Legacy"}] +set sdBuildScript [get_config_builder $config $validConfigs $cpuGroup] +get_die_configuration $hwPlatform $dieType +print_message "Runnig script: $scriptPath \nDesign Arguments: $config $designFlow $dieType \nDesign Build Script: $sdBuildScript" + +# Configure Libero project files and directories +set projectName "${hwPlatform}[expr {$dieType eq "ES" ? "_${dieType}" : ""}]_${cpuRef}_${config}_${sdName}" ; # projectName only reflects dieType if dieType is "ES" +append projectFolderName "${cpuRef}_${config}_BD" +set projectDir $scriptDir/$projectFolderName +puts "Info: projectName: $projectName" +puts "Info: projectFolderName: $projectFolderName" +puts "Info: projectDir: $projectDir" + +# Build Libero design project for selected configuration and hardware +if {[file exists $projectDir] == 1} then { + print_message "Error: A project with '$config' configuration already exists for the '$hwPlatform'." } else { - invalid_third_argument - exit 1 -} - -append target_board $hw_platform _ $die_variant -append project_folder_name MIV_ $config _BD -set project_dir "./$project_folder_name" -append project_name $target_board _ $soft_cpu _ $config _ $sd_reference - -if {"$config" == "CFG1"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" != "PS"} then { - invalid_third_argument - } else { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - } - download_required_direct_cores - source ./import/components/IMA_CFG1/import_sd_and_constraints_rtg4_ima_cfg1.tcl - save_project - base_design_built - } -} elseif {"$config" == "CFG2"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" != "PS"} then { - invalid_third_argument - } else { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - } - download_required_direct_cores - source ./import/components/IMA_CFG2/import_sd_and_constraints_rtg4_ima_cfg2.tcl - save_project - base_design_built - } -} else { - invalid_first_argument - exit 1 -} - + print_message "Creating a new project for the '$hwPlatform' board." + new_project \ + -location $projectDir \ + -name $projectName \ + -project_description {} \ + -block_mode 0 \ + -standalone_peripheral_initialization 0 \ + -instantiate_in_smartdesign 1 \ + -ondemand_build_dh 1 \ + -hdl {VERILOG} \ + -family {RTG4} \ + -die $diePackage \ + -package $dieSize \ + -speed $dieSpeed \ + -die_voltage {1.2} \ + -part_range $tempGrade \ + -adv_options {IO_DEFT_STD:LVCMOS 2.5V} \ + -adv_options {RESTRICTPROBEPINS:1} \ + -adv_options {RESTRICTSPIPINS:0} \ + -adv_options "TEMPR:$tempGrade" \ + -adv_options "VCCI_1.2_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.8_VOLTR:$tempGrade" \ + -adv_options "VCCI_2.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_3.3_VOLTR:$tempGrade" \ + -adv_options "VOLTR:$tempGrade" + project_settings -enable_set_mitigation 0 +} + +# Download the required direct cores +#download_required_direct_cores "$hwPlatform" "$softCpu" "$config" + +# Copy the example software program into the project directory +# file copy -force $scriptDir/import/software_example/$cpuGroup/$config/hex $projectDir + +# Import and build the design's SmartDesign +print_message "Building the $sdName..." +source $scriptDir/import/build_smartdesign/$sdBuildScript +print_message "$sdName Built." + +# Optimizations - add constraints, modify package files if needed +print_message "Applying Design Optimizations and Constraints..." +source $scriptDir/import/design_optimization.tcl +print_message "Optimization and Constraints Applied." + +# Configure 'Place & Route' tool pre_configure_place_and_route -if {"$design_flow_stage" == "SYNTHESIZE"} then { - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Synthesis... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Synthesize' from the design flow +if {"$designFlow" == "SYNTHESIZE"} then { + print_message "Starting Synthesis..." run_tool -name {SYNTHESIZE} save_project + print_message "Synthesis Complete." - puts "\n------------------------------------------------------------------------------- \ - \r\nSynthesis Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Place and Route... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Place & Route' from the design flow +} elseif {"$designFlow" == "PLACE_AND_ROUTE"} then { + print_message "Starting Place and Route..." run_verify_timing save_project + print_message "Place and Route Completed successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nPlace and Route Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nGenerating Bitstream... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Generate Bitstream' from the design flow +} elseif {"$designFlow" == "GENERATE_BITSTREAM"} then { + print_message "Generating Bitstream..." run_verify_timing run_tool -name {GENERATEPROGRAMMINGDATA} run_tool -name {GENERATEPROGRAMMINGFILE} save_project + print_message "Bitstream Generated successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nBitstream Generated. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nExporting Programming Files... \ - \r\n-------------------------------------------------------------------------------" +# Run 'Export Programming Job File' from the design flow (into default location) +} elseif {"$designFlow" == "EXPORT_PROGRAMMING_FILE"} then { + print_message "Exporting Programming Files..." run_verify_timing + run_tool -name {GENERATEPROGRAMMINGFILE} - export_prog_job \ - -job_file_name $project_name \ - -export_dir $project_dir/designer/BaseDesign/export \ + -job_file_name $projectName \ + -export_dir $projectDir/designer/$sdName/export \ -force_rtg4_otp 0 \ -design_bitstream_format {PPD} save_project - - puts "\n------------------------------------------------------------------------------- \ - \r\nProgramming Files Exported. \ - \r\n-------------------------------------------------------------------------------" + print_message "Programming Files Exported." } else { - puts "Info: No design flow tool run." + print_message "Info: No design flow tool run." } -legacy_core_msg +# Done \ No newline at end of file diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl index 2e55517..fd808d2 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl @@ -1,278 +1,137 @@ +# Parse user arguments set config [string toupper [lindex $argv 0]] -set design_flow_stage [string toupper [lindex $argv 1]] -set die_variant [string toupper [lindex $argv 2]] - -set hw_platform RTG4_Dev_Kit -set soft_cpu MIV_RV32 -set sd_reference BaseDesign - -#ES device is not supported in these scripts - -# -# Procedure blocks start -proc create_new_project_label { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nCreating a new project for the 'RTG4_Dev_Kit' board. \ - \r\n-------------------------------------------------------------------------------" -} - -proc project_exists { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: A project exists for the 'RTG4_Dev_Kit' with this configuration. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_first_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 1st Argument has been entered. \ - \r\nInfo: Enter the 1st Argument responsible for type of design configuration -'CFG1..CFGn' \ - \r\nInfo: Default 'CFG1' design has been selected. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_first_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 1st Argument has been entered. No valid configuration detected. \ - \r\nInfo: Make sure you enter a valid first argument -'CFG1..CFGn'. \ - \r\n-------------------------------------------------------------------------------" -} - -proc no_second_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 2nd Argument has been entered. \ - \r\nInfo: Enter the 2nd Argument after the 1st to be taken further in the Design Flow. \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_second_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 2nd Argument has been entered. \ - \r\nInfo: Make sure you enter a valid 2nd argument -'Synthesize...Export_Programming_File'.\ - \r\n-------------------------------------------------------------------------------" -} - -proc no_third_argument_entered { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: No 3rd Argument has been entered. \ - \r\nInfo: Assuming the default 'PS' die type as target \ - \r\n-------------------------------------------------------------------------------" -} - -proc invalid_third_argument { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Wrong 3rd Argument has been entered. \ - \r\nInfo: Only valid 3rd Argument is 'PS' or ''. \ - \r\n-------------------------------------------------------------------------------" -} - -proc base_design_built { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nInfo: BaseDesign built. \ - \r\n-------------------------------------------------------------------------------" -} - -proc es_device_not_supported { } { - puts "\n------------------------------------------------------------------------------- \ - \r\nError: Engineering Sample (ES) die not supported in these scripts. \ - \r\n-------------------------------------------------------------------------------" -} - -proc download_required_direct_cores { } { - download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} -} - -proc pre_configure_place_and_route { } { - configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:false} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:false} -} - -proc run_verify_timing { } { - run_tool -name {VERIFYTIMING} -} -# Procedure blocks end -# - -#Filter for argument argv0: config -if {$config == ""} then { - set config "CFG1" - no_first_argument_entered -} elseif {$config != "CFG1" - && $config != "CFG2" - && $config != "CFG3"} then { - puts "config is: $config" - invalid_first_argument - exit 1 -} else { - puts "Info: Configuration selected: $config" -} - -#Filter for argument argv1: design flow -if {$design_flow_stage == ""} then { - no_second_argument_entered -} elseif {$design_flow_stage == "SYNTHESIZE" - || $design_flow_stage == "PLACE_AND_ROUTE" - || $design_flow_stage == "GENERATE_BITSTREAM" - || $design_flow_stage == "EXPORT_PROGRAMMING_FILE"} then { - puts "Info: Design flow run tool selected: $design_flow_stage" -} elseif {$design_flow_stage == "ES" - || $design_flow_stage == "PS"} then { - set die_variant "$design_flow_stage" -} else { - invalid_second_argument - exit 1 -} - -#Filter for argument argv2: die type -if {$die_variant == ""} { - set die_variant "PS" - no_third_argument_entered -} elseif {$die_variant == "PS"} { - puts "Info: Die type selected: $die_variant" -} elseif {$die_variant == "ES"} { - es_device_not_supported - exit 1 +set designFlow [string toupper [lindex $argv 1]] +set dieType [string toupper [lindex $argv 2]] + +# Get the path of the currently executing script and set execution directory +set scriptPath [info script] +set scriptDir [file dirname $scriptPath] + +# Load the TCL file with all of the procedural blocks +source $scriptDir/import/proc_blocks.tcl + +# Set valid configurations +set hwPlatform "RTG4_DEV" +set hwFamily "RTG4" +set softCpu "MIV_RV32" +set cpuRef "MIV_RV32" +set validConfigs [list "CFG1" "CFG2" "CFG3"] +set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"] +set validDieTypes [list "PS" ""] +set sdName {BaseDesign} +set exProgramHex "miv-rv32i-systick-blinky.hex" + +# Call procedures to validate user arguments +set config [verify_config $config] +set designFlow [verify_designFlow $designFlow] +set dieType [verify_dieType $dieType] + +# Prime the TCL builder script for desired build settings +set cpuGroup [expr {$softCpu eq "MIV_RV32" ? "MIV_RV32" : "MIV_Legacy"}] +set sdBuildScript [get_config_builder $config $validConfigs $cpuGroup] +get_die_configuration $hwPlatform $dieType +print_message "Runnig script: $scriptPath \nDesign Arguments: $config $designFlow $dieType \nDesign Build Script: $sdBuildScript" + +# Configure Libero project files and directories +set projectName "${hwPlatform}[expr {$dieType eq "ES" ? "_${dieType}" : ""}]_${cpuRef}_${config}_${sdName}" ; # projectName only reflects dieType if dieType is "ES" +append projectFolderName "${softCpu}_${config}_BD" +set projectDir $scriptDir/$projectFolderName +puts "Info: projectName: $projectName" +puts "Info: projectFolderName: $projectFolderName" +puts "Info: projectDir: $projectDir" + +# Build Libero design project for selected configuration and hardware +if {[file exists $projectDir] == 1} then { + print_message "Error: A project with '$config' configuration already exists for the '$hwPlatform'." } else { - invalid_third_argument - exit 1 -} - -append target_board $hw_platform _ $die_variant -append project_folder_name MIV_ $config _BD -set project_dir "./$project_folder_name" -append project_name $target_board _ $soft_cpu _ $config _ $sd_reference - -if {"$config" == "CFG1"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" == "PS"} then { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - project_settings -enable_set_mitigation 0 - } else { - invalid_third_argument - exit 1 - } - download_required_direct_cores - source ./import/components/IMC_CFG1/import_sd_and_constraints_rtg4_imc_cfg1.tcl - save_project - base_design_built - } -} elseif {"$config" == "CFG2"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" == "PS"} then { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - project_settings -enable_set_mitigation 0 - } else { - invalid_third_argument - exit 1 - } - download_required_direct_cores - source ./import/components/IMC_CFG2/import_sd_and_constraints_rtg4_imc_cfg2.tcl - save_project - base_design_built - } -} elseif {"$config" == "CFG3"} then { - if {[file exists $project_dir] == 1} then { - project_exists - } else { - create_new_project_label - if {"$die_variant" == "PS"} then { - new_project -location $project_dir -name $project_name -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - project_settings -enable_set_mitigation 0 - } else { - invalid_third_argument - exit 1 - } - download_required_direct_cores - source ./import/components/IMC_CFG3/import_sd_and_constraints_rtg4_imc_cfg3.tcl - save_project - base_design_built - } -} else { - invalid_first_argument - exit 1 -} - + print_message "Creating a new project for the '$hwPlatform' board." + new_project \ + -location $projectDir \ + -name $projectName \ + -project_description {} \ + -block_mode 0 \ + -standalone_peripheral_initialization 0 \ + -instantiate_in_smartdesign 1 \ + -ondemand_build_dh 1 \ + -hdl {VERILOG} \ + -family {RTG4} \ + -die $diePackage \ + -package $dieSize \ + -speed $dieSpeed \ + -die_voltage {1.2} \ + -part_range $tempGrade \ + -adv_options {IO_DEFT_STD:LVCMOS 2.5V} \ + -adv_options {RESTRICTPROBEPINS:1} \ + -adv_options {RESTRICTSPIPINS:0} \ + -adv_options "TEMPR:$tempGrade" \ + -adv_options "VCCI_1.2_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_1.8_VOLTR:$tempGrade" \ + -adv_options "VCCI_2.5_VOLTR:$tempGrade" \ + -adv_options "VCCI_3.3_VOLTR:$tempGrade" \ + -adv_options "VOLTR:$tempGrade" + project_settings -enable_set_mitigation 0 +} + +# Download the required direct cores +#download_required_direct_cores "$hwPlatform" "$softCpu" "$config" + +# Copy the example software program into the project directory +# file copy -force $scriptDir/import/software_example/$cpuGroup/$config/hex $projectDir + +# Import and build the design's SmartDesign +print_message "Building the $sdName..." +source $scriptDir/import/build_smartdesign/$sdBuildScript +print_message "$sdName Built." + +# Optimizations - add constraints, modify package files if needed +print_message "Applying Design Optimizations and Constraints..." +source $scriptDir/import/design_optimization.tcl +print_message "Optimization and Constraints Applied." + +# Configure 'Place & Route' tool pre_configure_place_and_route -if {"$design_flow_stage" == "SYNTHESIZE"} then { - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Synthesis... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Synthesize' from the design flow +if {"$designFlow" == "SYNTHESIZE"} then { + print_message "Starting Synthesis..." run_tool -name {SYNTHESIZE} save_project + print_message "Synthesis Complete." - puts "\n------------------------------------------------------------------------------- \ - \r\nSynthesis Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "PLACE_AND_ROUTE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nBegin Place and Route... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Place & Route' from the design flow +} elseif {"$designFlow" == "PLACE_AND_ROUTE"} then { + print_message "Starting Place and Route..." run_verify_timing save_project + print_message "Place and Route Completed successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nPlace and Route Complete. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "GENERATE_BITSTREAM"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nGenerating Bitstream... \ - \r\n-------------------------------------------------------------------------------" - +# Run 'Generate Bitstream' from the design flow +} elseif {"$designFlow" == "GENERATE_BITSTREAM"} then { + print_message "Generating Bitstream..." run_verify_timing run_tool -name {GENERATEPROGRAMMINGDATA} run_tool -name {GENERATEPROGRAMMINGFILE} save_project + print_message "Bitstream Generated successfully." - puts "\n------------------------------------------------------------------------------- \ - \r\nBitstream Generated. \ - \r\n-------------------------------------------------------------------------------" - - -} elseif {"$design_flow_stage" == "EXPORT_PROGRAMMING_FILE"} then { - - puts "\n------------------------------------------------------------------------------- \ - \r\nExporting Programming Files... \ - \r\n-------------------------------------------------------------------------------" +# Run 'Export Programming Job File' from the design flow (into default location) +} elseif {"$designFlow" == "EXPORT_PROGRAMMING_FILE"} then { + print_message "Exporting Programming Files..." run_verify_timing - run_tool -name {GENERATEPROGRAMMINGFILE} + run_tool -name {GENERATEPROGRAMMINGFILE} export_prog_job \ - -job_file_name $project_name \ - -export_dir $project_dir/designer/BaseDesign/export \ + -job_file_name $projectName \ + -export_dir $projectDir/designer/$sdName/export \ -force_rtg4_otp 0 \ -design_bitstream_format {PPD} save_project - - puts "\n------------------------------------------------------------------------------- \ - \r\nProgramming Files Exported. \ - \r\n-------------------------------------------------------------------------------" + print_message "Programming Files Exported." } else { - puts "Info: No design flow tool run." + print_message "Info: No design flow tool run." } + +# Done diff --git a/Libero_Projects/import/build_smartdesign/MIV_Legacy_build_sd.tcl b/Libero_Projects/import/build_smartdesign/MIV_Legacy_build_sd.tcl new file mode 100644 index 0000000..0749e45 --- /dev/null +++ b/Libero_Projects/import/build_smartdesign/MIV_Legacy_build_sd.tcl @@ -0,0 +1,230 @@ +# Libero SmartDesign builder script for PolarFire family hardware platforms +# This builder is targetted at the following soft-CPU configurations: +# +# CPU: MIV_RV32IMAF_L1_AHB - CFG1 +# CPU: MIV_RV32IMA_L1_AHB - CFG1 +# CPU: RV32IMA_L1_AHB - CFG2 +# +#Libero's TCL top level script +# +#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion + +#Importing and Linking all the HDL source files used in the design +import_files -library work -hdl_source $scriptDir/import/hdl/reset_synchronizer.v +build_design_hierarchy + +#Sourcing the Tcl files for each of the design's components +set cjdRstType [expr {$softCpu eq "MIV_RV32" ? "TRSTN" : "TRST"}] + +source $scriptDir/import/components/RTG4FCCC_C0.tcl +source $scriptDir/import/components/COREAHBTOAPB3_C0.tcl +source $scriptDir/import/components/CoreUARTapb_C0.tcl +source $scriptDir/import/components/CoreAHBL_C0.tcl +source $scriptDir/import/components/CoreAPB3_C0.tcl +source $scriptDir/import/components/CoreGPIO_IN_C0.tcl +source $scriptDir/import/components/CoreGPIO_OUT_C0.tcl +source $scriptDir/import/components/CoreJTAGDebug_${cjdRstType}_C0.tcl +source $scriptDir/import/components/CoreTimer_C0.tcl +source $scriptDir/import/components/CoreTimer_C1.tcl +if {$softCpu in {"MIV_RV32IMA_L1_AXI"}} {source $scriptDir/import/components/CoreAXITOAHBL_C0.tcl + source $scriptDir/import/components/CoreAXITOAHBL_C1.tcl} +source $scriptDir/import/components/${softCpu}_C0.tcl +source $scriptDir/import/components/RTG4_SRAM_C0.tcl + +# Creating SmartDesign BaseDesign +create_smartdesign -sd_name ${sdName} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Ports +sd_create_scalar_port -sd_name ${sdName} -port_name {CLK2_PAD} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TRSTB} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TCK} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TDI} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TMS} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TDO} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {RX} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TX} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {DEVRST_N} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sdName} -port_name {SW_1} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {SW_2} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_1} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_2} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_3} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_4} -port_direction {OUT} + + +# MIV_RV32IMAx_L1_xxx (Rocketchip - Legacy) common core instance setup +sd_instantiate_component -sd_name ${sdName} -component_name "${softCpu}_C0" -instance_name "${softCpu}_C0_0" +sd_create_pin_slices -sd_name ${sdName} -pin_name "${softCpu}_C0_0:IRQ" -pin_slices {[28:0]} +sd_connect_pins_to_constant -sd_name ${sdName} -pin_names "$softCpu\_C0_0:IRQ\[28:0\]" -value {GND} +sd_create_pin_slices -sd_name ${sdName} -pin_name "${softCpu}_C0_0:IRQ" -pin_slices {[29]} +sd_create_pin_slices -sd_name ${sdName} -pin_name "${softCpu}_C0_0:IRQ" -pin_slices {[30]} +sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_C0_0:DRV_TDO" +sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_C0_0:EXT_RESETN" +if {$softCpu in {"MIV_RV32IMAF_L1_AHB" "MIV_RV32IMA_L1_AHB"}} {sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_C0_0:AHB_MST_MEM_HSEL" + sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_C0_0:AHB_MST_MMIO_HSEL"} + +# Add RTG4FCCC_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {RTG4FCCC_C0} -instance_name {RTG4FCCC_C0_0} + + +# Add SYSRESET_0 instance +sd_instantiate_macro -sd_name ${sdName} -macro_name {SYSRESET} -instance_name {SYSRESET_0} + + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sdName} -macro_name {AND2} -instance_name {AND2_0} + + +# Add reset_synchronizer_0 instance +sd_instantiate_hdl_module -sd_name ${sdName} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} + + +# Add CoreTimer_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreTimer_C0} -instance_name {CoreTimer_C0_0} + + +# Add CoreTimer_C1 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreTimer_C1} -instance_name {CoreTimer_C1_0} + + +# Add CoreJTAGDebug_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name "CoreJTAGDebug_${cjdRstType}_C0" -instance_name "CoreJTAGDebug_${cjdRstType}_C0_0" + + +# Add RTG4_SRAM_C0_0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {RTG4_SRAM_C0} -instance_name {RTG4_SRAM_C0_0} + + +# Add CoreAHBL_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreAHBL_C0} -instance_name {CoreAHBL_C0_0} +sd_connect_pins_to_constant -sd_name ${sdName} -pin_names {CoreAHBL_C0_0:REMAP_M0} -value {GND} + + +# Add COREAHBTOAPB3_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {COREAHBTOAPB3_C0} -instance_name {COREAHBTOAPB3_C0_0} + + +# Add CoreAPB3_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreAPB3_C0} -instance_name {CoreAPB3_C0_0} + + +# Add CoreGPIO_IN_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreGPIO_IN_C0} -instance_name {CoreGPIO_IN_C0_0} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreGPIO_IN_C0_0:INT} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreGPIO_IN_C0_0:GPIO_OUT} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_IN_C0_0:GPIO_IN} -pin_slices {"[0:0]"} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_IN_C0_0:GPIO_IN} -pin_slices {"[1:1]"} + + +# Add CoreGPIO_OUT_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreGPIO_OUT_C0} -instance_name {CoreGPIO_OUT_C0_0} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreGPIO_OUT_C0_0:INT} +sd_connect_pins_to_constant -sd_name ${sdName} -pin_names {CoreGPIO_OUT_C0_0:GPIO_IN} -value {GND} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_OUT_C0_0:GPIO_OUT} -pin_slices {"[0:0]"} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_OUT_C0_0:GPIO_OUT} -pin_slices {"[1:1]"} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_OUT_C0_0:GPIO_OUT} -pin_slices {"[2:2]"} +sd_create_pin_slices -sd_name ${sdName} -pin_name {CoreGPIO_OUT_C0_0:GPIO_OUT} -pin_slices {"[3:3]"} + + +# Add CoreUARTapb_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreUARTapb_C0} -instance_name {CoreUARTapb_C0_0} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreUARTapb_C0_0:TXRDY} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreUARTapb_C0_0:RXRDY} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreUARTapb_C0_0:PARITY_ERR} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreUARTapb_C0_0:OVERFLOW} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {CoreUARTapb_C0_0:FRAMING_ERR} + + +# Config specific components + +# CFG3: Add CoreAXITOAHBL_C0 instance +if {$softCpu in {"MIV_RV32IMA_L1_AXI"}} {sd_instantiate_component -sd_name ${sdName} -component_name {CoreAXITOAHBL_C0} -instance_name {CoreAXITOAHBL_C0_0} } + +# CFG3: Add CoreAXITOAHBL_C1 instance +if {$softCpu in {"MIV_RV32IMA_L1_AXI"}} {sd_instantiate_component -sd_name ${sdName} -component_name {CoreAXITOAHBL_C1} -instance_name {CoreAXITOAHBL_C1_0} } + + +# Add scalar net connections +sd_connect_pins -sd_name ${sdName} -pin_names {"CLK2_PAD" "RTG4FCCC_C0_0:CLK2_PAD"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset" "AND2_0:Y"} +sd_connect_pins -sd_name ${sdName} -pin_names {"AND2_0:B" "RTG4FCCC_C0_0:LOCK" } +sd_connect_pins -sd_name ${sdName} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 ${softCpu}_C0_0:CLK" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 reset_synchronizer_0:clock" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 CoreTimer_C0_0:PCLK" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 CoreTimer_C1_0:PCLK" +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "RTG4_SRAM_C0_0:HCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreAHBL_C0_0:HCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "COREAHBTOAPB3_C0_0:HCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreUARTapb_C0_0:PCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreGPIO_IN_C0_0:PCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreGPIO_OUT_C0_0:PCLK"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "RTG4_SRAM_C0_0:HRESETN"} +if {$softCpu in {"MIV_RV32IMA_L1_AXI"}} {sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreAXITOAHBL_C0_0:HCLK" "CoreAXITOAHBL_C0_0:ACLK"} + sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "CoreAXITOAHBL_C1_0:HCLK" "CoreAXITOAHBL_C1_0:ACLK"} + sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreAXITOAHBL_C0_0:HRESETN" "CoreAXITOAHBL_C0_0:ARESETN"} + sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreAXITOAHBL_C1_0:HRESETN" "CoreAXITOAHBL_C1_0:ARESETN"} } + +sd_connect_pins -sd_name ${sdName} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync ${softCpu}_C0_0:RESETN" +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync CoreTimer_C0_0:PRESETn" +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync CoreTimer_C1_0:PRESETn" +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreAHBL_C0_0:HRESETN"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "COREAHBTOAPB3_C0_0:HRESETN"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreUARTapb_C0_0:PRESETN"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreGPIO_IN_C0_0:PRESETN"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "CoreGPIO_OUT_C0_0:PRESETN"} + +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TCK_0 ${softCpu}_C0_0:TCK" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TDI_0 ${softCpu}_C0_0:TDI" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TDO_0 ${softCpu}_C0_0:TDO" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TMS_0 ${softCpu}_C0_0:TMS" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_${cjdRstType}_0 ${softCpu}_C0_0:${cjdRstType}" +sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:IRQ\[29\] CoreTimer_C0_0:TIMINT" +sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:IRQ\[30\] CoreTimer_C1_0:TIMINT" +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreUARTapb_C0_0:RX" "RX" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreUARTapb_C0_0:TX" "TX" } + +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TCK TCK" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TDI TDI" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TDO TDO" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TMS TMS" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TRSTB TRSTB" + +# Add bus net connections +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_IN_C0_0:GPIO_IN[0]" "SW_1" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_IN_C0_0:GPIO_IN[1]" "SW_2" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_OUT_C0_0:GPIO_OUT[0]" "LED_1" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_OUT_C0_0:GPIO_OUT[1]" "LED_2" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_OUT_C0_0:GPIO_OUT[2]" "LED_3" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreGPIO_OUT_C0_0:GPIO_OUT[3]" "LED_4" } + +# Add bus interface net connections +sd_connect_pins -sd_name ${sdName} -pin_names {"COREAHBTOAPB3_C0_0:AHBslave" "CoreAHBL_C0_0:AHBmslave7" } +sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4_SRAM_C0_0:AHBSlaveInterface" "CoreAHBL_C0_0:AHBmslave8" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APB3mmaster" "COREAHBTOAPB3_C0_0:APBmaster" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APBmslave1" "CoreUARTapb_C0_0:APB_bif" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APBmslave2" "CoreGPIO_IN_C0_0:APB_bif" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APBmslave3" "CoreTimer_C0_0:APBslave" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APBmslave4" "CoreTimer_C1_0:APBslave" } +sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAPB3_C0_0:APBmslave5" "CoreGPIO_OUT_C0_0:APB_bif" } +if {$softCpu in {"MIV_RV32IMAF_L1_AHB" "MIV_RV32IMA_L1_AHB"}} {sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:AHB_MST_MMIO CoreAHBL_C0_0:AHBmmaster0" + sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:AHB_MST_MEM CoreAHBL_C0_0:AHBmmaster1"} +if {$softCpu in {"MIV_RV32IMA_L1_AXI"}} {sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAHBL_C0_0:AHBmmaster0" "CoreAXITOAHBL_C0_0:AHBMasterIF" } + sd_connect_pins -sd_name ${sdName} -pin_names {"CoreAHBL_C0_0:AHBmmaster1" "CoreAXITOAHBL_C1_0:AHBMasterIF" } + sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:MMIO_MST_AXI CoreAXITOAHBL_C0_0:AXI_MM_IF" + sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_C0_0:MEM_MST_AXI CoreAXITOAHBL_C1_0:AXI_MM_IF"} + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sdName} +# Save the smartDesign +save_smartdesign -sd_name ${sdName} +# Generate SmartDesign BaseDesign +generate_component -component_name ${sdName} diff --git a/Libero_Projects/import/build_smartdesign/MIV_RV32_build_sd.tcl b/Libero_Projects/import/build_smartdesign/MIV_RV32_build_sd.tcl new file mode 100644 index 0000000..4382adb --- /dev/null +++ b/Libero_Projects/import/build_smartdesign/MIV_RV32_build_sd.tcl @@ -0,0 +1,171 @@ +# Libero SmartDesign builder script for PolarFire family hardware platforms +# This builder is targetted at the following soft-CPU configurations: +# +# MIV_RV32: CFG1 - AHB +# MIV_RV32: CFG2 - AXI4 +# MIV_RV32: CFG3 - TCM +# + +#Libero's TCL top level script +# +#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion + +#Importing and Linking all the HDL source files used in the design +import_files -library work -hdl_source $scriptDir/import/hdl/reset_synchronizer.v +build_design_hierarchy + +#Sourcing the Tcl files for each of the design's components +set cjdRstType [expr {$softCpu eq "MIV_RV32" ? "TRSTN" : "TRST"}] + +source $scriptDir/import/components/RTG4FCCC_C0.tcl +source $scriptDir/import/components/CoreJTAGDebug_${cjdRstType}_C0.tcl +source $scriptDir/import/components/CoreTimer_C0.tcl +source $scriptDir/import/components/CoreTimer_C1.tcl +source $scriptDir/import/components/MIV_ESS_C0.tcl +source $scriptDir/import/components/${softCpu}_${config}_C0.tcl +if {$config eq "CFG1"} {source $scriptDir/import/components/RTG4_SRAM_C0.tcl } +if {$config eq "CFG2"} {source $scriptDir/import/components/RTG4_SRAM_AXI4_C0.tcl} + +# Creating SmartDesign BaseDesign +create_smartdesign -sd_name ${sdName} + +# Disable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 0 + +# Create top level Ports +sd_create_scalar_port -sd_name ${sdName} -port_name {CLK2_PAD} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TRSTB} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TCK} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TDI} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TMS} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TDO} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {RX} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {TX} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {DEVRST_N} -port_direction {IN} + +sd_create_scalar_port -sd_name ${sdName} -port_name {SW_1} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {SW_2} -port_direction {IN} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_1} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_2} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_3} -port_direction {OUT} +sd_create_scalar_port -sd_name ${sdName} -port_name {LED_4} -port_direction {OUT} + + +# MIV_RV32 instance setup +sd_instantiate_component -sd_name ${sdName} -component_name "${softCpu}_${config}_C0" -instance_name "${softCpu}_${config}_C0_0" +sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:JTAG_TDO_DR" +sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:EXT_RESETN" +sd_mark_pins_unused -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:TIME_COUNT_OUT" + + +# Add MIV_ESS_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {MIV_ESS_C0} -instance_name {MIV_ESS_C0_0} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_IN} -pin_slices {[3:2]} +sd_connect_pins_to_constant -sd_name ${sdName} -pin_names {MIV_ESS_C0_0:GPIO_IN[3:2]} -value {GND} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_OUT} -pin_slices {[0]} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_OUT} -pin_slices {[1]} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_OUT} -pin_slices {[2]} +sd_create_pin_slices -sd_name ${sdName} -pin_name {MIV_ESS_C0_0:GPIO_OUT} -pin_slices {[3]} +sd_mark_pins_unused -sd_name ${sdName} -pin_names {MIV_ESS_C0_0:GPIO_INT} + + +# Add RTG4FCCC_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {RTG4FCCC_C0} -instance_name {RTG4FCCC_C0_0} + + +# Add SYSRESET_0 instance +sd_instantiate_macro -sd_name ${sdName} -macro_name {SYSRESET} -instance_name {SYSRESET_0} + + +# Add AND2_0 instance +sd_instantiate_macro -sd_name ${sdName} -macro_name {AND2} -instance_name {AND2_0} + + +# Add reset_synchronizer_0 instance +sd_instantiate_hdl_module -sd_name ${sdName} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} + + +# Add CoreTimer_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreTimer_C0} -instance_name {CoreTimer_C0_0} + + +# Add CoreTimer_C1 instance +sd_instantiate_component -sd_name ${sdName} -component_name {CoreTimer_C1} -instance_name {CoreTimer_C1_0} + + +# Add CoreJTAGDebug_C0 instance +sd_instantiate_component -sd_name ${sdName} -component_name "CoreJTAGDebug_${cjdRstType}_C0" -instance_name "CoreJTAGDebug_${cjdRstType}_C0_0" + + +# Config specific components + +# CFG1: Add RTG4_SRAM_C0_0 instance +if {$config eq "CFG1"} {sd_instantiate_component -sd_name ${sdName} -component_name {RTG4_SRAM_C0} -instance_name {RTG4_SRAM_C0_0} } + +# CFG2: Add RTG4_SRAM_AXI4_C0_0 instance +if {$config eq "CFG2"} {sd_instantiate_component -sd_name ${sdName} -component_name {RTG4_SRAM_AXI4_C0} -instance_name {RTG4_SRAM_AXI4_C0_0} } + + +# Add scalar net connections +sd_connect_pins -sd_name ${sdName} -pin_names {"CLK2_PAD" "RTG4FCCC_C0_0:CLK2_PAD"} +sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset" "AND2_0:Y"} +sd_connect_pins -sd_name ${sdName} -pin_names {"AND2_0:B" "RTG4FCCC_C0_0:LOCK" } +sd_connect_pins -sd_name ${sdName} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 ${softCpu}_${config}_C0_0:CLK" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 MIV_ESS_C0_0:PCLK" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 reset_synchronizer_0:clock" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 CoreTimer_C0_0:PCLK" +sd_connect_pins -sd_name ${sdName} -pin_names "RTG4FCCC_C0_0:GL0 CoreTimer_C1_0:PCLK" +if {$config eq "CFG1"} {sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "RTG4_SRAM_C0_0:HCLK"} + sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "RTG4_SRAM_C0_0:HRESETN"} } +if {$config eq "CFG2"} {sd_connect_pins -sd_name ${sdName} -pin_names {"RTG4FCCC_C0_0:GL0" "RTG4_SRAM_AXI4_C0_0:ACLK"} + sd_connect_pins -sd_name ${sdName} -pin_names {"reset_synchronizer_0:reset_sync" "RTG4_SRAM_AXI4_C0_0:ARESETN"} } + +sd_connect_pins -sd_name ${sdName} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync ${softCpu}_${config}_C0_0:RESETN" +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync MIV_ESS_C0_0:PRESETN" +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync CoreTimer_C0_0:PRESETn" +sd_connect_pins -sd_name ${sdName} -pin_names "reset_synchronizer_0:reset_sync CoreTimer_C1_0:PRESETn" + +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TCK_0 ${softCpu}_${config}_C0_0:JTAG_TCK" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TDI_0 ${softCpu}_${config}_C0_0:JTAG_TDI" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TDO_0 ${softCpu}_${config}_C0_0:JTAG_TDO" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_TMS_0 ${softCpu}_${config}_C0_0:JTAG_TMS" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TGT_${cjdRstType}_0 ${softCpu}_${config}_C0_0:JTAG_${cjdRstType}" +sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:MSYS_EI CoreTimer_C0_0:TIMINT" +sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:EXT_IRQ CoreTimer_C1_0:TIMINT" +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:UART_RX" "RX" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:UART_TX" "TX" } + +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TCK TCK" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TDI TDI" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TDO TDO" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TMS TMS" +sd_connect_pins -sd_name ${sdName} -pin_names "COREJTAGDEBUG_${cjdRstType}_C0_0:TRSTB TRSTB" + +# Add bus net connections +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_IN[0]" "SW_1" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_IN[1]" "SW_2" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_OUT[0]" "LED_1" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_OUT[1]" "LED_2" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_OUT[2]" "LED_3" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:GPIO_OUT[3]" "LED_4" } + +# Add bus interface netconnections +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:APB_3_mTARGET" "CoreTimer_C0_0:APBslave" } +sd_connect_pins -sd_name ${sdName} -pin_names {"MIV_ESS_C0_0:APB_4_mTARGET" "CoreTimer_C1_0:APBslave" } +sd_connect_pins -sd_name ${sdName} -pin_names "MIV_ESS_C0_0:APB_0_mINITIATOR ${softCpu}_${config}_C0_0:APB_INITIATOR" +if {$config eq "CFG1"} {sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:AHBL_M_TARGET RTG4_SRAM_C0_0:AHBSlaveInterface"} +if {$config eq "CFG2"} {sd_connect_pins -sd_name ${sdName} -pin_names "${softCpu}_${config}_C0_0:AXI4_M_TARGET RTG4_SRAM_AXI4_C0_0:AXI4_Slave"} + + +# Re-enable auto promotion of pins of type 'pad' +auto_promote_pad_pins -promote_all 1 +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sdName} +# Save the smartDesign +save_smartdesign -sd_name ${sdName} +# Generate SmartDesign BaseDesign +generate_component -component_name ${sdName} diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl b/Libero_Projects/import/components/COREAHBTOAPB3_C0.tcl similarity index 73% rename from Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl rename to Libero_Projects/import/components/COREAHBTOAPB3_C0.tcl index 16aa3be..a75703e 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl +++ b/Libero_Projects/import/components/COREAHBTOAPB3_C0.tcl @@ -1,4 +1,4 @@ # Exporting core COREAHBTOAPB3_0 to TCL # Exporting Create design command for core COREAHBTOAPB3_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -component_name {COREAHBTOAPB3_0} -params { } +create_and_configure_core -core_vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -download_core -component_name {COREAHBTOAPB3_C0} -params { } # Exporting core COREAHBTOAPB3_0 to TCL done diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl b/Libero_Projects/import/components/CoreAHBL_C0.tcl similarity index 97% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl rename to Libero_Projects/import/components/CoreAHBL_C0.tcl index 712d16e..8c37f33 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl +++ b/Libero_Projects/import/components/CoreAHBL_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreAHBL_0 to TCL # Exporting Create design command for core CoreAHBL_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -component_name {CoreAHBL_0} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {CoreAHBL_C0} -params {\ "HADDR_SHG_CFG:1" \ "M0_AHBSLOT0ENABLE:false" \ "M0_AHBSLOT1ENABLE:false" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl b/Libero_Projects/import/components/CoreAPB3_C0.tcl similarity index 75% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl rename to Libero_Projects/import/components/CoreAPB3_C0.tcl index 080f1da..119682f 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl +++ b/Libero_Projects/import/components/CoreAPB3_C0.tcl @@ -1,8 +1,6 @@ -# Exporting Component Description of CoreAPB3_0 to TCL -# Family: RTG4 -# Part Number: RT4G150-CG1657 -# Create and Configure the core component CoreAPB3_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -component_name {CoreAPB3_0} -params {\ +# Exporting core CoreAPB3_0 to TCL +# Exporting Create design command for core CoreAPB3_0 +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -download_core -component_name {CoreAPB3_C0} -params {\ "APB_DWIDTH:32" \ "APBSLOT0ENABLE:false" \ "APBSLOT1ENABLE:true" \ @@ -39,4 +37,5 @@ create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -compon "SC_14:false" \ "SC_15:false" \ "UPR_NIBBLE_POSN:6" } -# Exporting Component Description of CoreAPB3_0 to TCL done +# Exporting core CoreAPB3_0 to TCL done + diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl b/Libero_Projects/import/components/CoreAXITOAHBL_C0.tcl similarity index 82% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl rename to Libero_Projects/import/components/CoreAXITOAHBL_C0.tcl index c4ebe04..f4e391d 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl +++ b/Libero_Projects/import/components/CoreAXITOAHBL_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreAXITOAHBL_0 to TCL # Exporting Create design command for core CoreAXITOAHBL_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -component_name {CoreAXITOAHBL_0} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -download_core -component_name {CoreAXITOAHBL_C0} -params {\ "ASYNC_CLOCKS:false" \ "AXI_DWIDTH:64" \ "AXI_SEL_MM_S:1" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl b/Libero_Projects/import/components/CoreAXITOAHBL_C1.tcl similarity index 82% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl rename to Libero_Projects/import/components/CoreAXITOAHBL_C1.tcl index 5b315bb..8d05905 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl +++ b/Libero_Projects/import/components/CoreAXITOAHBL_C1.tcl @@ -1,6 +1,6 @@ # Exporting core CoreAXITOAHBL_1 to TCL # Exporting Create design command for core CoreAXITOAHBL_1 -create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -component_name {CoreAXITOAHBL_1} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -download_core -component_name {CoreAXITOAHBL_C1} -params {\ "ASYNC_CLOCKS:false" \ "AXI_DWIDTH:64" \ "AXI_SEL_MM_S:1" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl b/Libero_Projects/import/components/CoreGPIO_IN_C0.tcl similarity index 97% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl rename to Libero_Projects/import/components/CoreGPIO_IN_C0.tcl index a1c824d..0c6c9d5 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl +++ b/Libero_Projects/import/components/CoreGPIO_IN_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreGPIO_IN to TCL # Exporting Create design command for core CoreGPIO_IN -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_IN} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -download_core -component_name {CoreGPIO_IN_C0} -params {\ "APB_WIDTH:32" \ "FIXED_CONFIG_0:true" \ "FIXED_CONFIG_1:true" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl b/Libero_Projects/import/components/CoreGPIO_OUT_C0.tcl similarity index 97% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl rename to Libero_Projects/import/components/CoreGPIO_OUT_C0.tcl index cecf205..a882025 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl +++ b/Libero_Projects/import/components/CoreGPIO_OUT_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreGPIO_OUT to TCL # Exporting Create design command for core CoreGPIO_OUT -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -component_name {CoreGPIO_OUT} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -download_core -component_name {CoreGPIO_OUT_C0} -params {\ "APB_WIDTH:32" \ "FIXED_CONFIG_0:true" \ "FIXED_CONFIG_1:true" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl b/Libero_Projects/import/components/CoreJTAGDebug_TRSTN_C0.tcl similarity index 93% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl rename to Libero_Projects/import/components/CoreJTAGDebug_TRSTN_C0.tcl index 4cc67f3..6701fd8 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl +++ b/Libero_Projects/import/components/CoreJTAGDebug_TRSTN_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreJTAGDebug_0 to TCL # Exporting Create design command for core CoreJTAGDebug_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -component_name {CoreJTAGDebug_0} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -download_core -component_name {CoreJTAGDebug_TRSTN_C0} -params {\ "IR_CODE_TGT_0:0x55" \ "IR_CODE_TGT_1:0x56" \ "IR_CODE_TGT_2:0x57" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl b/Libero_Projects/import/components/CoreJTAGDebug_TRST_C0.tcl similarity index 93% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl rename to Libero_Projects/import/components/CoreJTAGDebug_TRST_C0.tcl index 6543672..299b22c 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl +++ b/Libero_Projects/import/components/CoreJTAGDebug_TRST_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreJTAGDebug_0 to TCL # Exporting Create design command for core CoreJTAGDebug_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -component_name {CoreJTAGDebug_1} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -download_core -component_name {CoreJTAGDebug_TRST_C0} -params {\ "IR_CODE_TGT_0:0x55" \ "IR_CODE_TGT_1:0x56" \ "IR_CODE_TGT_2:0x57" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl b/Libero_Projects/import/components/CoreTimer_C0.tcl similarity index 77% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl rename to Libero_Projects/import/components/CoreTimer_C0.tcl index fda5b3b..44f7c08 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_0.tcl +++ b/Libero_Projects/import/components/CoreTimer_C0.tcl @@ -1,6 +1,6 @@ # Exporting core CoreTimer_0 to TCL # Exporting Create design command for core CoreTimer_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_0} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -download_core -component_name {CoreTimer_C0} -params {\ "INTACTIVEH:1" \ "WIDTH:32" } # Exporting core CoreTimer_0 to TCL done diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl b/Libero_Projects/import/components/CoreTimer_C1.tcl similarity index 77% rename from Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl rename to Libero_Projects/import/components/CoreTimer_C1.tcl index 6a598ae..037e778 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreTimer_1.tcl +++ b/Libero_Projects/import/components/CoreTimer_C1.tcl @@ -1,6 +1,6 @@ # Exporting core CoreTimer_1 to TCL # Exporting Create design command for core CoreTimer_1 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -component_name {CoreTimer_1} -params {\ +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreTimer:2.0.103} -download_core -component_name {CoreTimer_C1} -params {\ "INTACTIVEH:1" \ "WIDTH:32" } # Exporting core CoreTimer_1 to TCL done diff --git a/Libero_Projects/import/components/CoreUARTapb_C0.tcl b/Libero_Projects/import/components/CoreUARTapb_C0.tcl new file mode 100644 index 0000000..bf2fe43 --- /dev/null +++ b/Libero_Projects/import/components/CoreUARTapb_C0.tcl @@ -0,0 +1,14 @@ +# Exporting core CoreUARTapb_0 to TCL +# Exporting Create design command for core CoreUARTapb_0 +create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -download_core -component_name {CoreUARTapb_C0} -params {\ +"BAUD_VAL_FRCTN:0" \ +"BAUD_VAL_FRCTN_EN:false" \ +"BAUD_VALUE:1" \ +"FIXEDMODE:0" \ +"PRG_BIT8:0" \ +"PRG_PARITY:0" \ +"RX_FIFO:0" \ +"RX_LEGACY_MODE:0" \ +"TX_FIFO:0" \ +"USE_SOFT_FIFO:0" } +# Exporting core CoreUARTapb_0 to TCL done diff --git a/Libero_Projects/import/components/IMAF_CFG1/build_sd_rtg4_imaf_cfg1.tcl b/Libero_Projects/import/components/IMAF_CFG1/build_sd_rtg4_imaf_cfg1.tcl deleted file mode 100644 index bd0d0e2..0000000 --- a/Libero_Projects/import/components/IMAF_CFG1/build_sd_rtg4_imaf_cfg1.tcl +++ /dev/null @@ -1,188 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32IMAF_L1_AHB -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl -source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - -# Add CoreAHBL_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - - -# Add COREAHBTOAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - - -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - - -# Add CoreJTAGDebug_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - -# Add MIV_RV32IMAF_L1_AHB_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMAF_L1_AHB_0} -instance_name {MIV_RV32IMAF_L1_AHB_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[28:0]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:IRQ[28:0]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[29]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[30]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:AHB_MST_MEM_HSEL} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:AHB_MST_MMIO_HSEL} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:DRV_TDO} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:EXT_RESETN} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4_SRAM_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:TCK" "CoreJTAGDebug_1:TGT_TCK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:TDI" "CoreJTAGDebug_1:TGT_TDI_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:TMS" "CoreJTAGDebug_1:TGT_TMS_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:TRST" "CoreJTAGDebug_1:TGT_TRST_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "COREAHBTOAPB3_0:HRESETN" "CoreTimer_1:PRESETn" "MIV_RV32IMAF_L1_AHB_0:RESETN" "RTG4_SRAM_0:HRESETN" "CoreGPIO_IN:PRESETN" "CoreGPIO_OUT:PRESETN" "CoreAHBL_0:HRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:IRQ[29]" "CoreTimer_0:TIMINT" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32IMAF_L1_AHB_0:IRQ[30]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:TDO" "CoreJTAGDebug_1:TGT_TDO_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "COREAHBTOAPB3_0:HCLK" "RTG4FCCC_0:GL0" "CoreTimer_1:PCLK" "MIV_RV32IMAF_L1_AHB_0:CLK" "RTG4_SRAM_0:HCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_IN:PCLK" "CoreGPIO_OUT:PCLK" "CoreAHBL_0:HCLK" "CoreTimer_0:PCLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"TCK" "CoreJTAGDebug_1:TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"TRSTB" "CoreJTAGDebug_1:TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:AHBslave" "CoreAHBL_0:AHBmslave7" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "CoreAHBL_0:AHBmslave8" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMAF_L1_AHB_0:AHB_MST_MEM" "CoreAHBL_0:AHBmmaster1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster0" "MIV_RV32IMAF_L1_AHB_0:AHB_MST_MMIO" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} diff --git a/Libero_Projects/import/components/IMAF_CFG1/import_sd_and_constraints_rtg4_imaf_cfg1.tcl b/Libero_Projects/import/components/IMAF_CFG1/import_sd_and_constraints_rtg4_imaf_cfg1.tcl deleted file mode 100644 index 0a66d36..0000000 --- a/Libero_Projects/import/components/IMAF_CFG1/import_sd_and_constraints_rtg4_imaf_cfg1.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMAF_CFG1/build_sd_rtg4_imaf_cfg1.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/IMA_CFG1/build_sd_rtg4_ima_cfg1.tcl b/Libero_Projects/import/components/IMA_CFG1/build_sd_rtg4_ima_cfg1.tcl deleted file mode 100644 index 588c81a..0000000 --- a/Libero_Projects/import/components/IMA_CFG1/build_sd_rtg4_ima_cfg1.tcl +++ /dev/null @@ -1,189 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32IMA_L1_AHB -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl -source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AHB_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - - -# Add CoreAHBL_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - - -# Add COREAHBTOAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - - -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - - -# Add CoreJTAGDebug_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - -# Add MIV_RV32IMA_L1_AHB_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMA_L1_AHB_0} -instance_name {MIV_RV32IMA_L1_AHB_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[28:0]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:IRQ[28:0]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[29]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[30]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:AHB_MST_MEM_HSEL} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:AHB_MST_MMIO_HSEL} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:EXT_RESETN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:DRV_TDO} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4_SRAM_AHBL_AXI_C0_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TCK" "CoreJTAGDebug_1:TGT_TCK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TDI" "CoreJTAGDebug_1:TGT_TDI_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TMS" "CoreJTAGDebug_1:TGT_TMS_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TRST" "CoreJTAGDebug_1:TGT_TRST_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32IMA_L1_AHB_0:IRQ[29]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32IMA_L1_AHB_0:IRQ[30]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TDO" "CoreJTAGDebug_1:TGT_TDO_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:PRESETN" "MIV_RV32IMA_L1_AHB_0:RESETN" "CoreAHBL_0:HRESETN" "CoreGPIO_OUT:PRESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "CoreGPIO_IN:PRESETN" "reset_synchronizer_0:reset_sync" "RTG4_SRAM_0:HRESETN" "COREAHBTOAPB3_0:HRESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:PCLK" "MIV_RV32IMA_L1_AHB_0:CLK" "CoreAHBL_0:HCLK" "CoreGPIO_OUT:PCLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "CoreGPIO_IN:PCLK" "reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "RTG4_SRAM_0:HCLK" "COREAHBTOAPB3_0:HCLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TCK" "TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:AHBslave" "CoreAHBL_0:AHBmslave7" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "CoreAHBL_0:AHBmslave8" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"COREAHBTOAPB3_0:APBmaster" "CoreAPB3_0:APB3mmaster" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:APB_bif" "CoreAPB3_0:APBmslave1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:APB_bif" "CoreAPB3_0:APBmslave2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "CoreAPB3_0:APBmslave3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "CoreAPB3_0:APBmslave4" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:APB_bif" "CoreAPB3_0:APBmslave5" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:AHB_MST_MEM" "CoreAHBL_0:AHBmmaster1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:AHB_MST_MMIO" "CoreAHBL_0:AHBmmaster0" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} - diff --git a/Libero_Projects/import/components/IMA_CFG1/import_sd_and_constraints_rtg4_ima_cfg1.tcl b/Libero_Projects/import/components/IMA_CFG1/import_sd_and_constraints_rtg4_ima_cfg1.tcl deleted file mode 100644 index 4e17df0..0000000 --- a/Libero_Projects/import/components/IMA_CFG1/import_sd_and_constraints_rtg4_ima_cfg1.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMA_CFG1/build_sd_rtg4_ima_cfg1.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/IMA_CFG2/build_sd_rtg4_ima_cfg2.tcl b/Libero_Projects/import/components/IMA_CFG2/build_sd_rtg4_ima_cfg2.tcl deleted file mode 100644 index 0042213..0000000 --- a/Libero_Projects/import/components/IMA_CFG2/build_sd_rtg4_ima_cfg2.tcl +++ /dev/null @@ -1,198 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32IMA_L1_AXI -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl -source ./import/components/SHARED_COMPONENTS/COREAHBTOAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAHBL_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAPB3_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAXITOAHBL_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreAXITOAHBL_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_IN.tcl -source ./import/components/SHARED_COMPONENTS/CoreGPIO_OUT.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AXI_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - -# Add CoreAHBL_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - - -# Add COREAHBTOAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - - -# Add CoreAPB3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - - -# Add CoreAXITOAHBL_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_0} -instance_name {CoreAXITOAHBL_0} - - -# Add CoreAXITOAHBL_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_1} -instance_name {CoreAXITOAHBL_1} - - -# Add CoreGPIO_IN instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:GPIO_OUT} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - - -# Add CoreGPIO_OUT instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:GPIO_IN} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[0:0]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[1:1]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[2:2]"} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - - -# Add CoreJTAGDebug_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - -# Add CoreUARTapb_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:RXRDY} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:PARITY_ERR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - - -# Add MIV_RV32IMA_L1_AXI_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMA_L1_AXI_0} -instance_name {MIV_RV32IMA_L1_AXI_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[28:0]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_0:IRQ[28:0]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[29]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[30]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_0:DRV_TDO} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_0:EXT_RESETN} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4_SRAM_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TCK_0" "MIV_RV32IMA_L1_AXI_0:TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TDI_0" "MIV_RV32IMA_L1_AXI_0:TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TMS_0" "MIV_RV32IMA_L1_AXI_0:TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TRST_0" "MIV_RV32IMA_L1_AXI_0:TRST" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:reset_sync" "RTG4_SRAM_0:HRESETN" "CoreTimer_1:PRESETn" "COREAHBTOAPB3_0:HRESETN" "CoreGPIO_OUT:PRESETN" "CoreAHBL_0:HRESETN" "CoreTimer_0:PRESETn" "CoreUARTapb_0:PRESETN" "CoreGPIO_IN:PRESETN" "CoreAXITOAHBL_0:HRESETN" "CoreAXITOAHBL_0:ARESETN" "MIV_RV32IMA_L1_AXI_0:RESETN" "CoreAXITOAHBL_1:ARESETN" "CoreAXITOAHBL_1:HRESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32IMA_L1_AXI_0:IRQ[29]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32IMA_L1_AXI_0:IRQ[30]" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TGT_TDO_0" "MIV_RV32IMA_L1_AXI_0:TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"reset_synchronizer_0:clock" "RTG4_SRAM_0:HCLK" "CoreTimer_1:PCLK" "COREAHBTOAPB3_0:HCLK" "CoreGPIO_OUT:PCLK" "CoreAHBL_0:HCLK" "CoreTimer_0:PCLK" "CoreUARTapb_0:PCLK" "CoreGPIO_IN:PCLK" "RTG4FCCC_0:GL0" "CoreAXITOAHBL_0:HCLK" "CoreAXITOAHBL_0:ACLK" "MIV_RV32IMA_L1_AXI_0:CLK" "CoreAXITOAHBL_1:ACLK" "CoreAXITOAHBL_1:HCLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TCK" "TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_1:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreUARTapb_0:TX" "TX" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_IN:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreGPIO_OUT:GPIO_OUT[3]" "LED_4" } - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave7" "COREAHBTOAPB3_0:AHBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmslave8" "RTG4_SRAM_0:AHBSlaveInterface" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "COREAHBTOAPB3_0:APBmaster" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave1" "CoreUARTapb_0:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave2" "CoreGPIO_IN:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave3" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave4" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APBmslave5" "CoreGPIO_OUT:APB_bif" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster0" "CoreAXITOAHBL_0:AHBMasterIF" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster1" "CoreAXITOAHBL_1:AHBMasterIF" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AXI_0:MEM_MST_AXI" "CoreAXITOAHBL_1:AXI_MM_IF" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AXI_0:MMIO_MST_AXI" "CoreAXITOAHBL_0:AXI_MM_IF" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} diff --git a/Libero_Projects/import/components/IMA_CFG2/import_sd_and_constraints_rtg4_ima_cfg2.tcl b/Libero_Projects/import/components/IMA_CFG2/import_sd_and_constraints_rtg4_ima_cfg2.tcl deleted file mode 100644 index 636afaa..0000000 --- a/Libero_Projects/import/components/IMA_CFG2/import_sd_and_constraints_rtg4_ima_cfg2.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMA_CFG2/build_sd_rtg4_ima_cfg2.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/IMC_CFG1/build_sd_rtg4_imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/build_sd_rtg4_imc_cfg1.tcl deleted file mode 100644 index 03f2551..0000000 --- a/Libero_Projects/import/components/IMC_CFG1/build_sd_rtg4_imc_cfg1.tcl +++ /dev/null @@ -1,149 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32 -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG1_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - - -# Add CoreJTAGDebug_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - - -# Add MIV_RV32_CFG1_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG1_0} -instance_name {MIV_RV32_CFG1_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1_0:TIME_COUNT_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1_0:JTAG_TDO_DR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1_0:EXT_RESETN} - - -# Add MIV_ESS_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4_SRAM_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MIV_RV32_CFG1_0:JTAG_TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MIV_RV32_CFG1_0:JTAG_TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MIV_RV32_CFG1_0:JTAG_TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTN_0" "MIV_RV32_CFG1_0:JTAG_TRSTN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PRESETN" "reset_synchronizer_0:reset_sync" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "RTG4_SRAM_0:HRESETN" "MIV_RV32_CFG1_0:RESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG1_0:MSYS_EI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32_CFG1_0:EXT_IRQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG1_0:JTAG_TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PCLK" "reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "RTG4_SRAM_0:HCLK" "MIV_RV32_CFG1_0:CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } - - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_3_mTARGET" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_4_mTARGET" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG1_0:APB_MSTR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_0:AHBSlaveInterface" "MIV_RV32_CFG1_0:AHBL_M_SLV" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} - diff --git a/Libero_Projects/import/components/IMC_CFG1/import_sd_and_constraints_rtg4_imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/import_sd_and_constraints_rtg4_imc_cfg1.tcl deleted file mode 100644 index 3ceaa51..0000000 --- a/Libero_Projects/import/components/IMC_CFG1/import_sd_and_constraints_rtg4_imc_cfg1.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMC_CFG1/build_sd_rtg4_imc_cfg1.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/IMC_CFG2/build_sd_rtg4_imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/build_sd_rtg4_imc_cfg2.tcl deleted file mode 100644 index 676acca..0000000 --- a/Libero_Projects/import/components/IMC_CFG2/build_sd_rtg4_imc_cfg2.tcl +++ /dev/null @@ -1,150 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32 -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG2_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - - - -# Add CoreJTAGDebug_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - - -# Add MIV_RV32_CFG2_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG2_0} -instance_name {MIV_RV32_CFG2_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:TIME_COUNT_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:JTAG_TDO_DR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2_0:EXT_RESETN} - - -# Add MIV_ESS_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4_SRAM_AXI4_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_AXI4_0} -instance_name {RTG4_SRAM_AXI4_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TCK_0" "MIV_RV32_CFG2_0:JTAG_TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDI_0" "MIV_RV32_CFG2_0:JTAG_TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TMS_0" "MIV_RV32_CFG2_0:JTAG_TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TRSTN_0" "MIV_RV32_CFG2_0:JTAG_TRSTN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TGT_TDO_0" "MIV_RV32_CFG2_0:JTAG_TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PRESETN" "reset_synchronizer_0:reset_sync" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" "RTG4_SRAM_AXI4_0:ARESETN" "MIV_RV32_CFG2_0:RESETN" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG2_0:MSYS_EI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:TIMINT" "MIV_RV32_CFG2_0:EXT_IRQ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PCLK" "reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" "RTG4_SRAM_AXI4_0:ACLK" "MIV_RV32_CFG2_0:CLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } - - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:APBslave" "MIV_ESS_0:APB_3_mTARGET" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_1:APBslave" "MIV_ESS_0:APB_4_mTARGET" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG2_0:APB_MSTR" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_AXI4_0:AXI4_Slave" "MIV_RV32_CFG2_0:AXI4_M_SLV" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} - diff --git a/Libero_Projects/import/components/IMC_CFG2/import_sd_and_constraints_rtg4_imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/import_sd_and_constraints_rtg4_imc_cfg2.tcl deleted file mode 100644 index 3ef7492..0000000 --- a/Libero_Projects/import/components/IMC_CFG2/import_sd_and_constraints_rtg4_imc_cfg2.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMC_CFG2/build_sd_rtg4_imc_cfg2.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/IMC_CFG3/build_sd_rtg4_imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/build_sd_rtg4_imc_cfg3.tcl deleted file mode 100644 index 16e4404..0000000 --- a/Libero_Projects/import/components/IMC_CFG3/build_sd_rtg4_imc_cfg3.tcl +++ /dev/null @@ -1,144 +0,0 @@ -#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) -#MIV Cores : MIV_RV32 -# -#Libero's TCL top level script -# -#This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion - -#Importing and Linking all the HDL source files used in the design -import_files -hdl_source ./import/hdl/reset_synchronizer.v -build_design_hierarchy - -#Sourcing the Tcl files for creating individual components under the top level -source ./import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreJTAGDebug_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_0.tcl -source ./import/components/SHARED_COMPONENTS/CoreTimer_1.tcl -source ./import/components/SHARED_COMPONENTS/MIV_RV32_CFG3_0.tcl -source ./import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl - -# Creating SmartDesign BaseDesign -set sd_name {BaseDesign} -create_smartdesign -sd_name ${sd_name} - -# Disable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 0 - -# Create top level Ports -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDO} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TRSTB} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TCK} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TDI} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TMS} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {RX} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {TX} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {DEVRST_N} -port_direction {IN} - -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_1} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {PUSH_BTN_2} -port_direction {IN} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_1} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} -sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - - - -# Add CoreJTAGDebug_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - - -# Add CoreTimer_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - - -# Add CoreTimer_1 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - - -# Add MIV_RV32_CFG3_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG3_0} -instance_name {MIV_RV32_CFG3_0} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3_0:TIME_COUNT_OUT} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3_0:JTAG_TDO_DR} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3_0:EXT_RESETN} - - -# Add MIV_ESS_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_ESS_0} -instance_name {MIV_ESS_0} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_IN} -pin_slices {[3:2]} -sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_IN[3:2]} -value {GND} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[0]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[1]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[2]} -sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_ESS_0:GPIO_OUT} -pin_slices {[3]} -sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_ESS_0:GPIO_INT} - - -# Add AND2_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - - -# Add RCOSC_50MHZ_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - - -# Add reset_synchronizer_0 instance -sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - - -# Add RTG4FCCC_0 instance -sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - - -# Add SYSRESET_0 instance -sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - - -# Add scalar net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:B" "RTG4FCCC_0:LOCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:A" "SYSRESET_0:POWER_ON_RESET_N" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TCK" "CoreJTAGDebug_0:TGT_TCK_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TDI" "CoreJTAGDebug_0:TGT_TDI_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TMS" "CoreJTAGDebug_0:TGT_TMS_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TRSTN" "CoreJTAGDebug_0:TGT_TRSTN_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PRESETN" "reset_synchronizer_0:reset_sync" "MIV_RV32_CFG3_0:RESETN" "CoreTimer_0:PRESETn" "CoreTimer_1:PRESETn" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreTimer_0:TIMINT" "MIV_RV32_CFG3_0:MSYS_EI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:EXT_IRQ" "CoreTimer_1:TIMINT" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3_0:JTAG_TDO" "CoreJTAGDebug_0:TGT_TDO_0" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:PCLK" "reset_synchronizer_0:clock" "RTG4FCCC_0:GL0" "MIV_RV32_CFG3_0:CLK" "CoreTimer_0:PCLK" "CoreTimer_1:PCLK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TCK" "TCK" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDI" "TDI" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TDO" "TDO" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TMS" "TMS" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreJTAGDebug_0:TRSTB" "TRSTB" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_RX" "RX" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:UART_TX" "TX" } - - -# Add bus net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[0]" "PUSH_BTN_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_IN[1]" "PUSH_BTN_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[0]" "LED_1" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[1]" "LED_2" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[2]" "LED_3" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:GPIO_OUT[3]" "LED_4" } - - -# Add bus interface net connections -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_3_mTARGET" "CoreTimer_0:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_4_mTARGET" "CoreTimer_1:APBslave" } -sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_ESS_0:APB_0_mINITIATOR" "MIV_RV32_CFG3_0:APB_MSTR" } - -# Re-enable auto promotion of pins of type 'pad' -auto_promote_pad_pins -promote_all 1 -# Re-arrange SmartDesign layout -sd_reset_layout -sd_name ${sd_name} -# Save the SmartDesign -save_smartdesign -sd_name ${sd_name} -# Generate the SmartDesign -generate_component -component_name ${sd_name} - diff --git a/Libero_Projects/import/components/IMC_CFG3/import_sd_and_constraints_rtg4_imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/import_sd_and_constraints_rtg4_imc_cfg3.tcl deleted file mode 100644 index 768a9a8..0000000 --- a/Libero_Projects/import/components/IMC_CFG3/import_sd_and_constraints_rtg4_imc_cfg3.tcl +++ /dev/null @@ -1,42 +0,0 @@ -puts "\n------------------------------------------------------------------------------- \ - \r\nImporting Components... \ - \r\n------------------------------------------------------------------------------- \n" - -source ./import/components/IMC_CFG3/build_sd_rtg4_imc_cfg3.tcl - -puts "\n------------------------------------------------------------------------------- \ - \r\nComponents Imported. \ - \r\n------------------------------------------------------------------------------- \n" - -build_design_hierarchy -set_root BaseDesign - -puts "\n------------------------------------------------------------------------------- \ - \r\nApplying Design Constraints... \ - \r\n------------------------------------------------------------------------------- \n" - -import_files -io_pdc ./import/constraints/io/io_constraints.pdc -import_files -sdc ./import/constraints/io_jtag_constraints.sdc - -# #Associate SDC constraint file to Place and Route tool -organize_tool_files -tool {PLACEROUTE} \ - -file $project_dir/constraint/io/io_constraints.pdc \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {SYNTHESIZE} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -organize_tool_files -tool {VERIFYTIMING} \ - -file $project_dir/constraint/io_jtag_constraints.sdc \ - -module {BaseDesign::work} -input_type {constraint} - -set_root BaseDesign -run_tool -name {CONSTRAINT_MANAGEMENT} -derive_constraints_sdc - -puts "\n------------------------------------------------------------------------------- \ - \r\nDesign Constraints Applied. \ - \r\n------------------------------------------------------------------------------- \n" - diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl b/Libero_Projects/import/components/MIV_ESS_C0.tcl similarity index 98% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl rename to Libero_Projects/import/components/MIV_ESS_C0.tcl index 07267e6..93d4bc1 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_ESS_0.tcl +++ b/Libero_Projects/import/components/MIV_ESS_C0.tcl @@ -2,7 +2,7 @@ # Family: PolarFire # Part Number: MPF300TS-FCG484I # Create and Configure the core component MIV_ESS_0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -component_name {MIV_ESS_0} -download_core -params {\ +create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -component_name {MIV_ESS_C0} -download_core -params {\ "APBSLOT11ENABLE:false" \ "APBSLOT12ENABLE:false" \ "APBSLOT13ENABLE:false" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl b/Libero_Projects/import/components/MIV_RV32IMAF_L1_AHB_C0.tcl similarity index 78% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl rename to Libero_Projects/import/components/MIV_RV32IMAF_L1_AHB_C0.tcl index 378a8ad..f95dcbd 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMAF_L1_AHB_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32IMAF_L1_AHB_C0.tcl @@ -1,6 +1,6 @@ # Exporting core MIV_RV32IMAF_L1_AHB_0 to TCL # Exporting Create design command for core MIV_RV32IMAF_L1_AHB_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -component_name {MIV_RV32IMAF_L1_AHB_0} -params {\ +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -download_core -component_name {MIV_RV32IMAF_L1_AHB_C0} -params {\ "ECC_EN:false" \ "RESET_VECTOR_ADDR_0:0x0" \ "RESET_VECTOR_ADDR_1:0x8000" } diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AHB_0.tcl b/Libero_Projects/import/components/MIV_RV32IMA_L1_AHB_C0.tcl similarity index 79% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AHB_0.tcl rename to Libero_Projects/import/components/MIV_RV32IMA_L1_AHB_C0.tcl index dbe95c4..76ea5c8 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AHB_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32IMA_L1_AHB_C0.tcl @@ -1,6 +1,6 @@ # Exporting core MIV_RV32IMA_L1_AHB_0 to TCL # Exporting Create design command for core MIV_RV32IMA_L1_AHB_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -component_name {MIV_RV32IMA_L1_AHB_0} -params {\ +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -download_core -component_name {MIV_RV32IMA_L1_AHB_C0} -params {\ "ECC_EN:false" \ "EXT_HALT:false" \ "RESET_VECTOR_ADDR_0:0x0" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AXI_0.tcl b/Libero_Projects/import/components/MIV_RV32IMA_L1_AXI_C0.tcl similarity index 80% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AXI_0.tcl rename to Libero_Projects/import/components/MIV_RV32IMA_L1_AXI_C0.tcl index 613ae7e..72fd6ac 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32IMA_L1_AXI_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32IMA_L1_AXI_C0.tcl @@ -1,6 +1,6 @@ # Exporting core MIV_RV32IMA_L1_AXI_0 to TCL # Exporting Create design command for core MIV_RV32IMA_L1_AXI_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -component_name {MIV_RV32IMA_L1_AXI_0} -params {\ +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -download_core -component_name {MIV_RV32IMA_L1_AXI_C0} -params {\ "MASTER_TYPE:0" \ "MEM_WID:5" \ "MMIO_WID:5" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG1_0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl similarity index 61% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG1_0.tcl rename to Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl index 094bfd7..4a23e6c 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG1_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl @@ -1,24 +1,24 @@ -# Exporting core MIV_RV32_CFG1_0 to TCL -# Exporting Create design command for core MIV_RV32_CFG1_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG1_0} -params {\ -"AHB_END_ADDR_0:0x7fff" \ +# Exporting core MIV_RV32_CFG1_C0 to TCL +# Exporting Create design command for core MIV_RV32_CFG1_C0 +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\ +"AHB_END_ADDR_0:0xffff" \ "AHB_END_ADDR_1:0x8fff" \ -"AHB_MASTER_TYPE:1" \ -"AHB_SLAVE_MIRROR:true" \ +"AHB_INITIATOR_TYPE:1" \ "AHB_START_ADDR_0:0x0" \ "AHB_START_ADDR_1:0x8000" \ +"AHB_TARGET_MIRROR:true" \ "APB_END_ADDR_0:0xffff" \ "APB_END_ADDR_1:0x7fff" \ -"APB_MASTER_TYPE:1" \ -"APB_SLAVE_MIRROR:false" \ +"APB_INITIATOR_TYPE:1" \ "APB_START_ADDR_0:0x0" \ "APB_START_ADDR_1:0x7000" \ +"APB_TARGET_MIRROR:false" \ "AXI_END_ADDR_0:0xffff" \ "AXI_END_ADDR_1:0x6fff" \ -"AXI_MASTER_TYPE:0" \ -"AXI_SLAVE_MIRROR:false" \ +"AXI_INITIATOR_TYPE:0" \ "AXI_START_ADDR_0:0x0" \ "AXI_START_ADDR_1:0x6000" \ +"AXI_TARGET_MIRROR:false" \ "BOOTROM_DEST_ADDR_LOWER:0x0" \ "BOOTROM_DEST_ADDR_UPPER:0x4000" \ "BOOTROM_PRESENT:false" \ @@ -26,15 +26,23 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "BOOTROM_SRC_END_ADDR_UPPER:0x8000" \ "BOOTROM_SRC_START_ADDR_LOWER:0x0" \ "BOOTROM_SRC_START_ADDR_UPPER:0x8000" \ +"C_EXT:true" \ "DEBUGGER:true" \ "ECC_ENABLE:false" \ +"F_EXT:false" \ "FWD_REGS:false" \ -"GEN_DECODE_RV32:3" \ "GEN_MUL_TYPE:2" \ "GPR_REGS:false" \ +"I_REGS:false" \ +"I_TRACE:false" \ +"ICACHE_EN:false" \ "INTERNAL_MTIME:true" \ "INTERNAL_MTIME_IRQ:true" \ +"M_EXT:true" \ +"MI_I_MEM:false" \ +"MIV_HART_ID:0x0" \ "MTIME_PRESCALER:100" \ +"NO_MACC_BLK:false" \ "NUM_EXT_IRQS:1" \ "RECONFIG_BOOTROM:false" \ "RESET_VECTOR_ADDR_0:0x0" \ @@ -43,11 +51,12 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "TAS_END_ADDR_1:0x4000" \ "TAS_START_ADDR_0:0x0" \ "TAS_START_ADDR_1:0x4000" \ -"TCM_END_ADDR_0:0x3fff" \ +"TCM_END_ADDR_0:0x7fff" \ "TCM_END_ADDR_1:0x4000" \ "TCM_PRESENT:false" \ +"TCM_REGS:false" \ "TCM_START_ADDR_0:0x0" \ "TCM_START_ADDR_1:0x4000" \ "TCM_TAS_PRESENT:false" \ "VECTORED_INTERRUPTS:false" } -# Exporting core MIV_RV32_CFG1_0 to TCL done +# Exporting core MIV_RV32_CFG1_C0 to TCL done diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG2_0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl similarity index 69% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG2_0.tcl rename to Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl index cb26ab3..979cd11 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG2_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl @@ -1,24 +1,24 @@ # Exporting core MIV_RV32_CFG2_0 to TCL # Exporting Create design command for core MIV_RV32_CFG2_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG2_0} -params {\ +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\ "AHB_END_ADDR_0:0xffff" \ "AHB_END_ADDR_1:0x8fff" \ -"AHB_MASTER_TYPE:0" \ -"AHB_SLAVE_MIRROR:false" \ +"AHB_INITIATOR_TYPE:0" \ "AHB_START_ADDR_0:0x0" \ "AHB_START_ADDR_1:0x8000" \ +"AHB_TARGET_MIRROR:false" \ "APB_END_ADDR_0:0xffff" \ "APB_END_ADDR_1:0x7fff" \ -"APB_MASTER_TYPE:1" \ -"APB_SLAVE_MIRROR:false" \ +"APB_INITIATOR_TYPE:1" \ "APB_START_ADDR_0:0x0" \ "APB_START_ADDR_1:0x7000" \ -"AXI_END_ADDR_0:0x7fff" \ +"APB_TARGET_MIRROR:false" \ +"AXI_END_ADDR_0:0xffff" \ "AXI_END_ADDR_1:0x8fff" \ -"AXI_MASTER_TYPE:2" \ -"AXI_SLAVE_MIRROR:true" \ +"AXI_INITIATOR_TYPE:2" \ "AXI_START_ADDR_0:0x0" \ "AXI_START_ADDR_1:0x8000" \ +"AXI_TARGET_MIRROR:true" \ "BOOTROM_DEST_ADDR_LOWER:0x0" \ "BOOTROM_DEST_ADDR_UPPER:0x4000" \ "BOOTROM_PRESENT:false" \ @@ -26,15 +26,23 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "BOOTROM_SRC_END_ADDR_UPPER:0x8000" \ "BOOTROM_SRC_START_ADDR_LOWER:0x0" \ "BOOTROM_SRC_START_ADDR_UPPER:0x8000" \ +"C_EXT:false" \ "DEBUGGER:true" \ "ECC_ENABLE:false" \ +"F_EXT:false" \ "FWD_REGS:false" \ -"GEN_DECODE_RV32:2" \ "GEN_MUL_TYPE:0" \ "GPR_REGS:false" \ +"I_REGS:false" \ +"I_TRACE:false" \ +"ICACHE_EN:false" \ "INTERNAL_MTIME:true" \ "INTERNAL_MTIME_IRQ:true" \ +"M_EXT:true" \ +"MI_I_MEM:false" \ +"MIV_HART_ID:0x0" \ "MTIME_PRESCALER:100" \ +"NO_MACC_BLK:false" \ "NUM_EXT_IRQS:1" \ "RECONFIG_BOOTROM:false" \ "RESET_VECTOR_ADDR_0:0x0" \ @@ -43,9 +51,10 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "TAS_END_ADDR_1:0x4000" \ "TAS_START_ADDR_0:0x0" \ "TAS_START_ADDR_1:0x4000" \ -"TCM_END_ADDR_0:0x3fff" \ +"TCM_END_ADDR_0:0xffff" \ "TCM_END_ADDR_1:0x4000" \ "TCM_PRESENT:false" \ +"TCM_REGS:false" \ "TCM_START_ADDR_0:0x0" \ "TCM_START_ADDR_1:0x4000" \ "TCM_TAS_PRESENT:false" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG3_0.tcl b/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl similarity index 67% rename from Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG3_0.tcl rename to Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl index 8cf5cdc..543c8ba 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/MIV_RV32_CFG3_0.tcl +++ b/Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl @@ -1,24 +1,24 @@ # Exporting core MIV_RV32_CFG3_0 to TCL # Exporting Create design command for core MIV_RV32_CFG3_0 -create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component_name {MIV_RV32_CFG3_0} -params {\ +create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\ "AHB_END_ADDR_0:0xffff" \ "AHB_END_ADDR_1:0x8fff" \ -"AHB_MASTER_TYPE:0" \ -"AHB_SLAVE_MIRROR:false" \ +"AHB_INITIATOR_TYPE:0" \ "AHB_START_ADDR_0:0x0" \ "AHB_START_ADDR_1:0x8000" \ +"AHB_TARGET_MIRROR:false" \ "APB_END_ADDR_0:0xffff" \ "APB_END_ADDR_1:0x7fff" \ -"APB_MASTER_TYPE:1" \ -"APB_SLAVE_MIRROR:false" \ +"APB_INITIATOR_TYPE:1" \ "APB_START_ADDR_0:0x0" \ "APB_START_ADDR_1:0x7000" \ +"APB_TARGET_MIRROR:false" \ "AXI_END_ADDR_0:0xffff" \ -"AXI_END_ADDR_1:0x6fff" \ -"AXI_MASTER_TYPE:0" \ -"AXI_SLAVE_MIRROR:false" \ +"AXI_END_ADDR_1:0x8fff" \ +"AXI_INITIATOR_TYPE:0" \ "AXI_START_ADDR_0:0x0" \ -"AXI_START_ADDR_1:0x6000" \ +"AXI_START_ADDR_1:0x8000" \ +"AXI_TARGET_MIRROR:false" \ "BOOTROM_DEST_ADDR_LOWER:0x0" \ "BOOTROM_DEST_ADDR_UPPER:0x4000" \ "BOOTROM_PRESENT:false" \ @@ -26,15 +26,23 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "BOOTROM_SRC_END_ADDR_UPPER:0x8000" \ "BOOTROM_SRC_START_ADDR_LOWER:0x0" \ "BOOTROM_SRC_START_ADDR_UPPER:0x8000" \ +"C_EXT:false" \ "DEBUGGER:true" \ "ECC_ENABLE:false" \ +"F_EXT:false" \ "FWD_REGS:false" \ -"GEN_DECODE_RV32:0" \ -"GEN_MUL_TYPE:2" \ +"GEN_MUL_TYPE:0" \ "GPR_REGS:false" \ +"I_REGS:false" \ +"I_TRACE:false" \ +"ICACHE_EN:false" \ "INTERNAL_MTIME:true" \ "INTERNAL_MTIME_IRQ:true" \ +"M_EXT:false" \ +"MI_I_MEM:false" \ +"MIV_HART_ID:0x0" \ "MTIME_PRESCALER:100" \ +"NO_MACC_BLK:false" \ "NUM_EXT_IRQS:1" \ "RECONFIG_BOOTROM:false" \ "RESET_VECTOR_ADDR_0:0x0" \ @@ -43,9 +51,10 @@ create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -component "TAS_END_ADDR_1:0x4000" \ "TAS_START_ADDR_0:0x0" \ "TAS_START_ADDR_1:0x4000" \ -"TCM_END_ADDR_0:0x7fff" \ +"TCM_END_ADDR_0:0xffff" \ "TCM_END_ADDR_1:0x8000" \ "TCM_PRESENT:true" \ +"TCM_REGS:false" \ "TCM_START_ADDR_0:0x0" \ "TCM_START_ADDR_1:0x8000" \ "TCM_TAS_PRESENT:false" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl b/Libero_Projects/import/components/RTG4FCCC_C0.tcl similarity index 88% rename from Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl rename to Libero_Projects/import/components/RTG4FCCC_C0.tcl index 5f99d70..5b0d901 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl +++ b/Libero_Projects/import/components/RTG4FCCC_C0.tcl @@ -1,15 +1,15 @@ -# Exporting Component Description of RTG4FCCC_0 to TCL +# Exporting Component Description of RTG4FCCC_C0 to TCL # Family: RTG4 # Part Number: RT4G150-CG1657 -# Create and Configure the core component RTG4FCCC_0 -create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -component_name {RTG4FCCC_0} -params {\ +# Create and Configure the core component RTG4FCCC_C0 +create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:2.0.204} -download_core -component_name {RTG4FCCC_C0} -params {\ "ADVANCED_TAB_CHANGED:false" \ "CLK0_IS_USED:false" \ "CLK0_PAD_IS_USED:false" \ "CLK1_IS_USED:false" \ "CLK1_PAD_IS_USED:false" \ "CLK2_IS_USED:false" \ -"CLK2_PAD_IS_USED:false" \ +"CLK2_PAD_IS_USED:true" \ "CLK3_IS_USED:false" \ "CLK3_PAD_IS_USED:false" \ "DYN_CONF_IS_USED:false" \ @@ -86,7 +86,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -c "GPD_EXPOSE_RESETS:false" \ "GPD_SYNC_STYLE:G3STYLE_AND_LOCK_RSTSYNC" \ "INCLUDE_RECONFIGURATION_LOGIC:true" \ -"INIT:088101248800020B80404040664C993186181C31C46C" \ +"INIT:088101248800020B80404040664C993186181C31C448" \ "IO_HARDWIRED_0_IS_DIFF:false" \ "IO_HARDWIRED_1_IS_DIFF:false" \ "IO_HARDWIRED_2_IS_DIFF:false" \ @@ -104,7 +104,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -c "PLL_EXT_FB_GL:EXT_FB_GL0" \ "PLL_FB_SRC:CCC_INTERNAL" \ "PLL_IN_FREQ:50.0000" \ -"PLL_IN_SRC:OSC_50MHZ" \ +"PLL_IN_SRC:IO_HARDWIRED_2" \ "PLL_IS_USED:true" \ "PLL_LOCK_IND:1024" \ "PLL_LOCK_WND:6000" \ @@ -113,7 +113,7 @@ create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -c "PLL_SSM_FREQ:40" \ "PLL_SUPPLY_VOLTAGE:25_V" \ "PLL_VCO_TARGET:700" \ -"RCOSC_25_50MHZ_IS_USED:true" \ +"RCOSC_25_50MHZ_IS_USED:false" \ "RX0_RECOVERY_BLOCK_DATA:Unused-Unused" \ "RX0_RECOVERY_BLOCK_IS_USED:false" \ "RX0_RECOVERY_BLOCK_STROBE:Unused" \ @@ -127,4 +127,4 @@ create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -c "Y1_IS_USED:false" \ "Y2_IS_USED:false" \ "Y3_IS_USED:false" } -# Exporting Component Description of RTG4FCCC_0 to TCL done +# Exporting Component Description of RTG4FCCC_C0 to TCL done diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl b/Libero_Projects/import/components/RTG4_SRAM_AXI4_C0.tcl similarity index 88% rename from Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl rename to Libero_Projects/import/components/RTG4_SRAM_AXI4_C0.tcl index aec3e13..c08b044 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl +++ b/Libero_Projects/import/components/RTG4_SRAM_AXI4_C0.tcl @@ -1,6 +1,6 @@ # Exporting core RTG4_SRAM_AXI4_0 to TCL # Create design TCL command for core RTG4_SRAM_AXI4_0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_AXI4_0} -params {\ +create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_AXI4_C0} -params {\ "AXI4_AWIDTH:32" \ "AXI4_DWIDTH:32" \ "AXI4_IDWIDTH:8" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl b/Libero_Projects/import/components/RTG4_SRAM_C0.tcl similarity index 69% rename from Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl rename to Libero_Projects/import/components/RTG4_SRAM_C0.tcl index 8f99429..44aaeb3 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl +++ b/Libero_Projects/import/components/RTG4_SRAM_C0.tcl @@ -1,6 +1,6 @@ -# Exporting core RTG4_SRAM_0 to TCL -# Create design TCL command for core RTG4_SRAM_0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_0} -params {\ +# Exporting core RTG4_SRAM_C0 to TCL +# Create design TCL command for core RTG4_SRAM_C0 +create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_C0} -params {\ "AXI4_AWIDTH:32" \ "AXI4_DWIDTH:32" \ "AXI4_IDWIDTH:8" \ @@ -22,4 +22,4 @@ create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} "USE_NATIVE_INTERFACE:F" \ "WDEPTH:32768" \ "WWIDTH:36" } -# Exporting core RTG4_SRAM_0 to TCL done +# Exporting core RTG4_SRAM_C0 to TCL done diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl deleted file mode 100644 index f0f8880..0000000 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/CoreUARTapb_0.tcl +++ /dev/null @@ -1,16 +0,0 @@ -# Exporting Component Description of CoreUARTapb_0 to TCL -# Family: RTG4 -# Part Number: RT4G150-CG1657 -# Create and Configure the core component CoreUARTapb_0 -create_and_configure_core -core_vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -component_name {CoreUARTapb_0} -params {\ -"BAUD_VAL_FRCTN:0" \ -"BAUD_VAL_FRCTN_EN:false" \ -"BAUD_VALUE:1" \ -"FIXEDMODE:0" \ -"PRG_BIT8:0" \ -"PRG_PARITY:0" \ -"RX_FIFO:0" \ -"RX_LEGACY_MODE:0" \ -"TX_FIFO:0" \ -"USE_SOFT_FIFO:0" } -# Exporting Component Description of CoreUARTapb_0 to TCL done diff --git a/Libero_Projects/import/constraints/io/io_constraints.pdc b/Libero_Projects/import/constraints/io/io_constraints.pdc index f9e6036..e371b1f 100644 --- a/Libero_Projects/import/constraints/io/io_constraints.pdc +++ b/Libero_Projects/import/constraints/io/io_constraints.pdc @@ -25,15 +25,23 @@ # User Locked I/O settings # +# -- Clock (50MHz) -- # +# MSIOD73PB1/GB12_23/CCC_NE0_CLKI2/SPWR_NE0_1_RX_STROBE_P +# Dedicated (50MHz) -- CLK2_PAD -# -- User PushButtons I/O -- # +set_io CLK2_PAD \ + -pinname AA39 \ + -fixed yes \ + -DIRECTION INPUT + +# -- User I/O -- # -set_io {PUSH_BTN_1} \ +set_io {SW_1} \ -pinname AA30 \ -fixed yes \ -DIRECTION INPUT -set_io {PUSH_BTN_2} \ +set_io {SW_2} \ -pinname AB31 \ -fixed yes \ -DIRECTION INPUT diff --git a/Libero_Projects/import/constraints/io_jtag_constraints.sdc b/Libero_Projects/import/constraints/io_jtag_constraints.sdc index b634388..521fcd0 100644 --- a/Libero_Projects/import/constraints/io_jtag_constraints.sdc +++ b/Libero_Projects/import/constraints/io_jtag_constraints.sdc @@ -4,4 +4,4 @@ create_clock -name { TCK } \ [ get_ports { TCK } ] # JTAG and Mi-V clocks are independent - adding asynchronous clock group -set_clock_groups -name {async1} -asynchronous -group [ get_clocks { RTG4FCCC_0_inst_0/RTG4FCCC_0_0/GL0} ] -group [ get_clocks { TCK } ] \ No newline at end of file +set_clock_groups -name {async1} -asynchronous -group [ get_clocks { RTG4FCCC_C0_0/RTG4FCCC_C0_0/GL0} ] -group [ get_clocks { TCK } ] \ No newline at end of file diff --git a/Libero_Projects/import/design_optimization.tcl b/Libero_Projects/import/design_optimization.tcl new file mode 100644 index 0000000..ed014b9 --- /dev/null +++ b/Libero_Projects/import/design_optimization.tcl @@ -0,0 +1,25 @@ +# Build the design hierarchy and set the root of the project +build_design_hierarchy +set_root $sdName + +# Import constraint files for all base and design guide configurations +import_files -sdc $scriptDir/import/constraints/io_jtag_constraints.sdc +import_files -io_pdc $scriptDir/import/constraints/io/io_constraints.pdc + +# Organize PDC and SDC constraints to Synthesis, Place and Route and Verify Timing tools +# CFG1, CFG2, CFG3 MIV_RV32: Base Configs +organize_tool_files -tool {PLACEROUTE} \ + -file $projectDir/constraint/io/io_constraints.pdc \ + -file $projectDir/constraint/io_jtag_constraints.sdc \ + -module ${sdName}::work -input_type {constraint} + +organize_tool_files -tool {SYNTHESIZE} \ + -file $projectDir/constraint/io_jtag_constraints.sdc \ + -module ${sdName}::work -input_type {constraint} + +organize_tool_files -tool {VERIFYTIMING} \ + -file $projectDir/constraint/io_jtag_constraints.sdc \ + -module ${sdName}::work -input_type {constraint} + +run_tool -name {CONSTRAINT_MANAGEMENT} +derive_constraints_sdc \ No newline at end of file diff --git a/Libero_Projects/import/proc_blocks.tcl b/Libero_Projects/import/proc_blocks.tcl new file mode 100644 index 0000000..6791ce7 --- /dev/null +++ b/Libero_Projects/import/proc_blocks.tcl @@ -0,0 +1,244 @@ +# +# Procedure blocks start + +proc print_message {message} { + set lines [split $message "\n"] + set maxLength 0 + foreach line $lines { + set length [string length $line] + if {$length > $maxLength} { + set maxLength $length + } + } + set stars [string repeat "*" [expr {$maxLength + 4}]] + puts "$stars" + foreach line $lines { + puts "* $line *" + } + puts "$stars" +} + +proc print_alternative_message {message} { + puts "\n-------------------------------------------------------------------------------" + puts "$message" + puts "-------------------------------------------------------------------------------" +} + + +proc safe_source {filename} { + global scriptDir + global sdBuildScript + set errmsg "" + set result [catch {source [file join $scriptDir $filename]} errmsg] + if {$result != 0} { + # Here we use the global ::errorInfo variable to get the error information + puts stderr "Error in $filename: $errmsg" + puts stderr "Stack trace: $::errorInfo" + # Re-raise the error so that the calling script knows there was a problem + return -code error $errmsg + } +} + + +# Procedure to verify the 'config' argument +proc verify_config { config } { + # Use the global variable 'validConfigs' + global validConfigs + + # If 'config' is empty, set it to a default value + if {$config eq ""} { + set config "CFG1" + puts "Info: Default 'CFG1' design has been selected." + # If 'config' is not in the list of valid values, exit the script + } elseif {[lsearch -exact $validConfigs $config] == -1} { + puts "Error: Wrong 1st Argument has been entered. No valid configuration detected." + exit 1 + } else { + puts "Info: Configuration selected: $config" + } + + return "$config" +} + +proc verify_designFlow { designFlow } { + # Use the global variable 'validDesignFlows' + global validDesignFlows + + # If 'designFlow' is "BASE" or empty, set it to a default value + if {$designFlow eq "" || $designFlow eq "BASE"} { + set designFlow "BASE" + puts "Info: No specific Design Flow selected. Default 'BASE' operation will be performed." + # If 'designFlow' is not in the list of valid values, exit the script + } elseif {[lsearch -exact $validDesignFlows $designFlow] == -1} { + puts "Error: Wrong 2nd Argument has been entered. No valid Design Flow detected." + exit 1 + } else { + puts "Info: Design flow run tool selected: $designFlow" + } + + return $designFlow +} + +# Procedure to verify the 'dieType' argument +proc verify_dieType { dieType } { + global validDieTypes + + if {![info exists dieType] || $dieType eq ""} { + set dieType "PS" + puts "Info: No die type argument has been entered. Assuming default 'PS'." + } elseif {[lsearch -exact $validDieTypes $dieType] == -1} { + puts "Error: Invalid die type argument. Please enter a valid die type." + exit 1 + } else { + puts "Info: Die type selected: $dieType" + } + + return $dieType +} + +proc get_config_builder {config validConfigs cpuGroup} { + set configMapping [dict create] + + foreach validConfig $validConfigs { + switch -exact -- $validConfig { + "CFG1" - + "CFG2" - + "CFG3" { + dict set configMapping $validConfig $cpuGroup + } + "CFG4" { + dict set configMapping $validConfig "MIV_RV32_Crypto" + } + "DGC1" - + "DGC2" - + "DGC3" - + "DGC4" { + dict set configMapping $validConfig "MIV_ESS" + } + default { + dict set configMapping $validConfig $cpuGroup + } + } + } + + set mappedValue [dict get $configMapping $config] + if {$mappedValue eq ""} { + set mappedValue $cpuGroup + } + + return "${mappedValue}_build_sd.tcl" +} + +proc get_legacy_core_name {config coreRef} { + + if { ($config eq "CFG1") && ($coreRef eq "MIV_RV32IMAF")} { + return "MIV_RV32IMAF_L1_AHB" + } elseif {($config eq "CFG1") && ($coreRef eq "MIV_RV32IMA")} { + return "MIV_RV32IMA_L1_AHB" + } elseif {($config eq "CFG2") && ($coreRef eq "MIV_RV32IMA")} { + return "MIV_RV32IMA_L1_AXI" + } +} + +proc get_die_configuration { hwPlatform dieType } { + + # Hardware Platforms (other devices require constraints to be matched) + global diePackage + global dieSize + global tempGrade + global dieSpeed + + switch $hwPlatform { + "PF_EVAL" { + set diePackage [expr {$dieType == "PS" ? "MPF300TS" : "MPF300TS_ES"}] + set dieSize "FCG1152" + set tempGrade [expr {$dieType == "PS" ? "IND" : "EXT"}] + set dieSpeed "-1" + } "PF_AVAL" { + set diePackage [expr {$dieType == "PS" ? "MPF300TS" : "MPF300TS_ES"}] + set dieSize "FCG484" + set tempGrade [expr {$dieType == "PS" ? "IND" : "EXT"}] + set dieSpeed "STD" + } "PF_EVEREST" { + set diePackage [expr {$dieType == "PS" ? "MPF300TS" : "MPF300TS_ES"}] + set dieSize "FCG1152" + set tempGrade [expr {$dieType == "PS" ? "IND" : "EXT"}] + set dieSpeed "-1" + } "PF_SPLASH" { + set diePackage [expr {$dieType == "PS" ? "MPF300TS" : "MPF300TS_ES"}] + set dieSize "FCG484" + set tempGrade [expr {$dieType == "PS" ? "IND" : "EXT"}] + set dieSpeed "-1" + } "RTG4_DEV" { + set diePackage "RT4G150" + set dieSize "1657 CG" + set tempGrade "MIL" + set dieSpeed "STD" + } default { + puts "Error: Invalid hardware platform. Please enter a valid hardware platform." + exit 1 + } + } +} + +proc download_required_direct_cores {hwPlatform softCpu config} { + download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:CORERESET_PF:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore} + if {$softCpu eq "MIV_RV32"} { + download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore} + download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore} + download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore} + } + if {$softCpu eq "MIV_RV32IMA_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} } + if {$softCpu eq "MIV_RV32IMA_L1_AXI"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} } + if {$softCpu eq "MIV_RV32IMAF_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMAF_L1_AHB:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} } + if {($hwPlatform eq "PF_Eval_Kit") && ($config eq "CFG4")} { + download_core -vlnv {Actel:SystemBuilder:PF_DDR3:2.4.122} -location {www.microchip-ip.com/repositories/SgCore} + download_core -vlnv {Actel:DirectCore:CORESPI:5.2.104} -location {www.microchip-ip.com/repositories/SgCore} + download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore} + } +} + +proc update_param {config param_to_update value_to_set} { + set config_file [open $config] + set config_file_data [read $config_file] + set config_file_lines [split $config_file_data "\n"] + close $config_file + set config_file [open $config w] + foreach line $config_file_lines { + if { [regexp $param_to_update $line] } { + puts $config_file "$param_to_update$value_to_set" + puts $line + } else { + puts $config_file "$line" + } + } + close $config_file +} + +proc configure_ram_device {scriptDir config sd_name projectDir} { + # Import RAM.cfg for design initialization memory for Hard-RAM TCM config + print_message "Generating Design Initialization Data..." + file copy -force $scriptDir/import/software_example/$config/RAM.cfg ./$projectDir/designer/$sd_name + configure_ram -cfg_file $projectDir/designer/$sd_name/RAM.cfg + generate_design_initialization_data + print_message "Design Initialization Data Generated." +} + +proc pre_configure_place_and_route { } { + # Configuring Place_and_Route tool for a timing pass. + configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:false} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} +} + +proc run_verify_timing { } { + run_tool -name {VERIFYTIMING} +} +# Procedure blocks end +# \ No newline at end of file diff --git a/README.md b/README.md index 659f873..4d0d534 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,7 @@ # RTG4 Development Kit Mi-V Sample Designs This repository contains Libero projects for the following soft core RISC-V processors: -* MIV_RV32 +* MIV_RV32 (**M**|**C**|**F**) * MIV_RV32IMA_L1_AHB * * MIV_RV32IMA_L1_AXI * * MIV_RV32IMAF_L1_AHB * @@ -20,7 +20,7 @@ To download or clone the repository: # Libero Projects -The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2022.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository. +The Libero_Projects folder contains [sample Mi-V Libero designs](Libero_Projects) for Libero SoC v2023.1. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository. ## Design Features The Libero designs include the following features: @@ -40,7 +40,7 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file # Design Tools The following design tools are required. -## Libero SoC v2022.2 +## Libero SoC v2023.1 [Libero SoC](https://www.microchip.com/en-us/products/fpgas-and-plds/fpga-and-soc-design-tools/fpga/libero-software-later-versions#downloads) is Microchip's FPGA design software. ## FlashPro Express