Skip to content

Commit

Permalink
Merge pull request #5 from seb-slowiko/v2021-3
Browse files Browse the repository at this point in the history 
Update for Libero SoC v2021.3 and DGC designs

Merging candidate for release 2021.3-v1.0
  • Loading branch information
@kevinscully100
kevinscully100 authored Mar 4, 2022
2 parents 49e2c22 + db5635e commit f91eeb9
Show file tree
Hide file tree
Showing 15 changed files with 72 additions and 149 deletions.
2 changes: 1 addition & 1 deletion FlashPro_Express_Projects/README.md
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
# RTG4 Development Kit FPGA Programming Files

This folder contains FlashPro Express v2021.2 projects for the RTG4 Development Kit Mi-V sample designs.
This folder contains FlashPro Express v2021.3 projects for the RTG4 Development Kit Mi-V sample designs.

## FlashPro Express
The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express.
Expand Down
4 changes: 2 additions & 2 deletions Libero_Projects/README.md
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
# RTG4 Development Kit Mi-V Sample FPGA Designs
This folder contains Tcl scripts that build Libero SoC v2021.2 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.
This folder contains Tcl scripts that build Libero SoC v2021.3 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000.

#### RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign

Expand All @@ -21,7 +21,7 @@ This folder contains Tcl scripts that build Libero SoC v2021.2 design projects f

| Config | Description|
| :------:|:----------------------------------------|
| CFG1 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
| CFG1 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IMC</li><li>Multiplier: MACC (Pipelined)</li><li>Interfaces: AHB Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|
| CFG2 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: IM</li><li>Multiplier: Fabric</li><li>Interfaces: AXI4 Master (mirrored), APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Disabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled* </li></ul>|
| CFG3 | This design uses the MIV_RV32 core configured as follows: <ul><li>RISC-V Extensions: I</li><li>Multiplier: none</li><li>Interfaces: APB3 Master</li><li>Internal IRQs: 6</li><li>TCM: Enabled</li><li>System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled</li><li>Debug: enabled</li></ul>|

Expand Down
11 changes: 4 additions & 7 deletions Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -60,20 +60,16 @@ proc base_design_built { }\
puts "--------------------------------------------------------------------------------------------------------- \n"
}

proc download_cores_all_cfgs { }\
proc download_required_direct_cores { }\
{
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
Expand All @@ -82,12 +78,13 @@ proc download_cores_all_cfgs { }\

proc pre_configure_place_and_route { }\
{
# Configuring Place_and_Route tool for a timing pass.
#Configuring Place_and_Route tool for a timing pass.
configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true}
}

proc run_verify_timing { }\
{
#Runs Verify Timing tool
run_tool -name {VERIFYTIMING}
}

Expand Down Expand Up @@ -118,7 +115,7 @@ if {"$config" == "CFG1"} then {
}
}

pre_configure_place_and_route
pre_configure_place_and_route

if {"$design_flow_stage" == "SYNTHESIZE"} then {
puts "\n---------------------------------------------------------------------------------------------------------"
Expand Down
15 changes: 6 additions & 9 deletions Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,20 +64,16 @@ proc base_design_built { }\
puts "--------------------------------------------------------------------------------------------------------- \n"
}

proc download_cores_all_cfgs { }\
proc download_required_direct_cores { }\
{
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
Expand All @@ -86,12 +82,13 @@ proc download_cores_all_cfgs { }\

proc pre_configure_place_and_route { }\
{
# Configuring Place_and_Route tool for a timing pass.
#Configuring Place_and_Route tool for a timing pass.
configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true}
}

proc run_verify_timing { }\
{
#Runs Verify Timing tool
run_tool -name {VERIFYTIMING}
}

Expand All @@ -101,7 +98,7 @@ if {"$config" == "CFG1"} then {
} else {
create_new_project_label
new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
save_project
base_design_built
Expand All @@ -112,7 +109,7 @@ if {"$config" == "CFG1"} then {
} else {
create_new_project_label
new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl
save_project
base_design_built
Expand All @@ -126,7 +123,7 @@ if {"$config" == "CFG1"} then {
no_first_argument_entered
create_new_project_label
new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl
save_project
base_design_built
Expand Down
16 changes: 7 additions & 9 deletions Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -77,20 +77,16 @@ proc config2_not_available { }\
}


proc download_cores_all_cfgs { }\
proc download_required_direct_cores { }\
{
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
#download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
Expand All @@ -99,11 +95,13 @@ proc download_cores_all_cfgs { }\

proc pre_configure_place_and_route { }\
{
#Configuring Place_and_Route tool for a timing pass.
configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:true} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:true}
}

proc run_verify_timing { }\
{
#Runs Verify Timing tool
run_tool -name {VERIFYTIMING}
}

Expand All @@ -114,7 +112,7 @@ if {"$config" == "CFG1"} then {
create_new_project_label
new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
project_settings -enable_set_mitigation 0
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
save_project
base_design_built
Expand All @@ -126,7 +124,7 @@ if {"$config" == "CFG1"} then {
create_new_project_label
new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
project_settings -enable_set_mitigation 0
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl
save_project
base_design_built
Expand All @@ -138,7 +136,7 @@ if {"$config" == "CFG1"} then {
create_new_project_label
new_project -location $project_dir_CFG3 -name $Libero_project_name_CFG3 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
project_settings -enable_set_mitigation 0
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl
save_project
base_design_built
Expand All @@ -153,7 +151,7 @@ if {"$config" == "CFG1"} then {
create_new_project_label
new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL}
project_settings -enable_set_mitigation 1
download_cores_all_cfgs
download_required_direct_cores
source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl
save_project
base_design_built
Expand Down
Loading

0 comments on commit f91eeb9

Please sign in to comment.