From 28d6f9cd46d7c36106c6e4a070a22face86ffddf Mon Sep 17 00:00:00 2001 From: Sebastian Slowikowski Date: Wed, 16 Feb 2022 14:50:40 +0000 Subject: [PATCH 1/4] Update for Lib. v2021.3 - Low lvl TCL and SgCore wildcards All of the SgCore components used are now downloaded using the TCL wildcards for version numbers. This should allow for easier updating procedures of the Libero Scripted Designs in the future where files would not need to be edited manually to modify component's version numbers. This technique would only work if the component's ports have not changed. A function has been added to auto-arrange the SmartDesign layout after building. Signed-off by: Sebastian Slowikowski --- .../top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl | 27 +++++------------ .../top_level_rtg4_dev_kit_rv32ima_cfg1.tcl | 29 +++++-------------- .../top_level_rtg4_dev_kit_rv32ima_cfg2.tcl | 29 +++++-------------- .../top_level_rtg4_dev_kit_rv32imc_cfg1.tcl | 26 +++++------------ .../top_level_rtg4_dev_kit_rv32imc_cfg2.tcl | 26 +++++------------ .../top_level_rtg4_dev_kit_rv32imc_cfg3.tcl | 26 ++++++----------- .../SHARED_COMPONENTS/RTG4FCCC_0.tcl | 2 +- .../SHARED_COMPONENTS/RTG4_SRAM_0.tcl | 2 +- .../SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl | 2 +- 9 files changed, 50 insertions(+), 119 deletions(-) diff --git a/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl b/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl index 2b34b87..bd0d0e2 100644 --- a/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl +++ b/Libero_Projects/import/components/IMAF_CFG1/top_level_rtg4_dev_kit_rv32imaf_cfg1.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32IMAF_L1_AHB +# #Libero's TCL top level script -# Core: MIV_RV32IMAF_L1_AHB # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -51,17 +52,14 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -insta sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - # Add COREAHBTOAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - # Add CoreAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -70,7 +68,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -81,22 +78,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -106,7 +99,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32IMAF_L1_AHB_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMAF_L1_AHB_0} -instance_name {MIV_RV32IMAF_L1_AHB_0} sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMAF_L1_AHB_0:IRQ} -pin_slices {[28:0]} @@ -119,37 +111,30 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:DRV_TD sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMAF_L1_AHB_0:EXT_RESETN} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4_SRAM_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } @@ -195,7 +180,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAHBL_0:AHBmmaster0" "MIV_RV # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} diff --git a/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl b/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl index 3e36c0e..588c81a 100644 --- a/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl +++ b/Libero_Projects/import/components/IMA_CFG1/top_level_rtg4_dev_kit_rv32ima_cfg1.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32IMA_L1_AHB +# #Libero's TCL top level script -# Core: MIV_RV32IMA_L1_AHB # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -47,23 +48,19 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OU sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} - # Add CoreAHBL_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -instance_name {CoreAHBL_0} sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - # Add COREAHBTOAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - # Add CoreAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -72,7 +69,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -83,22 +79,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -108,7 +100,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32IMA_L1_AHB_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMA_L1_AHB_0} -instance_name {MIV_RV32IMA_L1_AHB_0} sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AHB_0:IRQ} -pin_slices {[28:0]} @@ -121,37 +112,30 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:EXT_RES sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AHB_0:DRV_TDO} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4_SRAM_AHBL_AXI_C0_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"AND2_0:Y" "reset_synchronizer_0:reset" } sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:TCK" "CoreJTAGDebug_1:TGT_TCK_0" } @@ -196,7 +180,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AHB_0:AHB_MST_MM # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} + diff --git a/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl b/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl index 7c8919c..0042213 100644 --- a/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl +++ b/Libero_Projects/import/components/IMA_CFG2/top_level_rtg4_dev_kit_rv32ima_cfg2.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32IMA_L1_AXI +# #Libero's TCL top level script -# Core: MIV_RV32IMA_L1_AXI # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -53,27 +54,22 @@ sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAHBL_0} -insta sd_connect_pins_to_constant -sd_name ${sd_name} -pin_names {CoreAHBL_0:REMAP_M0} -value {GND} - # Add COREAHBTOAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {COREAHBTOAPB3_0} -instance_name {COREAHBTOAPB3_0} - # Add CoreAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreAXITOAHBL_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_0} -instance_name {CoreAXITOAHBL_0} - # Add CoreAXITOAHBL_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAXITOAHBL_1} -instance_name {CoreAXITOAHBL_1} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -82,7 +78,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -93,22 +88,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_1} -instance_name {CoreJTAGDebug_1} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -118,7 +109,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32IMA_L1_AXI_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32IMA_L1_AXI_0} -instance_name {MIV_RV32IMA_L1_AXI_0} sd_create_pin_slices -sd_name ${sd_name} -pin_name {MIV_RV32IMA_L1_AXI_0:IRQ} -pin_slices {[28:0]} @@ -129,37 +119,30 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_0:DRV_TDO sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32IMA_L1_AXI_0:EXT_RESETN} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4_SRAM_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } @@ -207,7 +190,9 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32IMA_L1_AXI_0:MMIO_MST_A # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} diff --git a/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl b/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl index 8ba87b6..fa9ce0e 100644 --- a/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl +++ b/Libero_Projects/import/components/IMC_CFG1/top_level_rtg4_dev_kit_rv32imc_cfg1.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32 +# #Libero's TCL top level script -# Core: MIV_RV32IMC # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -48,7 +49,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OU sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -57,7 +57,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -68,22 +67,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -93,7 +88,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32_CFG1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG1} -instance_name {MIV_RV32_CFG1} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1:TIME_COUNT_OUT} @@ -101,37 +95,30 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1:JTAG_TDO_DR} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG1:EXT_RESETN} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4_SRAM_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_0} -instance_name {RTG4_SRAM_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } @@ -174,7 +161,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"CoreAPB3_0:APB3mmaster" "MIV_RV # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} + diff --git a/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl b/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl index 2ff3f0f..e4dde6f 100644 --- a/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl +++ b/Libero_Projects/import/components/IMC_CFG2/top_level_rtg4_dev_kit_rv32imc_cfg2.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32 +# #Libero's TCL top level script -# Core: MIV_RV32IMC # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -48,7 +49,6 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OU sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -57,7 +57,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -68,22 +67,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -93,7 +88,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32_CFG2 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG2} -instance_name {MIV_RV32_CFG2} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2:TIME_COUNT_OUT} @@ -101,37 +95,30 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2:JTAG_TDO_DR} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG2:EXT_RESETN} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4_SRAM_AXI4_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4_SRAM_AXI4_0} -instance_name {RTG4_SRAM_AXI4_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } @@ -174,7 +161,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"RTG4_SRAM_AXI4_0:AXI4_Slave" "M # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} + diff --git a/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl b/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl index e88f50f..97546a8 100644 --- a/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl +++ b/Libero_Projects/import/components/IMC_CFG3/top_level_rtg4_dev_kit_rv32imc_cfg3.tcl @@ -1,6 +1,7 @@ -#RTG4 Dev Kit = RTG4150-1657CG +#Hardware : RTG4 Dev Kit (rev B (RTG4150-1657CG)) +#MIV Cores : MIV_RV32 +# #Libero's TCL top level script -# Core: MIV_RV32IMC # #This Tcl file sources other Tcl files to build the design(on which recursive export is run) in a bottom-up fashion @@ -43,11 +44,11 @@ sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_2} -port_direction {OU sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_3} -port_direction {OUT} sd_create_scalar_port -sd_name ${sd_name} -port_name {LED_4} -port_direction {OUT} + # Add CoreAPB3_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreAPB3_0} -instance_name {CoreAPB3_0} - # Add CoreGPIO_IN instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_IN} -instance_name {CoreGPIO_IN} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_IN:INT} @@ -56,7 +57,6 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_sl sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_IN:GPIO_IN} -pin_slices {"[1:1]"} - # Add CoreGPIO_OUT instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreGPIO_OUT} -instance_name {CoreGPIO_OUT} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreGPIO_OUT:INT} @@ -67,22 +67,18 @@ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_ sd_create_pin_slices -sd_name ${sd_name} -pin_name {CoreGPIO_OUT:GPIO_OUT} -pin_slices {"[3:3]"} - # Add CoreJTAGDebug_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreJTAGDebug_0} -instance_name {CoreJTAGDebug_0} - # Add CoreTimer_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_0} -instance_name {CoreTimer_0} - # Add CoreTimer_1 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreTimer_1} -instance_name {CoreTimer_1} - # Add CoreUARTapb_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {CoreUARTapb_0} -instance_name {CoreUARTapb_0} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:TXRDY} @@ -92,7 +88,6 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:OVERFLOW} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {CoreUARTapb_0:FRAMING_ERR} - # Add MIV_RV32_CFG3 instance sd_instantiate_component -sd_name ${sd_name} -component_name {MIV_RV32_CFG3} -instance_name {MIV_RV32_CFG3} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3:TIME_COUNT_OUT} @@ -100,32 +95,26 @@ sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3:JTAG_TDO_DR} sd_mark_pins_unused -sd_name ${sd_name} -pin_names {MIV_RV32_CFG3:EXT_RESETN} - # Add AND2_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {AND2} -instance_name {AND2_0} - # Add RCOSC_50MHZ_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {RCOSC_50MHZ} -instance_name {RCOSC_50MHZ_0} - # Add reset_synchronizer_0 instance sd_instantiate_hdl_module -sd_name ${sd_name} -hdl_module_name {reset_synchronizer} -hdl_file {hdl\reset_synchronizer.v} -instance_name {reset_synchronizer_0} - # Add RTG4FCCC_0 instance sd_instantiate_component -sd_name ${sd_name} -component_name {RTG4FCCC_0} -instance_name {RTG4FCCC_0} - # Add SYSRESET_0 instance sd_instantiate_macro -sd_name ${sd_name} -macro_name {SYSRESET} -instance_name {SYSRESET_0} - # Add scalar net connections sd_connect_pins -sd_name ${sd_name} -pin_names {"SYSRESET_0:DEVRST_N" "DEVRST_N" } sd_connect_pins -sd_name ${sd_name} -pin_names {"RCOSC_50MHZ_0:CLKOUT" "RTG4FCCC_0:RCOSC_50MHZ" } @@ -167,7 +156,10 @@ sd_connect_pins -sd_name ${sd_name} -pin_names {"MIV_RV32_CFG3:APB_MSTR" "CoreAP # Re-enable auto promotion of pins of type 'pad' auto_promote_pad_pins -promote_all 1 -# Save the smartDesign +# Re-arrange SmartDesign layout +sd_reset_layout -sd_name ${sd_name} +# Save the SmartDesign save_smartdesign -sd_name ${sd_name} -# Generate SmartDesign BaseDesign +# Generate the SmartDesign generate_component -component_name ${sd_name} + diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl index f000e0e..5f99d70 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl +++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4FCCC_0.tcl @@ -2,7 +2,7 @@ # Family: RTG4 # Part Number: RT4G150-CG1657 # Create and Configure the core component RTG4FCCC_0 -create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:2.0.201} -component_name {RTG4FCCC_0} -params {\ +create_and_configure_core -core_vlnv {Actel:SgCore:RTG4FCCC:*} -download_core -component_name {RTG4FCCC_0} -params {\ "ADVANCED_TAB_CHANGED:false" \ "CLK0_IS_USED:false" \ "CLK0_PAD_IS_USED:false" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl index 8fb0ae3..8f99429 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl +++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_0.tcl @@ -1,6 +1,6 @@ # Exporting core RTG4_SRAM_0 to TCL # Create design TCL command for core RTG4_SRAM_0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -component_name {RTG4_SRAM_0} -params {\ +create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_0} -params {\ "AXI4_AWIDTH:32" \ "AXI4_DWIDTH:32" \ "AXI4_IDWIDTH:8" \ diff --git a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl index fa7b1c3..aec3e13 100644 --- a/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl +++ b/Libero_Projects/import/components/SHARED_COMPONENTS/RTG4_SRAM_AXI4_0.tcl @@ -1,6 +1,6 @@ # Exporting core RTG4_SRAM_AXI4_0 to TCL # Create design TCL command for core RTG4_SRAM_AXI4_0 -create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -component_name {RTG4_SRAM_AXI4_0} -params {\ +create_and_configure_core -core_vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:*} -download_core -component_name {RTG4_SRAM_AXI4_0} -params {\ "AXI4_AWIDTH:32" \ "AXI4_DWIDTH:32" \ "AXI4_IDWIDTH:8" \ From 7a264385d9f9f2f8b7724fd2ffde9805e5ac8f99 Mon Sep 17 00:00:00 2001 From: Sebastian Slowikowski Date: Wed, 16 Feb 2022 14:51:40 +0000 Subject: [PATCH 2/4] Update for Lib. v2021.3 - Top TCL The function to download all latest cores has been modified to only download the required DirectCores for all of the supported configurations. Additional comments have been added and general formatting improved in all of the top lvl TCL files Signed-off by: Sebastian Slowikowski --- .../RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl | 11 ++++------- .../RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl | 15 ++++++--------- .../RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl | 8 +++----- 3 files changed, 13 insertions(+), 21 deletions(-) diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl index edeeb54..9288a1d 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMAF_BaseDesign.tcl @@ -60,20 +60,16 @@ proc base_design_built { }\ puts "--------------------------------------------------------------------------------------------------------- \n" } -proc download_cores_all_cfgs { }\ +proc download_required_direct_cores { }\ { download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - #download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} @@ -82,12 +78,13 @@ proc download_cores_all_cfgs { }\ proc pre_configure_place_and_route { }\ { - # Configuring Place_and_Route tool for a timing pass. + #Configuring Place_and_Route tool for a timing pass. configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} } proc run_verify_timing { }\ { + #Runs Verify Timing tool run_tool -name {VERIFYTIMING} } @@ -118,7 +115,7 @@ if {"$config" == "CFG1"} then { } } - pre_configure_place_and_route +pre_configure_place_and_route if {"$design_flow_stage" == "SYNTHESIZE"} then { puts "\n---------------------------------------------------------------------------------------------------------" diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl index 8239290..ec873e0 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign.tcl @@ -64,20 +64,16 @@ proc base_design_built { }\ puts "--------------------------------------------------------------------------------------------------------- \n" } -proc download_cores_all_cfgs { }\ +proc download_required_direct_cores { }\ { download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - #download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} @@ -86,12 +82,13 @@ proc download_cores_all_cfgs { }\ proc pre_configure_place_and_route { }\ { - # Configuring Place_and_Route tool for a timing pass. + #Configuring Place_and_Route tool for a timing pass. configure_tool -name {PLACEROUTE} -params {TDPR:true} -params {IOREG_COMBINING:true} -params {INCRPLACEANDROUTE:false} -params {REPAIR_MIN_DELAY:true} } proc run_verify_timing { }\ { + #Runs Verify Timing tool run_tool -name {VERIFYTIMING} } @@ -101,7 +98,7 @@ if {"$config" == "CFG1"} then { } else { create_new_project_label new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl save_project base_design_built @@ -112,7 +109,7 @@ if {"$config" == "CFG1"} then { } else { create_new_project_label new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMA_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg2.tcl save_project base_design_built @@ -126,7 +123,7 @@ if {"$config" == "CFG1"} then { no_first_argument_entered create_new_project_label new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMA_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32ima_cfg1.tcl save_project base_design_built diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl index 1096b2b..4b6e50f 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl @@ -77,20 +77,16 @@ proc config2_not_available { }\ } -proc download_cores_all_cfgs { }\ +proc download_required_direct_cores { }\ { download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.5.101} -location {www.microchip-ip.com/repositories/DirectCore} - download_core -vlnv {Actel:SystemBuilder:RTG4_SRAM_AHBL_AXI:1.0.117} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:OSC:2.0.101} -location {www.microchip-ip.com/repositories/SgCore} - download_core -vlnv {Actel:SgCore:FCCC:2.0.201} -location {www.microchip-ip.com/repositories/SgCore} download_core -vlnv {Actel:DirectCore:CoreUARTapb:5.7.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreTimer:2.0.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREJTAGDEBUG:4.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:CoreGPIO:3.2.102} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore} - #download_core -vlnv {Actel:DirectCore:COREAXI4INTERCONNECT:2.8.103} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32:3.0.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} @@ -99,11 +95,13 @@ proc download_cores_all_cfgs { }\ proc pre_configure_place_and_route { }\ { + #Configuring Place_and_Route tool for a timing pass. configure_tool -name {PLACEROUTE} -params {EFFORT_LEVEL:true} -params {REPAIR_MIN_DELAY:true} -params {TDPR:true} -params {IOREG_COMBINING:true} } proc run_verify_timing { }\ { + #Runs Verify Timing tool run_tool -name {VERIFYTIMING} } From 0074ceeb29374095e89e19838eba62d67849cd19 Mon Sep 17 00:00:00 2001 From: Sebastian Slowikowski Date: Wed, 16 Feb 2022 14:52:56 +0000 Subject: [PATCH 3/4] Update for Lib. v2021.3 - Readmes updated GitHub readmes have been updated to reflect the new version of Libero SoC v2021.3 the scripts are compatible with. Readmes still require and update to reflect information on Design Guide Configurations. Signed-off by: Sebastian Slowikowski --- FlashPro_Express_Projects/README.md | 2 +- Libero_Projects/README.md | 2 +- README.md | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/FlashPro_Express_Projects/README.md b/FlashPro_Express_Projects/README.md index 54a1052..919089a 100644 --- a/FlashPro_Express_Projects/README.md +++ b/FlashPro_Express_Projects/README.md @@ -1,6 +1,6 @@ # RTG4 Development Kit FPGA Programming Files -This folder contains FlashPro Express v2021.2 projects for the RTG4 Development Kit Mi-V sample designs. +This folder contains FlashPro Express v2021.3 projects for the RTG4 Development Kit Mi-V sample designs. ## FlashPro Express The programming files contained under this folder were exported from the designs in the Libero_Projects folder in this repository. Select the desired programming file (.job) and program your device using FlashPro Express. diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md index 8c8e85a..1080d94 100644 --- a/Libero_Projects/README.md +++ b/Libero_Projects/README.md @@ -1,5 +1,5 @@ # RTG4 Development Kit Mi-V Sample FPGA Designs -This folder contains Tcl scripts that build Libero SoC v2021.2 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. +This folder contains Tcl scripts that build Libero SoC v2021.3 design projects for the RTG4 Development Kit. These scripts are executed in Libero SoC to generate the sample designs. All cores boot from memory at 0x8000_0000. #### RTG4_Dev_Kit_MIV_RV32IMA_BaseDesign diff --git a/README.md b/README.md index 15f8826..47f9f71 100644 --- a/README.md +++ b/README.md @@ -20,7 +20,7 @@ To download or clone the repository: # Libero Projects -The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2021.2. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository. +The Libero_Projects folder contains sample Mi-V Libero designs for Libero SoC v2021.3. Libero projects for older Libero releases can be downloaded from their [tags](https://github.com/Mi-V-Soft-RISC-V/RTG4-Development-Kit/releases) in this repository. ## Design Features The Libero designs include the following features: @@ -40,7 +40,7 @@ The FlashPro_Express_Projects folder contains the pre-generated programming file # Design Tools The following design tools are required. -## Libero SoC v2021.2 +## Libero SoC v2021.3 [Libero SoC](https://www.microsemi.com/products/fpga-soc/design-resources/design-software/libero-soc#downloads) is Microchip's FPGA design software. ## FlashPro Express From db5635edd64886e9774b0524d2d4d9c72372dd40 Mon Sep 17 00:00:00 2001 From: Sebastian Slowikowski Date: Wed, 23 Feb 2022 11:34:03 +0000 Subject: [PATCH 4/4] Update for Lib. v2021.3 - Download cores function fix MIV_RV32 The top level TCL script RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl has had old function references to where SgCores and DirectCores were being downloaded together. The function call hasn't been changed properly across the script causing errors. This commit fixes the issue. Author: Merijn van de Water Signed-off: Sebastian Slowikowski --- Libero_Projects/README.md | 2 +- Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Libero_Projects/README.md b/Libero_Projects/README.md index 1080d94..40d4651 100644 --- a/Libero_Projects/README.md +++ b/Libero_Projects/README.md @@ -21,7 +21,7 @@ This folder contains Tcl scripts that build Libero SoC v2021.3 design projects f | Config | Description| | :------:|:----------------------------------------| -| CFG1 | This design uses the MIV_RV32 core configured as follows:
  • RISC-V Extensions: IMC
  • Multiplier: MACC (Pipelined)
  • Interfaces: AHB Master (mirrored), APB3 Master
  • Internal IRQs: 6
  • TCM: Enabled
  • System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled
  • Debug: enabled
| +| CFG1 | This design uses the MIV_RV32 core configured as follows:
  • RISC-V Extensions: IMC
  • Multiplier: MACC (Pipelined)
  • Interfaces: AHB Master (mirrored), APB3 Master
  • Internal IRQs: 6
  • TCM: Disabled
  • System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled
  • Debug: enabled
| | CFG2 | This design uses the MIV_RV32 core configured as follows:
  • RISC-V Extensions: IM
  • Multiplier: Fabric
  • Interfaces: AXI4 Master (mirrored), APB3 Master
  • Internal IRQs: 6
  • TCM: Disabled
  • System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled
  • Debug: enabled*
| | CFG3 | This design uses the MIV_RV32 core configured as follows:
  • RISC-V Extensions: I
  • Multiplier: none
  • Interfaces: APB3 Master
  • Internal IRQs: 6
  • TCM: Enabled
  • System Timer: Internal MTIME enabled, Internal MTIME IRQ enabled
  • Debug: enabled
| diff --git a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl index 4b6e50f..5a4f424 100644 --- a/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl +++ b/Libero_Projects/RTG4_Dev_Kit_MIV_RV32_BaseDesign.tcl @@ -112,7 +112,7 @@ if {"$config" == "CFG1"} then { create_new_project_label new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} project_settings -enable_set_mitigation 0 - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl save_project base_design_built @@ -124,7 +124,7 @@ if {"$config" == "CFG1"} then { create_new_project_label new_project -location $project_dir_CFG2 -name $Libero_project_name_CFG2 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} project_settings -enable_set_mitigation 0 - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMC_CFG2/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg2.tcl save_project base_design_built @@ -136,7 +136,7 @@ if {"$config" == "CFG1"} then { create_new_project_label new_project -location $project_dir_CFG3 -name $Libero_project_name_CFG3 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} project_settings -enable_set_mitigation 0 - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMC_CFG3/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg3.tcl save_project base_design_built @@ -151,7 +151,7 @@ if {"$config" == "CFG1"} then { create_new_project_label new_project -location $project_dir_CFG1 -name $Libero_project_name_CFG1 -project_description {} -block_mode 0 -standalone_peripheral_initialization 0 -instantiate_in_smartdesign 1 -ondemand_build_dh 1 -hdl {VERILOG} -family {RTG4} -die {RT4G150} -package {1657 CG} -speed {STD} -die_voltage {1.2} -part_range {MIL} -adv_options {IO_DEFT_STD:LVCMOS 2.5V} -adv_options {RESTRICTPROBEPINS:1} -adv_options {RESTRICTSPIPINS:0} -adv_options {TEMPR:MIL} -adv_options {VCCI_1.2_VOLTR:MIL} -adv_options {VCCI_1.5_VOLTR:MIL} -adv_options {VCCI_1.8_VOLTR:MIL} -adv_options {VCCI_2.5_VOLTR:MIL} -adv_options {VCCI_3.3_VOLTR:MIL} -adv_options {VOLTR:MIL} project_settings -enable_set_mitigation 1 - download_cores_all_cfgs + download_required_direct_cores source ./import/components/IMC_CFG1/import_component_and_constraints_rtg4_dev_kit_rv32imc_cfg1.tcl save_project base_design_built