diff --git a/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/applicaiton/main.c b/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/applicaiton/main.c index 3fb8d3a..e271f7b 100644 --- a/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/applicaiton/main.c +++ b/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/applicaiton/main.c @@ -19,25 +19,26 @@ #include "drivers/fpga_ip/CoreUARTapb/core_uart_apb.h" #include "drivers/fpga_ip/CoreMMC/core_mmc.h" -#define INTERRUPT_EVERY_10MS (100u) -#define SECTOR_SIZE_BYTES (512u) -#define SECTOR_SIZE_WORDS (SECTOR_SIZE_BYTES / sizeof(uint32_t)) -#define NUMBER_OF_SECTORS (1u) -#define SECTOR_1 (0x1u) -#define TIMEOUT_10_SECS (1000u) -#define INCREASE_BY_2 (8u) -#define SUCCESS (0u) -#define FAILURE (1u) - -/* Sector address within eMMC device */ -#define BLOCK_1 0x00000001u -#define NO_MULTI_BLKS 64 -#define MAX_NO_BLOCKS 15515584 /* 8meg device- can be read from the extended CSR register */ - -static uint32_t g_write_data_buffer[SECTOR_SIZE_WORDS] = {0u}; -static uint32_t g_read_data_buffer[SECTOR_SIZE_WORDS] = {0u}; +#define NUMBER_OF_SECTORS_TO_WRITE (MAX_NO_OF_BLOCKS) + +#define INTERRUPT_EVERY_10MS (100u) +#define SECTOR_SIZE_BYTES (512u) +#define SECTOR_SIZE_WORDS (SECTOR_SIZE_BYTES / sizeof(uint32_t)) +/* This value is determined by the FIFO_DEPTH CoreMMC verilog parameter*/ +#define FIFO_DEPTH_BYTES (4096u) +#define MAX_NO_OF_BLOCKS (FIFO_DEPTH_BYTES / SECTOR_SIZE_BYTES) +#define SECTOR_1 (0x1u) +#define TIMEOUT_10_SECS (1000u) +#define INCREASE_BY_2 (8u) +#define SUCCESS (0u) +#define FAILURE (1u) + +static uint32_t g_write_data_buffer[NUMBER_OF_SECTORS_TO_WRITE * SECTOR_SIZE_WORDS] = {0u}; +static uint32_t g_read_data_buffer[NUMBER_OF_SECTORS_TO_WRITE * SECTOR_SIZE_WORDS] = {0u}; static uint32_t ten_ms_sys_tick = 0; +static const uint8_t multiblock_message[] = "\r\n\nCoreMMC multi-block write and read-back test:" + "\r\nWriting and reading back "; static const uint8_t init_fail[] = "\r\neMMC device initialisation failure\r\n"; static const uint8_t read_back_success[] = "\r\nSUCCESS: Write and read data match\r\n"; static const uint8_t data_mismatch_fail[] = "\r\nFAILURE: Write and read data mismatch\r\n"; @@ -80,11 +81,11 @@ print(const uint8_t *const message) } static void -fill_buffer(uint32_t *const buffer, const uint32_t increment) +fill_buffer(uint32_t *const buffer, const uint32_t number_of_sectors, const uint32_t increment) { uint32_t value = 0u; - for (uint32_t index = 0u; index < SECTOR_SIZE_WORDS; index++) + for (uint32_t index = 0u; index < (number_of_sectors * SECTOR_SIZE_WORDS); index++) { *(buffer + index) = value; value += increment; @@ -186,8 +187,14 @@ multiblock_write_readback(mmc_instance_t *const this_mmc, volatile uint32_t *read_fifo = (uint32_t *)MMC_get_fifo_read_address((mmc_instance_t *)this_mmc); mmc_transfer_status_t mmc_command_status = MMC_TRANSFER_FAIL; + uint8_t report_blocks[25] = {0}; - print("\r\n\nCoreMMC multi-block write and read-back test:"); + sprintf(report_blocks, + "%i Bytes (%i blocks).", + (SECTOR_SIZE_BYTES * number_of_sectors), + number_of_sectors); + print(multiblock_message); + print(report_blocks); MMC_init_fifo(this_mmc); @@ -269,19 +276,19 @@ main(void) if (MMC_INIT_SUCCESS == mmc_state) { memset(g_read_data_buffer, 0x0u, sizeof(g_read_data_buffer)); - fill_buffer(g_write_data_buffer, INCREASE_BY_2); + fill_buffer(g_write_data_buffer, sector, INCREASE_BY_2); mmc_state = single_block_write_readback(&g_emmc, g_write_data_buffer, g_read_data_buffer, SECTOR_1); memset(g_read_data_buffer, 0x0u, sizeof(g_read_data_buffer)); - fill_buffer(g_write_data_buffer, INCREASE_BY_2); + fill_buffer(g_write_data_buffer, NUMBER_OF_SECTORS_TO_WRITE, INCREASE_BY_2); mmc_state = multiblock_write_readback(&g_emmc, g_write_data_buffer, g_read_data_buffer, - sector * NO_MULTI_BLKS, - NUMBER_OF_SECTORS); + SECTOR_1, + NUMBER_OF_SECTORS_TO_WRITE); } else { diff --git a/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/platform/drivers/fpga_ip/CoreMMC/core_mmc.h b/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/platform/drivers/fpga_ip/CoreMMC/core_mmc.h index 331ca5e..b0279de 100644 --- a/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/platform/drivers/fpga_ip/CoreMMC/core_mmc.h +++ b/driver-examples/CoreMMC/miv-rv32-coremmc-mmc_read_back/src/platform/drivers/fpga_ip/CoreMMC/core_mmc.h @@ -578,7 +578,7 @@ void MMC_param_config(mmc_params_t *this_mmc_params); resp_reg = MMC_init(&g_mmc0, MMC0_BASE_ADDR, &g_mmc0_param); if(MMC_INIT_SUCCESS == resp_reg) { - ... + // ... } @endcode */ @@ -605,7 +605,7 @@ mmc_transfer_status_t MMC_init(mmc_instance_t *this_mmc, addr_t base_address, @code uint8_t *pFifoData; - ... + // ... pFifoData = (uint8_t *)MMC_get_fifo_write_address(&g_emmc_1); MMC_init_fifo( &g_emmc_1); iCount= no_blocks * size_of_block; @@ -615,6 +615,7 @@ mmc_transfer_status_t MMC_init(mmc_instance_t *this_mmc, addr_t base_address, } @endcode */ + addr_t MMC_get_fifo_write_address(mmc_instance_t *this_mmc); /** @@ -636,7 +637,7 @@ addr_t MMC_get_fifo_write_address(mmc_instance_t *this_mmc); @code uint8_t *pFifoData; - ... + // ... pFifoData = (uint8_t *)MMC_get_fifo_read_address(&g_emmc_1); iCount= no_blocks *size_of_block; while(iCount--) @@ -645,6 +646,7 @@ addr_t MMC_get_fifo_write_address(mmc_instance_t *this_mmc); } @endcode */ + addr_t MMC_get_fifo_read_address(mmc_instance_t *this_mmc); /** @@ -671,12 +673,13 @@ addr_t MMC_get_fifo_read_address(mmc_instance_t *this_mmc); command. @code - ... + // ... ret_var = MMC_multi_block_write( &g_emmc_1, no_blocks, sect_addr, timeout); while(MMC_CMD_PROCESSING == MMC_status(&g_emmc_1)) { - ; // wait for MMC_multi_block_write() to finish - // Could do other stuff here + ; + // wait for MMC_multi_block_write() to finish + // Could do other stuff here } if(MMC_TRANSFER_SUCCESS != MMC_status(&g_emmc_1, )) { @@ -688,6 +691,7 @@ addr_t MMC_get_fifo_read_address(mmc_instance_t *this_mmc); } @endcode */ + mmc_transfer_status_t MMC_status(mmc_instance_t *this_mmc, uint32_t current_timeout_ticks); @@ -711,7 +715,7 @@ mmc_transfer_status_t MMC_status(mmc_instance_t *this_mmc, @code uint8_t *pFifoData; - ... + // ... pFifoData = (uint8_t *)MMC_get_fifo_write_address(&g_emmc_1); MMC_init_fifo( &g_emmc_1); // makes sure FIFO is empty before starting iCount= no_blocks *size_of_block; @@ -788,11 +792,12 @@ void MMC_init_fifo(const mmc_instance_t *this_mmc); BLOCK_1); if(MMC_TRANSFER_SUCCESS == resp_reg) { - ... + // ... } } @endcode */ + mmc_transfer_status_t MMC_single_block_write(const mmc_instance_t *this_mmc, const uint32_t *src_addr, uint32_t dst_addr); @@ -846,28 +851,28 @@ mmc_transfer_status_t MMC_single_block_write(const mmc_instance_t *this_mmc, This example shows how to initialize the device and perform a single block transfer. - @code - MMC_init_fifo(&g_emmc_1) - fill the FIFO - from g_buffer_a to FIFO - iCount= 512/4; - while(iCount--) - { - *pFifoData = p_tx_buff[iCount]; - } - ret_var = MMC_single_block_write_nb( &g_emmc_1, sect_addr, - current_timeout_ticks, timeout); - while(MMC_CMD_PROCESSING == MMC_status(&g_emmc_1,GetTickCount())) - { - ; - } - if(MMC_TRANSFER_SUCCESS != MMC_status(&g_emmc_1,GetTickCount())) - { - ..handle the error - } - else + #define MMC0_BASE_ADDR 0x30000000u + #define BLOCK_1 0x00000001u + + mmc_instance_t g_mmc0; + mmc_params_t g_mmc0_param; + + mmc_transfer_status_t resp_reg; + uint8_t data_buffer[512] = {0u}; + + MMC_param_config(&g_mmc0_param); + + // Set the MMC clock rate to 1/10 HCLK. + g_mmc0_param.clk_rate_div = 4u; + resp_reg = MMC_init(&g_mmc0, MMC0_BASE_ADDR, &g_mmc0_param); + if (MMC_INIT_SUCCESS == resp_reg) { - ..success- continue + resp_reg = MMC_single_block_write(&g_mmc0, data_buffer, BLOCK_1); + if (MMC_TRANSFER_SUCCESS == resp_reg) + { + // ... + } } @endcode */ @@ -928,33 +933,39 @@ mmc_transfer_status_t MMC_single_block_write_nb(mmc_instance_t *this_mmc, transfer. @code - ... - pFifoData = (uint32_t *)MMC_get_fifo_write_address(&g_emmc_1); - MMC_init_fifo( &g_emmc_1); -> make sure FIFO empty - - iCount= no_blocks * 512; - while(iCount--) -> fill the FIFO - from g_buffer_a to FIFO + volatile uint32_t *write_fifo = + (uint32_t*)MMC_get_fifo_write_address(&g_emmc_1); + MMC_init_fifo(&g_emmc_1); // Ensure the write FIFO is empty + + mmc_command_status = + MMC_multi_block_write((mmc_instance_t *)&g_emmc_1, + number_of_sectors, + sector_address, + get_clock_ticks(), + TIMEOUT_10_SECS); + + // Fill the write FIFO form the write buffer + for (uint32_t index = 0; index < (number_of_sectors * SECTOR_SIZE_WORDS); + index++) { - pFifoData = g_write_data_buff[iCount]; note:in this case filling in - reverse + *write_fifo = *(write_buffer + index); } - ret_var = MMC_multi_block_write( &g_emmc_1, no_blocks, sect_addr, - GetTickCount(), TEN_SEC_TIMEOUT); - while(MMC_CMD_PROCESSING == ret_var) + + while (MMC_CMD_PROCESSING == mmc_command_status) { - ret_var = MMC_status(&g_emmc_1,GetTickCount()); + mmc_command_status = MMC_status(&g_emmc_1, get_clock_ticks()); } - - if(MMC_TRANSFER_SUCCESS != MMC_status(&g_emmc_1,GetTickCount())) + if (MMC_TRANSFER_SUCCESS == mmc_command_status) { - ... handle the error + // Success, continue } else { - ... success + // Handle the error } @endcode */ + mmc_transfer_status_t MMC_multi_block_write(mmc_instance_t *this_mmc, uint16_t no_of_blks, uint32_t dst_addr, @@ -1030,7 +1041,7 @@ mmc_transfer_status_t MMC_multi_block_write(mmc_instance_t *this_mmc, rx_data_buffer); if(MMC_TRANSFER_SUCCESS == resp_reg) { - ... + // ... } } } @@ -1103,21 +1114,22 @@ mmc_transfer_status_t MMC_single_block_read(const mmc_instance_t *this_mmc, } if(MMC_TRANSFER_SUCCESS == MMC_status(&g_emmc_1,GetTickCount())) { - empty the FIFO - - pFifoData = (uint8_t *)MMC_get_fifo_read_address(&g_emmc_1); - while( size_of_transfer--) - { - g_write_data_buff[temp_compare] = *pFifoData; - } + // empty the FIFO + pFifoData = (uint8_t *)MMC_get_fifo_read_address(&g_emmc_1); + while (size_of_transfer--) + { + g_write_data_buff[temp_compare] = *pFifoData; + } } else { - - .. handle the error + // handle the error } - } end of processing- command finished + } + // end of processing - command finished @endcode */ + mmc_transfer_status_t MMC_single_block_read_nb(mmc_instance_t *this_mmc, uint32_t src_addr, uint32_t current_timeout_ticks, @@ -1200,18 +1212,19 @@ mmc_transfer_status_t MMC_single_block_read_nb(mmc_instance_t *this_mmc, } if(MMC_TRANSFER_SUCCESS == MMC_status(&g_emmc_1,GetTickCount())) { - empty the FIFO - - pFifoData = (uint8_t *)MMC_get_fifo_read_address(&g_emmc_1); - while( index < size_of_transfer) - { - p_rx_buff[index] = *pFifoData; - } + // empty the FIFO + pFifoData = (uint8_t *)MMC_get_fifo_read_address(&g_emmc_1); + while (index < size_of_transfer) + { + p_rx_buff[index] = *pFifoData; + } } else { - handle the error + // handle the error } - } end of processing- command finished + } + // end of processing - command finished @endcode */ mmc_transfer_status_t MMC_multi_block_read(mmc_instance_t *this_mmc, @@ -1246,6 +1259,7 @@ mmc_transfer_status_t MMC_multi_block_read(mmc_instance_t *this_mmc, } @endcode */ + void MMC_isr(mmc_instance_t *this_mmc); #ifdef __cplusplus