Error: OpenOCD only supports Debug Module version 2 (0.13), not 1 (dmstatus=0x1).

[JV73]

Using the Future-Avalanche-Board, I built my own RV32_IMC implementation in Libero with a small amount of TCM and minimal
peripherals. I then modified an existing miv-riscv example project for SoftConsole and tried to test the code via the 'hw_debug' launcher; but I get the following error:

Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : No Embedded FlashPro6 (revision B) devices found
Info : clock speed 6000 kHz
Info : JTAG tap: fpga.tap tap/device found: 0x2f8131cf (mfg: 0x0e7
(GateField), part: 0xf813, ver: 0x2)
Info : JTAG tap: fpga.tap disabled
Info : JTAG tap: fpga.cpu enabled
Info : RISC-V IDCODE = 0x2e50105f
Error: OpenOCD only supports Debug Module version 2 (0.13), not 1 (dmstatus=0x1). This error might be caused by a JTAG signal issue.
Try reducing the JTAG clock speed.
Info : Listening on port 3333 for gdb connections
Started by GNU MCU Eclipse
Info : accepting 'gdb' connection on tcp/3333
Error: Target not examined yet
Error executing event gdb-attach on target fpga.miv:

Error: Target not initialized. Return ERROR_FAIL.
Error: Target not initialized. Return ERROR_FAIL.

[JV73]

After a few trial/error iterations, I fell-back to the initial reference design (working) and started modifying things one at a time. Turned out that, the example designs all have a coreUARTapb connected to the serial/uart pins of the embedded Flashpro5 (FTDI chip). When that UART is present, the SoftConsole debugger works just fine; when it is removed, I get the error above.

Adding a 'dummy' output port that is 'tied-high' and placed on F17 (TX_out) solves the problem. Looking at the board schematic, it's simply a direct connection from the FPGA to the Cbus1 pin on the FTDI chip. I'm not sure why driving this pin (versus leaving it unused - which should provide a weak pull-up) affects operation of the SoftConsole debugger, but apparently, it does.

[nitindeshpande]

@jv37
Thanks for your efforts. I need to get inputs from the relevant team on this. I will get back to you once i have the information.

[nitindeshpande]

@JV73, We tried to replicate this issue on our end.
In the reference Libero design for Avalanche board we removed the CoreUARTapb connections (along with the constraints) and the SoftConsole JTAG debug still worked fine. User SoftConsole project with debug launchers provided [here]((https://github.com/Mi-V-Soft-RISC-V/miv-rv32-bare-metal-examples).

Which version of the Future-Avalanche-Board are you using?

[nitindeshpande]

Also, if you could provide us your Libero design with which you see the issue, we will try replicating the issue and debug t further. Thank you.

[JV73]

Interesting. I'll see if I can back-track and re-create the issue. Stay tuned.