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instruction_categorised_new_format.json
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{
"ARM": {
"branching": {
"B%{cond}": ["Branch %{cond}", {}, ["thumb_conditions"]],
"BL%{cond}": ["Branch with Link %{cond}", {}, []],
"BLX%{cond}": ["Branch with Link and Exchange %{cond}", {}, []],
"BX%{cond}": ["Branch and Exchange %{cond}", {}, []],
"BXJ%{cond}": ["Branch and Exchange Jazelle %{cond}", {}, []],
"CBZ": ["Compare and Branch on Zero", {}, ["thumb_only", "unconditionnal"]],
"CBNZ": ["Compare and Branch on NonZero", {}, ["thumb_only", "unconditionnal"]],
"LDC%{coproc_2}%{cond}": ["Load Coprocessor %{cond}", {}, ["coprocessor_encodings"]],
"LDR%{wtype}%{cond}": ["Load Register %{cond}", {"wtype": ["", "b", "sb", "h", "sh", "d"]}, []],
"TBB": ["Table Branch Byte", "thumb_only", ["thumb_only"]],
"TBH": ["Table Branch Halfword", "thumb_only", ["thumb_only"]],
"PLD%{cond}": ["Preload Data %{cond}", "unconditionnal", ["unconditionnal"]],
"PLDW%{cond}": ["Preload Data (Wide) %{cond}", "unconditionnal", ["unconditionnal"]],
"PLI%{cond}": ["Preload Instruction %{cond}", "unconditionnal", ["unconditionnal"]]
},
"Data processing": {
"Standard data-processing instructions": {
"ADC%{cond}": ["Add With Carry %{cond}", "flag_updater", ["flag_updater"]],
"ADD%{cond}": ["Add %{cond}", "flag_updater", ["flag_updater"]],
"ADR%{cond}": ["Add to PC %{cond}", {}, []],
"AND%{cond}": ["Bitwise AND %{cond}", "flag_updater", ["flag_updater"]],
"BIC%{cond}": ["Bitwise Bit Clear %{cond}", "flag_updater", ["flag_updater"]],
"CMN%{cond}": ["Compare Negative %{cond}", {}, []],
"CMP%{cond}": ["Compare %{cond}", {}, []],
"EOR%{cond}": ["Bitwise Exclusive OR %{cond}", "flag_updater", ["flag_updater"]],
"MOV%{cond}": ["Move %{cond}", "flag_updater", ["flag_updater"]],
"MVN%{cond}": ["Bitwise NOT %{cond}", "flag_updater", ["flag_updater"]],
"ORN%{cond}": ["Bitwise OR NOT %{cond}", "flag_updater", ["flag_updater"]],
"ORR%{cond}": ["Bitwise OR %{cond}", "flag_updater", ["flag_updater"]],
"RSB%{cond}": ["Reverse Subtract %{cond}", "flag_updater", ["flag_updater"]],
"RSC%{cond}": ["Reverse Subtract with Carry %{cond}", "flag_updater", ["flag_updater"]],
"SBC%{cond}": ["Subtract with Carry %{cond}", "flag_updater", ["flag_updater"]],
"SUB%{cond}": ["Subtract %{cond}", "flag_updater", ["flag_updater"]],
"TEQ%{cond}": ["Test Equivalence %{cond}", {}, []],
"TST%{cond}": ["Test %{cond}", {}, []]
},
"Shift instructions": {
"ASR%{cond}": ["Arithmetic Shift Right %{cond}", "flag_updater", ["flag_updater"]],
"LSL%{cond}": ["Logical Shift Left %{cond}", "flag_updater", ["flag_updater"]],
"LSR%{cond}": ["Logical Shift Right %{cond}", "flag_updater", ["flag_updater"]],
"ROR%{cond}": ["Rotate Right %{cond}", "flag_updater", ["flag_updater"]],
"RRX%{cond}": ["Rotate Right with Extend %{cond}", "flag_updater", ["flag_updater"]]
},
"Multiply instructions": {
"General": {
"MLA%{cond}": ["Multiply Accumulate %{cond}", "flag_updater", ["flag_updater"]],
"MLS%{cond}": ["Multiply and Subtract %{cond}", "flag_updater", ["flag_updater"]],
"MUL%{cond}": ["Multiply %{cond}", "flag_updater", ["flag_updater"]]
},
"Signed": {
"SMLABB%{cond}": ["Signed Multiply Accumulate (halfwords) %{cond}", "two_half_parts", ["two_half_parts"]],
"SMLAD%{cond}": ["Signed Multiply Accumulate Dual %{cond}", "cross_parts", ["cross_parts"]],
"SMLAL%{cond}": ["Signed Multiply Accumulate Long %{cond}", "flag_updater", ["flag_updater"]],
"SMLALBB%{cond}": ["Signed Multiply Accumulate Long (halfwords) %{cond}", "two_half_parts", ["two_half_parts"]],
"SMLALD%{cond}": ["Signed Multiply Accumulate Dual %{cond}", "cross_parts", ["cross_parts"]],
"SMLAWB%{cond}": ["Signed Multiply Accumulate (word by halfword) %{cond}", "last_half_part", ["last_half_part"]],
"SMLSD%{cond}": ["Signed Multiply Subtract Dual %{cond}", "cross_parts", ["cross_parts"]],
"SMLSLD%{cond}": ["Signed Multiply Subtract Long Dual %{cond}", "cross_parts", ["cross_parts"]],
"SMMLA%{cond}": ["Signed Most Significant Word Multiply Accumulate %{cond}", "rounded", ["rounded"]],
"SMMLS%{cond}": ["Signed Most Significant Word Multiply Subtract %{cond}", "rounded", ["rounded"]],
"SMMUL%{cond}": ["Signed Most Significant Word Multiply %{cond}", "rounded", ["rounded"]],
"SMUAD%{cond}": ["Signed Dual Multiply Add %{cond}", "cross_parts", ["cross_parts"]],
"SMULBB%{cond}": ["Signed Multiply (halfwords) %{cond}", "two_half_parts", ["two_half_parts"]],
"SMULL%{cond}": ["Signed Multiply Long %{cond}", "flag_updater", ["flag_updater"]],
"SMULWB%{cond}": ["Signed Multiply (word by halfword) %{cond}", "last_half_part", ["last_half_part"]],
"SMUSD%{cond}": ["Signed Multiply Subtract Dual %{cond}", "cross_parts", ["cross_parts"]]
},
"Unsigned": {
"UMAAL%{cond}": ["Unsigned Multiply Accumulate Accumulate Long %{cond}", {}, []],
"UMLAL%{cond}": ["Unsigned Multiply Accumulate Long %{cond}", "flag_updater", ["flag_updater"]],
"UMULL%{cond}": ["Unsigned Multiply Long %{cond}", "flag_updater", ["flag_updater"]]
}
},
"Saturating instructions": {
"SSAT%{cond}": ["Signed Saturate %{cond}", {}, []],
"SSAT16%{cond}": ["Signed Saturate 16 %{cond}", {}, []],
"USAT%{cond}": ["Unsigned Saturate %{cond}", {}, []],
"USAT16%{cond}": ["Unsigned Saturate 16 %{cond}", {}, []]
},
"Saturating addition and substraction instructions": {
"QADD%{cond}": ["Saturating Add %{cond}", {}, []],
"QSUB%{cond}": ["Saturating Subtract %{cond}", {}, []],
"QDADD%{cond}": ["Saturating Double and Add %{cond}", {}, []],
"QDSUB%{cond}": ["Saturating Double and Subtract %{cond}", {}, []]
},
"Packing and unpacking instructions": {
"PKH%{cond}": ["Pack Halfword %{cond}", "half_and_half", ["half_and_half"]],
"SXTAB%{cond}": ["Signed Extend and Add Byte %{cond}", {}, []],
"SXTAB16%{cond}": ["Signed Extend and Add Byte 16 %{cond}", {}, []],
"SXTAH%{cond}": ["Signed Extend and Add Halfword %{cond}", {}, []],
"SXTB%{cond}": ["Signed Extend Byte %{cond}", {}, []],
"SXTB16%{cond}": ["Signed Extend Byte 16 %{cond}", {}, []],
"SXTH%{cond}": ["Signed Extend Halfword %{cond}", {}, []],
"UXTAB%{cond}": ["Unsigned Extend and Add Byte %{cond}", {}, []],
"UXTAB16%{cond}": ["Unsigned Extend and Add Byte 16 %{cond}", {}, []],
"UXTAH%{cond}": ["Unsigned Extend and Add Halfword %{cond}", {}, []],
"UXTB%{cond}": ["Unsigned Extend Byte %{cond}", {}, []],
"UXTB16%{cond}": ["Unsigned Extend Byte 16 %{cond}", {}, []],
"UXTH%{cond}": ["Unsigned Extend Halfword %{cond}", {}, []]
},
"Parallel addition and substraction instructions": {
"SADD16%{cond}": ["Signed Add 16 %{cond}", {}, []],
"QADD16%{cond}": ["Saturating Add 16 %{cond}", {}, []],
"SHADD16%{cond}": ["Signed Halving Add 16 %{cond}", {}, []],
"UADD16%{cond}": ["Unsigned Add 16 %{cond}", {}, []],
"UQADD16%{cond}": ["Unsigned Saturating Add 16 %{cond}", {}, []],
"UHADD16%{cond}": ["Unsigned Halving Add 16 %{cond}", {}, []],
"SASX%{cond}": ["Signed Add and Subtract with Exchange %{cond}", {}, []],
"QASX%{cond}": ["Saturating Add and Subtract with Exchange %{cond}", {}, []],
"SHASX%{cond}": ["Signed Halving Add and Subtract with Exchange %{cond}", {}, []],
"UASX%{cond}": ["Unsigned Add and Subtract with Exchange %{cond}", {}, []],
"UQASX%{cond}": ["Unsigned Saturating Add and Subtract with Exchange %{cond}", {}, []],
"UHASX%{cond}": ["Unsigned Halving Add and Subtract with Exchange %{cond}", {}, []],
"SSAX%{cond}": ["Signed Subtract and Add with Exchange %{cond}", {}, []],
"QSAX%{cond}": ["Saturating Subtract and Add with Exchange %{cond}", {}, []],
"SHSAX%{cond}": ["Signed Halving Subtract and Add with Exchange %{cond}", {}, []],
"USAX%{cond}": ["Unsigned Subtract and Add with Exchange %{cond}", {}, []],
"UQSAX%{cond}": ["Unsigned Saturating Subtract and Add with Exchange %{cond}", {}, []],
"UHSAX%{cond}": ["Unsigned Halving Subtract and Add with Exchange %{cond}", {}, []],
"SSUB16%{cond}": ["Signed Subtract 16 %{cond}", {}, []],
"QSUB16%{cond}": ["Saturating Subtract 16 %{cond}", {}, []],
"SHSUB16%{cond}": ["Signed Halving Subtract 16 %{cond}", {}, []],
"USUB16%{cond}": ["Unsigned Subtract 16 %{cond}", {}, []],
"UQSUB16%{cond}": ["Unsigned Saturating Subtract 16 %{cond}", {}, []],
"UHSUB16%{cond}": ["Unsigned Halving Subtract 16 %{cond}", {}, []],
"SADD8%{cond}": ["Signed Add 8 %{cond}", {}, []],
"QADD8%{cond}": ["Saturating Add 8 %{cond}", {}, []],
"SHADD8%{cond}": ["Signed Halving Add 8 %{cond}", {}, []],
"UADD8%{cond}": ["Unsigned Add 8 %{cond}", {}, []],
"UQADD8%{cond}": ["Unsigned Saturating Add 8 %{cond}", {}, []],
"UHADD8%{cond}": ["Unsigned Halving Add 8 %{cond}", {}, []],
"SSUB8%{cond}": ["Signed Subtract 8 %{cond}", {}, []],
"QSUB8%{cond}": ["Saturating Subtract 8 %{cond}", {}, []],
"SHSUB8%{cond}": ["Signed Halving Subtract 8 %{cond}", {}, []],
"USUB8%{cond}": ["Unsigned Subtract 8 %{cond}", {}, []],
"UQSUB8%{cond}": ["Unsigned Saturating Subtract 8 %{cond}", {}, []],
"UHSUB8%{cond}": ["Unsigned Halving Subtract 8 %{cond}", {}, []]
},
"Divide instructions": {
"SDIV%{cond}": ["Signed Divide %{cond}", {}, []],
"UDIV%{cond}": ["Unsigned Divide %{cond}", {}, []]
},
"Miscellaneous data-processing instructions": {
"BFC%{cond}": ["Bit Field Clear %{cond}", {}, []],
"BFI%{cond}": ["Bit Field Insert %{cond}", {}, []],
"CLZ%{cond}": ["Count Leading Zeros %{cond}", {}, []],
"MOVT%{cond}": ["Move Top %{cond}", {}, []],
"RBIT%{cond}": ["Reverse Bits %{cond}", {}, []],
"REV%{cond}": ["Byte-Reverse Word %{cond}", {}, []],
"REV16%{cond}": ["Byte-Reverse Packed Halfword %{cond}", {}, []],
"REVSH%{cond}": ["Byte-Reverse Signed Halfword %{cond}", {}, []],
"SBFX%{cond}": ["Signed Bit Field Extract %{cond}", {}, []],
"SEL%{cond}": ["Select Bytes %{cond}", {}, []],
"UBFX%{cond}": ["Unsigned Bit Field Extract %{cond}", {}, []],
"USAD8%{cond}": ["Unsigned Sum of Absolute Differences %{cond}", {}, []],
"USADA8%{cond}": ["Unsigned Sum of Absolute Differences and Accumulate %{cond}", {}, []]
}
},
"Status register access instructions": {
"Banked register access instructions": {
"MRS%{cond}": ["Move to Register from Special register %{cond}", {}, []],
"MSR%{cond}": ["Move to Special register from ARM core register %{cond}", {}, []]
}
},
"Load/store instructions": {
"LDR%{cond}": ["Load Register %{cond}", {}, []],
"STR%{cond}": ["Store Register %{cond}", {}, []],
"LDRT%{cond}": ["Load Register Unprivileged %{cond}", {}, []],
"STRT%{cond}": ["Store Register Unprivileged %{cond}", {}, []],
"LDREX%{cond}": ["Load Register Exclusive %{cond}", {}, []],
"STREX%{cond}": ["Store Register Exclusive %{cond}", {}, []],
"STRH%{cond}": ["Store Register Halfword %{cond}", {}, []],
"STRHT%{cond}": ["Store Register Halfword Unprivileged %{cond}", {}, []],
"STREXH%{cond}": ["Store Register Exclusive Halfword %{cond}", {}, []],
"LDRH%{cond}": ["Load Register Halfword %{cond}", {}, []],
"LDRHT%{cond}": ["Load Register Halfword Unprivileged %{cond}", {}, []],
"LDREXH%{cond}": ["Load Register Exclusive Halfword %{cond}", {}, []],
"LDRSH%{cond}": ["Load Register Signed Halfword %{cond}", {}, []],
"LDRSHT%{cond}": ["Load Register Signed Halfword Unprivileged %{cond}", {}, []],
"STRB%{cond}": ["Store Register Byte %{cond}", {}, []],
"STRBT%{cond}": ["Store Register Byte Unprivileged %{cond}", {}, []],
"STREXB%{cond}": ["Store Register Exclusive Byte %{cond}", {}, []],
"LDRB%{cond}": ["Load Register Byte %{cond}", {}, []],
"LDRBT%{cond}": ["Load Register Byte Unprivileged %{cond}", {}, []],
"LDREXB%{cond}": ["Load Register Exclusive Byte %{cond}", {}, []],
"LDRSB%{cond}": ["Load Register Signed Byte %{cond}", {}, []],
"LDRSBT%{cond}": ["Load Register Signed Byte Unprivileged %{cond}", {}, []],
"LDRD%{cond}": ["Load Register Dual %{cond}", {}, []],
"STRD%{cond}": ["Store Register Dual %{cond}", {}, []],
"LDREXD%{cond}": ["Load Register Exclusive Dual %{cond}", {}, []],
"STREXD%{cond}": ["Store Register Exclusive Dual %{cond}", {}, []]
},
"Load/store multiple instructions": {
"LDM%{cond}": ["Load Multiple %{cond}", {"amode":{"default":"da", "da":"fa", "db":"ea", "ia":"fd", "ib":"ed"}}, []],
"POP%{cond}": ["Pop Multiple Registers %{cond}", {}, []],
"PUSH%{cond}": ["Push Multiple Registers %{cond}", {}, []],
"STM%{cond}": ["Store Multiple %{cond}", {"amode":{"default":"ia", "da":"ed", "db":"fd", "ia":"ea", "ib":"fa"}}, []]
},
"Miscellaneous instructions": {
"CLREX%{cond}": ["Clear-Exclusive %{cond}", "unconditionnal", ["unconditionnal"]],
"DBG%{cond}": ["Debug Hint %{cond}", {}, []],
"DMB%{cond}": ["Data Memory Barrier %{cond}", "unconditionnal", ["unconditionnal"]],
"DSB%{cond}": ["Data Synchronization Barrier %{cond}", "unconditionnal", ["unconditionnal"]],
"ISB%{cond}": ["Instruction Synchronization Barrier %{cond}", "unconditionnal", ["unconditionnal"]],
"IT%{cond}": ["If-Then %{cond}", "thumb_only", ["thumb_only", "it_conditions"]],
"NOP%{cond}": ["No Operation %{cond}", {}, []],
"PLD%{cond}": ["Preload Data %{cond}", "unconditionnal", ["unconditionnal"]],
"PLDW%{cond}": ["Preload Data Wide %{cond}", "unconditionnal", ["unconditionnal"]],
"PLI%{cond}": ["Preload Instruction %{cond}", "unconditionnal", ["unconditionnal"]],
"SETEND%{cond}": ["Set Endianness %{cond}", "unconditionnal", ["unconditionnal"]],
"SEV%{cond}": ["Send Event %{cond}", {}, []],
"SWP%{cond}": ["Swap %{cond}", "deprecated", ["deprecated", "byte_suffix"]],
"WFE%{cond}": ["Wait for Event %{cond}", {}, []],
"WFI%{cond}": ["Wait for Interrupt %{cond}", {}, []],
"YIELD%{cond}": ["Yield %{cond}", {}, []]
},
"Exception-generating and exception-handling instructions": {
"SVC%{cond}": ["Supervisor Call %{cond}", {}, []],
"BKPT%{cond}": ["Breakpoint %{cond}", "unconditionnal", ["unconditionnal"]],
"SMC%{cond}": ["Secure Monitor Call %{cond}", {}, []],
"RFE%{cond}": ["Return From Exception %{cond}", {"amode":{"da":"fa", "db":"ea", "ia":"fd", "ib":"ed"}}, []],
"SUBS%{cond}": ["Subtract %{cond}", {}, []],
"HVC%{cond}": ["Hypervisor Call %{cond}", "unconditionnal", ["unconditionnal"]],
"ERET%{cond}": ["Exception Return %{cond}", {}, []],
"LDM%{cond}": ["Load Multiple %{cond}", {"amode":{"ia":"fd", "da":"fa", "db":"ea", "ib":"ed"}}, []],
"SRS%{cond}": ["Store Return State %{cond}", {"amode":{"da":"ed", "db":"fd", "ia":"ea", "ib":"fa"}}, []]
},
"Coprocessor instructions": {
"CDP%{cond}": ["Coprocessor Data Processing %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"MCR%{cond}": ["Move to Coprocessor from ARM core register %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"MCRR%{cond}": ["Move to Coprocessor from two ARM core registers %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"MRC%{cond}": ["Move to ARM core register from Coprocessor %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"MRRC%{cond}": ["Move to two ARM core registers from Coprocessor %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"LDC%{cond}": ["Load Coprocessor %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal"]],
"STC%{cond}": ["Store Coprocessor %{cond}", "coprocessor_encodings", ["coprocessor_encodings", "unconditionnal", "stc_l_encoding"]]
},
"Advanced SIMD and Floating-point load/store instructions": {
"Extension register load/store instructions": {
"VLDM%{cond}": ["Vector Load Multiple %{cond}", {"amode":["ia", "db"], "vector_sizes":[32, 64]}, []],
"VLDR%{cond}": ["Vector Load Register %{cond}", {"vector_sizes":[32, 64]}, []],
"VSTM%{cond}": ["Vector Store Multiple %{cond}", {"amode":["ia", "db"], "vector_sizes":[32, 64]}, []],
"VSTR%{cond}": ["Vector Store Register %{cond}", {"vector_sizes":[32, 64]}, []]
},
"Element and structure load/store instructions": {
"VLD1%{cond}": ["Vector Load (multiple single elements) %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VLD2%{cond}": ["Vector Load (multiple 2-elements structures) %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VLD3%{cond}": ["Vector Load (multiple 3-elements structures) %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VLD4%{cond}": ["Vector Load (multiple 4-elements structures) %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VST1%{cond}": ["Vector Store (multiple single elements) %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VST2%{cond}": ["Vector Store (multiple 2-elements structures) %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VST3%{cond}": ["Vector Store (multiple 3-elements structures) %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VST4%{cond}": ["Vector Store (multiple 4-elements structures) %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]]
}
},
"Advanced SIMD and Floating-point register transfer instructions": {
"VDUP%{cond}": ["Vector Duplicate %{cond}", "vector_size", ["vector_size", "simd_conditions"]],
"VMOV%{cond}": ["Vector Move %{cond}", {"vector_types":["i8", "i16", "i32", "i64", "f32", "f64"]}, []],
"VMRS%{cond}": ["Vector Move to ARM core register %{cond}", {}, []],
"VMSR%{cond}": ["Vector Move to Advanced SIMD and Floating-Point Extension System Register from ARM core register %{cond}", {}, []]
},
"Advanced SIMD data-processing instructions": {
"Advanced SIMD parallel addition and substraction": {
"VADD%{cond}": ["Vector Add %{cond}", {"vector_types":["i8", "i16", "i32", "i64"]}, ["simd_conditions"]],
"VADDHN%{cond}": ["Vector Add and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VADDL%{cond}": ["Vector Add Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VADDW%{cond}": ["Vector Add Wide %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VH%{cond}": ["Vector Halving %{cond}", {"vector_operations":["add", "sub"], "vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VPADAL%{cond}": ["Vector Pairwise Add and Accumulate Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VPADD%{cond}": ["Vector Pairwise Add %{cond}", {"vector_types":["i8", "i16", "i32"]}, ["simd_conditions"]],
"VPADDL%{cond}": ["Vector Pairwise Add Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VRADDHN%{cond}": ["Vector Rounding Add and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VRHADD%{cond}": ["Vector Rounding Halving Add %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VRSUBHN%{cond}": ["Vector Rounding Subtract and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VQADD%{cond}": ["Vector Saturating Add %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQSUB%{cond}": ["Vector Saturating Subtract %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VSUB%{cond}": ["Vector Subtract %{cond}", {"vector_types":["i8", "i16", "i32", "i64"]}, ["simd_conditions"]],
"VSUBHN%{cond}": ["Vector Subtract and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VSUBL%{cond}": ["Vector Subtract Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VSUBW%{cond}": ["Vector Subtract Wide %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]]
},
"Bitwise Advanced SIMD data-processing instructions": {
"VAND%{cond}": ["Vector Bitwise AND %{cond}", "simd_conditions", ["simd_conditions"]],
"VBIC%{cond}": ["Vector Bitwise Bit Clear %{cond}", {"vector_types":["i16", "i32"]}, []],
"VEOR%{cond}": ["Vector Bitwise Exclusive OR %{cond}", "simd_conditions", ["simd_conditions"]],
"VBIF%{cond}": ["Vector Bitwise Insert if False %{cond}", "simd_conditions", ["simd_conditions"]],
"VBIT%{cond}": ["Vector Bitwise Insert if True %{cond}", "simd_conditions", ["simd_conditions"]],
"VBSL%{cond}": ["Vector Bitwise Select %{cond}", "simd_conditions", ["simd_conditions"]],
"VMOV%{cond}": ["Vector Move %{cond}", {"vector_types":["s8", "s16", "u8", "u16", "32", "i8", "i16", "i32", "i64", "f32"]}, ["simd_conditions"]],
"VMVN%{cond}": ["Vector Bitwise NOT %{cond}", {"vector_types":["i16", "i32"]}, ["simd_conditions"]],
"VORR%{cond}": ["Vector Bitwise OR %{cond}", {"vector_types":["i16", "i32"]}, ["simd_conditions"]],
"VORN%{cond}": ["Vector Bitwise OR NOT %{cond}", {"vector_types":["i16", "i32"]}, ["simd_conditions"]]
},
"Advanced SIMD comparison instructions": {
"VAC%{cond}": ["Vector Absolute Compare %{cond}", {"comparaisons":["ge", "gt", "le", "lt"], "vector_types":["f32"]}, ["simd_conditions"]],
"VC%{cond}": ["Vector Compare %{cond}", {"comparaisons":["eq", "ge", "gt", "le", "lt"], "vector_types":["i8", "i16", "i32", "f32"]}, ["simd_conditions"]],
"VTST%{cond}": ["Vector Test %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]]
},
"Advanced SIMD shift instructions": {
"VQRSHL%{cond}": ["Vector Saturating Rounding Shift Left %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQRSHRN%{cond}": ["Vector Saturating Rounding Shift Right Narrow %{cond}", {"vector_types":["s16", "s32", "s64", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQRSHRUN%{cond}": ["Vector Saturating Rounding Shift Right Unsigned Narrow %{cond}", {"vector_types":["s16", "s32", "s64"]}, ["simd_conditions"]],
"VQSHL%{cond}": ["Vector Saturating Shift Left %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQSHLU%{cond}": ["Vector Saturating Shift Left Unsigned %{cond}", {"vector_types":["s8", "s16", "s32", "s64"]}, ["simd_conditions"]],
"VQSHRN%{cond}": ["Vector Saturating Shift Right Narrow %{cond}", {"vector_types":["s16", "s32", "s64", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQSHRUN%{cond}": ["Vector Saturating Shift Right Unsigned Narrow %{cond}", {"vector_types":["s8", "s16", "s32", "s64"]}, ["simd_conditions"]],
"VRSHL%{cond}": ["Vector Rounding Shift Left %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VRSHR%{cond}": ["Vector Rounding Shift Right %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VRSRA%{cond}": ["Vector Rounding Shift Right and Accumulate %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VRSHRN%{cond}": ["Vector Rounding Shift Right and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VSHL%{cond}": ["Vector Shift Left %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64", "i8", "i16", "i32", "i64"]}, ["simd_conditions"]],
"VSHLL%{cond}": ["Vector Shift Left Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32"]}, ["simd_conditions"]],
"VSHR%{cond}": ["Vector Shift Right %{cond}", {"vector_types":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VSHRN%{cond}": ["Vector Shift Right Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VSLI%{cond}": ["Vector Shift Left and Insert %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VSRA%{cond}": ["Vector Shift Right and Accumulate %{cond}", {"vector_sizes":["s8", "s16", "s32", "s64", "u8", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VSRI%{cond}": ["Vector Shift Right and Insert %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]]
},
"Advanced SIMD multiply instructions": {
"VML%{cond}": ["Vector Multiply and %{cond}", {"operations":["accumulate", "accumulate_long", "subtract", "subtract_long"], "vector_types":["s8", "s16", "s32", "u8", "u16", "u32", "i8", "i16", "i32"]}, ["simd_conditions"]],
"VMUL%{cond}": ["Vector Multiply %{cond}", "long", ["long", "simd_conditions"]],
"VFMA%{cond}": ["Vector Fused Multiply %{cond}", {"operations":["accumulate", "subtract"], "vector_types":["f32", "f64"]}, ["simd_conditions"]],
"VQDMLAL%{cond}": ["Vector Saturating Doubling Multiply %{cond}", {"operations":["accumulate_long", "subtract_long"], "vector_types":["s16", "s32"]}, ["simd_conditions"]],
"VQDMULH%{cond}": ["Vector Saturating Doubling Multiply Returning High Half %{cond}", {"vector_types":["s16", "s32"]}, ["simd_conditions"]],
"VQRDMULH%{cond}": ["Vector Saturating Rounding Doubling Multiply Returning High Half %{cond}", {"vector_types":["s16", "s32"]}, ["simd_conditions"]],
"VQDMULL%{cond}": ["Vector Saturating Doubling Multiply Long %{cond}", {"vector_types":["s16", "s32"]}, ["simd_conditions"]]
},
"Miscellaneous Advanced SIMD data-processing instructions": {
"VABA%{cond}": ["Vector Absolute Difference and Accumulate %{cond}", {"suffixes":["long"], "vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VABD%{cond}": ["Vector Absolute Difference %{cond}", {"suffixes":["long"], "vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VABS%{cond}": ["Vector Absolute %{cond}", {"vector_types":["s8", "s16", "s32", "f32", "f64"]}, ["simd_conditions"]],
"VCVT%{cond}": ["Vector Convert between integer and floating-point %{cond}", {"vector_conversions":["s32", "f32", "u32", "f32", "s32", "f64", "u32", "f64", "f16", "f32", "s16", "f32", "s16", "f64", "u16", "f32", "u16", "f64"]}, []],
"VCLS%{cond}": ["Vector Count Leading Sign Bits %{cond}", {"vector_types":["s8", "s16", "s32"]}, ["simd_conditions"]],
"VCLZ%{cond}": ["Vector Count Leading Zeros %{cond}", {"vector_types":["i8", "i16", "i32"]}, ["simd_conditions"]],
"VCNT%{cond}": ["Vector Count 1 bits %{cond}", {"vector_sizes":[8]}, ["simd_conditions"]],
"VDUP%{cond}": ["Vector Duplicate %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VEXT%{cond}": ["Vector Extract %{cond}", {"vector_sizes":[8, 16, 32, 64]}, ["simd_conditions"]],
"VMOVN%{cond}": ["Vector Move and Narrow %{cond}", {"vector_types":["i16", "i32", "i64"]}, ["simd_conditions"]],
"VMOVL%{cond}": ["Vector Move Long %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VMAX%{cond}": ["Vector Maximum %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VMIN%{cond}": ["Vector Minimum %{cond}", {"vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VNEG%{cond}": ["Vector Negate %{cond}", {"vector_types":["s8", "s16", "s32", "f32"]}, ["simd_conditions"]],
"VPMAX%{cond}": ["Vector Pairwise %{cond}", {"operations":["min", "max"], "vector_types":["s8", "s16", "s32", "u8", "u16", "u32"]}, ["simd_conditions"]],
"VRECPE%{cond}": ["Vector Reciprocal Estimate %{cond}", {"vector_types":["u32", "f32"]}, ["simd_conditions"]],
"VRECPS%{cond}": ["Vector Reciprocal Step %{cond}", {"vector_types":["f32"]}, ["simd_conditions"]],
"VRSQRTE%{cond}": ["Vector Reciprocal Square Root Estimate %{cond}", {"vector_types":["u32", "f32"]}, ["simd_conditions"]],
"VRSQRTS%{cond}": ["Vector Reciprocal Square Root Step %{cond}", {"vector_types":["f32"]}, ["simd_conditions"]],
"VREV16%{cond}": ["Vector Reverse in %{cond}", {"vector_reverse":[16, 32, 64], "vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VQABS%{cond}": ["Vector Saturating Absolute %{cond}", {"vector_types":["s16", "s32", "s64"]}, ["simd_conditions"]],
"VQMOVN%{cond}": ["Vector Move and Narrow %{cond}", {"vector_types":["s16", "s32", "s64", "u16", "u32", "u64"]}, ["simd_conditions"]],
"VQMOVUN%{cond}": ["Vector Move Unsigned and Narrow %{cond}", {"vector_types":["s16", "s32", "s64"]}, ["simd_conditions"]],
"VQNEG%{cond}": ["Vector Saturate Negate %{cond}", {"vector_types":["s16", "s32", "s64"]}, ["simd_conditions"]],
"VSWP%{cond}": ["Vector Swap %{cond}", "simd_conditions", ["simd_conditions"]],
"VTBL%{cond}": ["Vector Table Lookup %{cond}", "simd_conditions", ["simd_conditions"]],
"VTBX%{cond}": ["Vector Table Extension %{cond}", "simd_conditions", ["simd_conditions"]],
"VTRN%{cond}": ["Vector Transpose %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VUZP%{cond}": ["Vector Unzip %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]],
"VZIP%{cond}": ["Vector Zip %{cond}", {"vector_sizes":[8, 16, 32]}, ["simd_conditions"]]
}
},
"Floating-point data-processing instructions": {
"VABS%{cond}": ["Vector Absolute %{cond}", {"vector_types":["f32", "f64"]}, []],
"VADD%{cond}": ["Vector Add %{cond}", {"vector_types":["f32", "f64"]}, ["simd_conditions"]],
"VCMP%{cond}": ["Vector Compare %{cond}", {"vector_types":["f32", "f64"], "operations":["exception"]}, []],
"VCVT%{cond}": ["Vector Convert %{cond}", {"vector_conversions":["f32", "f64", "f16", "f32"]}, []],
"VCVTR%{cond}": ["Vector Convert Rounding %{cond}", {"vector_conversions":["s32", "f32", "u32", "f32", "s32", "f64", "u32", "f64"]}, []],
"VCVTT%{cond}": ["Vector Convert Top %{cond}", {"vector_conversions":["f16", "f32"]}, []],
"VCVTB%{cond}": ["Vector Convert Bottom %{cond}", {"vector_conversions":["f16", "f32"]}, []],
"VDIV%{cond}": ["Vector Divide %{cond}", {"vector_types":["f32", "f64"]}, []],
"VMLA%{cond}": ["Vector Multiply and %{cond}", {"operations":["accumulate", "subtract"], "vector_types":["f32", "f64"]}, ["simd_conditions"]],
"VFMA%{cond}": ["Vector Fused Multiply %{cond}", {"operations":["accumulate", "subtract"], "vector_types":["f32", "f64"]}, []],
"VMOV%{cond}": ["Vector Move %{cond}", {"vector_types":["f32", "f64"]}, ["simd_conditions"]],
"VMUL%{cond}": ["Vector Multiply %{cond}", {"vector_types":["f32", "f64"]}, ["simd_conditions"]],
"VNEG%{cond}": ["Vector Negate %{cond}", {"vector_types":["s8", "s16", "s32", "f32"]}, ["simd_conditions"]],
"VNMLA%{cond}": ["Vector Negate Multiply and %{cond}", {"operations":["accumulate", "subtract"], "vector_types":["f32", "f64"]}, []],
"VNMUL%{cond}": ["Vector Negate Multiply %{cond}", {"vector_types":["f32", "f64"]}, []],
"VFNM%{cond}": ["Vector Fused Negate Multiply %{cond}", {"operations":["accumulate", "subtract"], "vector_types":["f32", "f64"]}, []],
"VSQRT%{cond}": ["Vector Square Root %{cond}", {"vector_types":["f32", "f64"]}, []],
"VSUB%{cond}": ["Vector Subtract %{cond}", {"vector_types":["f32", "f64"]}, ["simd_conditions"]]
}
}
}