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Contributed Projects
| Project Name | Organization | Documentation |
| Encap_Decap | Stanford University | link |
| Arp_Reply | Stanford University | link |
| Flash_Oped | University of Cambridge | link |
| Memcached_Client | Xilinx | link |
| Netflow_Simple | Universidad Autonoma de Madrid | link |
| NIC_Oped | Stanford University | link |
| NIC_Oped_1G | Stanford University | link |
| NIC_SRAM | Stanford University | link |
| Openflow_Switch | Stanford University | link |
| Ported_NIC_Oped_1G | University of Pisa | link |
| Ported_Router_10G | University of Pisa | link |
| Ported_Router_Oped_10G | University of Pisa | link |
| Ported_Switch_Oped_10G | University of Pisa | link |
| Reg_io | University of Cambridge | link |
| RLDRAM_MMAP | University of Cambridge | link |
| RLDRAM_xapp852 | University of Cambridge | link |
| Simple_Switch_Oped_10G | Xilinx | link |
| RLDRAM_Stream | University of Cambridge | link |
##Encap_Decap
Owner: Yilong Geng
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This is a testing project for the nf10_encap module and the nf10_decap module. This project added the nf10_encap module and the nf10_decap module into the NIC data path. It can add an IP header to the packet according to its output port, or remove the additional IP header of an packet if it's using the encapsulation protocol.
Wiki Page: Encap_Decap wiki page
Github Repository:
##Arp_Reply
Owner: Yilong Geng
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This is a testing project for the arp_reply module. This project added the arp_reply module into the NIC data path. It can reply ARP requests according to the IP-MAC address pairs set in the configuration registers.
Wiki Page: Arp_Reply wiki page
Github Repository:
##Flash_Oped
Owner: Muhammad Shahbaz
Organization: University of Cambridge
Date Added: 04/08/2014
Short Description: This project provides a basic framework for automatic configuration of the NetFPGA-10G card's FPGA with OPED DMA.
Wiki Page: Flash_Oped wiki page
Github Repository:
##Memcached_Client
Owner: Michaela Blott
Organization: Xilinx
Date Added: 04/08/2014
Short Description: The NetFPGA-10G Testclient can be used to test the performance, latency and correctness of an application server. It comes with an interactive configuration terminal for the host that can be fully automated using python. It allows to load test scenarios directly from packet capture files (.pcap). Finally, support scripts to use it as a memcached testclient right away are included in this project.
Wiki Page: Memcached_Client wiki page
Github Repository:
##NetFlow_Simple
Owner: Marco Forconesi
Organization: Universidad Autonoma de Madrid
Date Added: 04/08/2014
Short Description: This project captures the active flows received on a 10 Gbps Ethernet interface and exports them via other 10 Gbps Ethernet interface using the NetFlow v5 protocol.
Wiki Page: NetFlow_Simple wiki page
Github Repository:
##NIC_Oped
Owner: Adam Covington
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This is a NIC project using OPED as DMA engine.
Wiki Page: NIC_Oped wiki page
Github Repository:
##NIC_Oped_1G
Owner: Adam Covington
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This project uses OPED as DMA engine and 1G Interfaces.
Wiki Page: NIC_Oped_1G wiki page
Github Repository:
##NIC_SRAM
Owner: Sam D'Amico
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This NIC uses the SRAM FIFO module to act as a packet buffer.
Wiki Page: NIC_SRAM wiki page
Github Repository:
##Openflow_Switch
Owner: Tatsuya Yabe
Organization: Stanford University
Date Added: 04/08/2014
Short Description: This is a hardware portion of OpenFlow1.0 Switch on NetFPGA-10G. The main role of the hardware portion is to modify packet header fields and forward it from one port to another/other port(s) at a line rate, with referring to flow tables residing in hardware.
Wiki Page: Openflow_Switch wiki page
Github Repository:
##Ported_NIC_Oped_1G
Owner: Gianni Antichi
Organization: University of Pisa
Date Added: 04/08/2014
Short Description: This is a NIC. It uses OPED as DMA engine and the Output Port Lookup logic taken from the NetFPGA-1G pipeline.
Wiki Page: Ported_NIC_Oped_1G wiki page
Github Repository:
##Ported_Router_10G
Owner: Gianni Antichi
Organization: University of Pisa
Date Added: 04/08/2014
Short Description: This is a PW-OSPF Router. It uses the Output Port Lookup logic taken from the NetFPGA-1G pipeline.
Wiki Page: Ported_Router_10G wiki page
Github Repository:
##Ported_Router_Oped_10G
Owner: Gianni Antichi
Organization: University of Pisa
Date Added: 04/08/2014
Short Description: This is a PW-OSPF Router. It OPED as DMA engine and the Output Port Lookup logic taken from the NetFPGA-1G pipeline.
Wiki Page: Ported_Router_Oped_10G wiki page
Github Repository:
##Ported_Switch_Oped_10G
Owner: Gianni Antichi
Organization: University of Pisa
Date Added: 04/08/2014
Short Description: This is a L2 Switch. It OPED as DMA engine and the Output Port Lookup logic taken from the NetFPGA-1G pipeline.
Wiki Page: Ported_Switch_Oped_10G wiki page
Github Repository:
##Reg_io
Owner: Muhammad Shahbaz
Organization: University of Cambridge
Date Added: 04/08/2014
Short Description: This is a Register IO sample project using the DMA engine.
Wiki Page: Reg_io wiki page
Github Repository:
##RLDRAM_MMAP
Owner: Muhammad Shahbaz
Organization: University of Cambridge
Date Added: 04/08/2014
Short Description: This is a memory mapped RLDRAM project using the DMA engine.
Wiki Page: RLDRAM_MMAP wiki page
Github Repository:
##RLDRAM_xapp852
Owner: Muhammad Shahbaz
Organization: University of Cambridge
Date Added: 04/08/2014
Short Description: This project implements a patch for simulating and running the Xilinx Application Note (XAPP852) - RLDRAM II Memory Interface for Virtex-5 FPGAs.
Wiki Page: RLDRAM_xapp852 wiki page
Github Repository:
##Simple_Switch_Oped_10G
Owner: Michaela Blott
Organization: Xilinx
Date Added: 04/08/2014
Short Description: This project implements a bare minimum functionality of a learning CAM switch. In general, it's useful as a base module for implementing more complex custom switching fabrics.
Wiki Page: Simple_Switch_Oped_10G wiki page
Github Repository:
##RLDRAM_Stream
Owner: Jong Hun Han
Organization: University of Cambridge
Date Added: 06/03/2014
Short Description: This RLDRAM AXI-Stream contrib project is to implement a reference nic with a Xilinx RLDRAM controller to use the RLDRAM as a packet buffer.
Wiki Page: RLDRAM Stream wiki page
Github Repository: