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NetFPGA 10G Learning CAM Switch
reference_switch
projects/reference_switch
- NetFPGA-10G Specific cores
- Xilinx AXI Peripheral
- Microblaze Subsystem
- Other
The division of the hardware into modules was hinted in the previous section. Understanding these modules is essential in making the most of the available designs. The distributed projects in the NFP, including the Switch, all follow the same modular structure. This design is a pipeline where each stage is a separate module. Please, refer to the Reference NIC project for more information.
The first stage in the pipeline consists of several queues which we call the Rx queues. These queues receive packets from IO physical ports (i.e., 10GMAC) and provide a unified interface (AXI) to the rest of the system.
In the main datapath, the first module a packet passes through is the Input Arbiter. The input arbiter decides which Rx queue to service next, and pulls the packet from that Rx queue and hands it to the next module in the pipeline: The output port lookup module. The output port lookup module is responsible for deciding which port a packet goes out of. Here it is actually implemented the learning CAM switch logic. The 16-entries CAM table is consulted to make the frame forwarding decision. It learns MAC addresses from the source address of Ethernet frames on the ports. After that decision is made, the packet is then handed to the output queues module which stores the packet in the output queues corresponding to the output port until the Tx queue is ready to accept the packet for transmission.
The Tx queues are analogous to the Rx queues and they send packets out of the IO ports instead of receiving.
Note: Actually, the reference switch is not able to support the fully 40G line rate in the worst case scenario.
all the informations could be found here.
Each projects has some features that are verified by doing Simulation tests and HW tests. The test infrastructure is based on the python. You can find the tests inside the projects/{project_name}/test folder.
To run the test, you need two machines, A and B. Let's say Machine A is equipped with NetFPGA and Machine B is equipped with a third-party 10G dual-port NIC.
Download the reference_switch bitfile from projects/reference_switch/bitfiles/reference_switch.bit. (Refer to Production Test Manual if you don't know how to download the bitfile and/or not setup JTAG cable yet.)
Connect Machine A and Machine B using two 10G cables. Assume we use nf0 (the port nearest to the PCI Express) and nf1 on Machine A and eth1 and eth2 on Machine B. Generate packets from eth1 with given MAC addresses (let's say, dest-MAC = x and src-MAC = y). Check that all the NetFPGA physical ports send back the packet. Then, generate from eth2 packets with dest-MAC = y and src-MAC = x. You will be able to see that only nf0 will forward back packets.