NetFPGA 1G CML Reference Manual
- Overview
- FPGA Configuration
- Power Supplies
- Oscillators and Clocks
- FPGA Memory
- DDR3 Memory
- QDRII+ Memory
- BPI Flash Memory
- SD Card
- PCIe Interface
- Ethernet PHYs
- PIC Subsystem
- On-Board I/O
- PMOD Expansion Connectors
- FMC Expansion Connector
- Appendix A: Manufacturing Test
- Appendix B: FPGA Pin Constraints
The NetFPGA-1G-CML is a versatile, low cost network hardware development platform featuring a Xilinx Kintex-7 XC7K325T FPGA and includes four Ethernet interfaces capable of negotiating up to 1 GB/s connections. 512 MB of 800 MHz DDR3 can support high-throughput packet buffering while 4.5 MB of QDRII+ can maintain low-latency access to high demand data, like routing tables. Rapid boot configuration is supported by a 128 MB BPI Flash, which is also available for non-volatile storage applications. The standard PCIe form factor supports high speed x4 Gen 2 interfacing. The FMC carrier connector provides a convenient expansion interface for extending card functionality via Select I/O and GTX serial interfaces. The FMC connector can support SATA-II data rates for network storage applications. The FMC connector can also be used to extend functionality via a wide variety of other cards designed for communication, measurement, and control.
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The Kintex-7 XC7K325T-1FFG676 FPGA has ample logic and I/O capacity for
supporting a wide range of designs with the following capabilities:
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The system logic configuration is stored within the FPGA in SRAM-based memory cells. This data defines the FPGA’s logic functions and circuit connections, but it is volatile since it remains valid only as long as power is applied. Because of this, the device is configured (i.e. programmed) every time it is turned-on. In addition, it may also be re-configured at any time power is applied. Once power is removed, the most recently programmed logic configuration is lost. The configuration data is commonly called a bitstream which is most often contained in files of type “.bit” or “.mcs”. These files may be created several different ways using Xilinx development software.
The FPGA may be configured from three different sources. These include the on-board BPI flash, an off-board USB flash drive, or via a PC. The NetFPGA-1G-CML follows a specific configuration sequence when it powers up and comes out of reset. If a valid “download.bit” file is detected on an attached USB flash drive, that bitstream will be used to program the FPGA. The flash drive must be FAT formatted, contain a single “download.bit” file, and be attached to the USB-HOST port (J13) with jumper JP4 in place. If no flash drive bitstream is detected, an attempt will be made to configure the device from the on-board BPI flash address 0x0. If no flash bitstream is available, the board idles until it is programmed from a PC. PC programming can be done either via a USB cable connected to the USB PROG port (J12), or a JTAG programming cable connected to the XILINX PROG CABLE port (J15). Any flash drive bitstreams that are not built for the Xilinx XC7K325T FPGA will be ignored. This power-on programming sequence can be re-initiated at any time after power is applied by depressing the red PROG button (BTN5).
Both Digilent and Xilinx distribute free software that can be used to transfer bitstreams from a PC as well as create bitstream files to load via a flash drive. Digilent’s Adept and Xilinx’s iMPACT applications can directly program the FPGA using a .bit file via a standard USB A to Micro B cable connected to J12 or through any of several Digilent JTAG programming cables connected to J15. The on-board BPI flash is programmed via similar means. When programming the BPI, iMPACT transfers a .mcs format bitstream to the flash in a two-step process. iMPACT first programs the FPGA directly with a special purpose BPI flash interface. It will then transfer the .mcs bitstream to the flash through that interface. This process is fully automated by the iMPACT program, so a designer only needs to be concerned with the creation of the .mcs file using Xilinx’s design software.
More details on configuring the XC7K325T FPGA via the on board BPI (using Master BPI mode), via the PIC USB-HOST (using Slave Serial mode), and via the JTAG mode can be found in the Xilinx 7 Series FPGAs Configuration User Guide (UG470).
The NetFPGA-1G-CML requires a 12V, 5A, or greater power source. Power is supplied via the J17 Molex connector at the rear of the PCB, as is often done with high performance PC graphics cards. No power is supplied via the PCIe motherboard bus connector. If a PCIe Molex connector is not available, an adapter (Logisys AD201 or equivalent) can be used to convert the more common 12V 6-pin connections to the required PCIe Molex.
When not installed on a PC motherboard, the NetFPGA-1G-CML can be used on a desktop with the included support posts. Either a stand-alone PC power supply or a power brick (e.g. Digilent SWPS-60W) can be used to provide power on the desktop, but a special adapter must be used with the power brick (Fig. 1.). Note that power bricks use a keyed connector that is incompatible with the J17 Molex connector. Do not attempt to force a power brick connector into J17. If you wish to use a power brick with the NetFPGA-1G-CML on the desktop, construct an adapter like that shown in Fig. 1. Note that the connectors are shown from the connection side in the diagram.
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| Figure 1. Power Adapter for Digilent SWPS-60W (connector end view). |
Analog Devices voltage regulators provide a number of on-board power and reference voltages that are derived from the main 12V supply, as shown in Table
- Supply power-on and power-off sequencing follows manufacturer recommendations. The on-board battery that supports encryption key storage and the real-time clock is charged when the PCB is powered on and should not need to be replaced during the lifetime of the board.
VADJ controls the signal levels used between the FMC connector and two FPGA Select I/O banks and can be set to 1.2 V, 1.8 V, 2.5 V, or 3.3 V as needed. The board is shipped with the VADJ supply turned off. To turn on VADJ, jumper JP5 is installed and the FPGA is configured to drive the VADJ_EN pin (AD16) high. The VADJ voltage is selected via the FPGA configuration using pins AF19 and AF20 as shown in Table 2.
When jumper JP4 is in place, the USB HID connector provides 5V at up to 0.5 A to external USB devices, including keyboards, mice, and thumb drives. An Analog Devices ADM1177 hot swap controller and power monitor is used to limit output current and allow safe device attachment and removal while the board is powered up. The PIC can also measure USB current and voltage by accessing the on-chip power monitor via the PIC I2C peripheral bus.
The Xilinx Kintex-7 Data Sheet: DC and AC Switching Characteristics (DS182) provides more information on the power supply requirements of the FPGA board.
| Supply | Derived From | Application |
|---|---|---|
| 5.0 V | 12.0 V | USB HID; FMC |
| 3.3 V | 12.0 V | SD Card; Ethernet PHYs; Cypress FX2LP; Microchip PIC; BPI Flash; FPGA I/O Banks 14,15; FMC; PMODs |
| 2.0 V | 5.0 V | FPGA auxiliary supply, VCCBAT; Backup battery; Real-time clock backup. |
| 1.8 V | 12.0 V | QDRII+ supply |
| 1.8 V | 3.3 V | FPGA GTX transceiver Quad PLL |
| 1.5 V | 12.0 V | DDR3; FPGA I/O Bank 34 |
| 1.2 V | 12.0 V | FPGA GTX transceiver termination |
| 1.0 V | 12.0 V | FPGA GTX analog supply |
| 1.0 V | 3.3 V | FPGA Core |
| 0.9 V | 3.3 V | QDRII+ reference |
| 0.75 V | 3.3 V | DDR3 reference |
| VADJ | 12.0 V | FPGA I/O Banks 12, 13; FMC; Configurable. |
| Table 1. On-board Power Supplies |
| SET_VADJ2 (FPGA AF20) | SET_VADJ1 (FPGA AF19) | VADJ |
|---|---|---|
| 0 | 0 | 1.2 V |
| 0 | 1 | 1.8 V |
| 1 | 0 | 2.5 V |
| 1 | 1 | 3.3 V |
| Table 2. VADJ Settings |
On-board oscillators support various board subsystems. A low-jitter 125 MHz oscillator is provided for the Ethernet PHYs and a 50 MHz oscillator drives the FPGA master configuration clock. The Cypress FX2LP and Microchip PIC microcontrollers each contain on-chip oscillators running at 24 MHz and 8 MHz, respectively.
The main FPGA system clock is provided by an ultra-low-jitter 200 MHz differential oscillator connected to pins AA2 and AA3 in I/O bank 34. This can drive up to ten internal PLLs (Phase Locked Loops) and MMCMs (Mixed-Mode Clock Managers) on the FPGA for high-performance multi-clock-domain designs. Please refer to the Xilinx 7-series Clock Resources User Guide (UG472) for more details on FPGA internal clocking resources.
The XC7K325T FPGA includes 445 on-chip Block RAMs (BRAMs) of 36Kb, or 4096 bytes with two-bit error correction, which amounts to a total of 1.78 MB of on-chip, error-corrected static RAM that can be used for a variety of purposes ranging from program storage for deeply embedded “bare metal” applications to data buffering and table lookup. Each 36Kb BRAM can be partitioned into two completely independent 18Kb RAMs to help facilitate more efficient hardware utilization. Furthermore, each BRAM can be configured for dual-port operation and includes register infrastructure to support FIFO functionality. These BRAM ports can be organized in either single or dual-clock configurations. The Xilinx tool chain includes a rich selection of resources for on-chip BRAM configuration and initialization. Further information is provided in the Xilinx 7 Series FPGAs Memory Resources User Guide (UG473).
The NetFPGA-1G-CML includes a Micron MT41K512M8 512 MB DDR3 SDRAM which employs an 800 MHz byte-wide data bus capable of operating at a data rate of 1600 MT/s. Project development with the SDRAM involves using the Xilinx Memory Interface Generator (MIG) in either the XPS design tool or the Vivado Design Suite. The MIG is an interface generation wizard for selecting part types and configuring FPGA Select I/O resources for the memory hardware interface. The interface is automatically configured by the MIG for use with the AXI4 system bus and provides options for 2:1 or 4:1 memory-to-bus clock ratios. The NetFPGA-1G-CML uses a VCCAUX-IO of 2.0V to support high performance DDR3 frequency settings. Please see the Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586) and the Micron 4Gb:x4,x8,x16 DDR3L SDRAM data sheet for more details.
A 4.5 MB Cypress CY7C2263KV18 QDRII+ Quad Data Rate SRAM is provided for applications that require high speed, low-latency memory. Common applications include FIFO buffers and table lookups. The notion of “Quad” data rate comes from the ability to simultaneously read from a unidirectional read port and write to a unidirectional write port on both clock edges. The NetFPGA-1G-CML QDRII+ is capable of operating at up to 450MHz to yield data transfer rates of up to 900 MT/s per 2-byte port. This yields a peak bandwidth of up to 3.6 GB/s. The Xilinx CORE Generator is able to generate and configure a physical layer interface into the QDRII+ via the user friendly Memory Interface Generator (MIG) wizard. More information regarding the QDRII+ memory part and the Xilinx MIG tool can be found in the Cypress CY7C2263KV18/CY7C2265KV18 data sheet, the Cypress Application Note QDR-II, QDR-II+, DDR-II, DDR-II+ Design Guide (AN4065), and the Xilinx 7 Series FPGAs Memory Interface Solutions User Guide (UG586).
A 1-Gbit Micron BPI (Byte Peripheral Interface) flash memory in a 128 MB x16 configuration is provided to support high-speed FPGA configuration after board reset. High-speed single-step configuration enables enumeration via the PCIe interface within 100 mS, as required by the PCI specification. In BPI configuration mode, the FPGA acts as the bus master, driving the flash address and control signals to transfer previously stored bitstream data into the configuration SRAM.
The BPI flash has enough capacity to store multiple device configurations. This facilitates multi-stage configuration boot as well as applications that utilize dynamic reconfiguration. Configuration bitstreams are not the only data which can be stored in the BPI flash. After configuration is complete, the BPI programming pins may be used as normal Select I/O within the design. As a result, non-volatile data of any type can also be stored to and retrieved from the BPI after device configuration is complete. More information regarding BPI based device configuration is available in the Xilinx 7 Series FPGAs Configuration User Guide (UG470) and application note XAPP587 BPI Fast Configuration and iMPACT Flash Programming with 7 Series FPGAs. Please also refer to the Micron P30-65nm Flash Memory data sheet for more specifics regarding device operation.
The NetFPGA-1G-CML SD card connector supports a second non-volatile storage resource which is also removable. This connector supports a standard size SD memory card and meets all physical layer requirements of both SPI and SD bus protocols. It supports the UHS-I pin assignment standard (but not UHS-II) and provides high speed signaling at 3.3V to support SC, HC, and XC class SD cards. Please see SD Specifications Part 1 Physical Layer Simplified Specification by the Technical Committee of the SD Card Association for more details regarding the use of SD memory cards with this connector.
The NetFPGA-1G-CML is designed with a PCI-Express form factor to support interconnection with common processor motherboards. Four of the FPGA’s eight high speed serial GTX transceivers are dedicated to implementing up to four-lanes of Gen. 2.0 (5 GB/s) PCIe communications with a host processing system. These transceivers work in conjunction with the on-chip 7 Series Integrated PCI Express Block and synthesizable on-chip logic to provide a scalable, high performance PCI Express I/O core.
This core is configured and incorporated into designs using either the Xilinx ISE Coregen tool or via instantiation and customization from the Vivado Design Suite IP catalog. Please refer to the Xilinx 7 Series FPGAs Integrated Block for PCI Express V2.0 (PG054) product guide and 7 Series FPGAs GTX/GTH Transceivers (UG476) user guide for more information.
Four Realtek RTL8211 Ethernet transceivers (PHYs) are provided to interface to network connections via on-board RJ-45 connectors. Each RJ-45 has two LEDs to indicate link status and activity. Each PHY controls three LEDs: two on an associated RJ-45 and a third on-board (LD5 –LD8.) The PHYs are programmed via a shared MDIO bus and are accessed via MDIO addresses 1 through 4: corresponding to connectors ETH1 through ETH4 on the PCB. At reset, each PHY defaults to 1Gbps with the LED configuration shown in Table 3.
On each RJ45, the bottom LED is the one that is closest to the PCIe connector. The default behavior of the on-board LED is to mimic that of the top RJ45 LED. The default auto-negotiation behavior allows each PHY to independently adjust its data rate to 10/100 Mbps or 1Gbps as needed.
Data is transferred to and from the PHYs via a Reduced Gigabit Media Independent Interface (RGMII). This is similar to the Gigabit Media Independent Interface (GMII), which uses eight bits for both transmit and receive data. RGMII achieves the same data rate with half the number of data bits and double-data-rate clocking. 1 Gbps data transfers are thereby achieved using a 125MHz clock with four bits transferred on each clock edge for both send and receive. This provides a significant reduction in the number of FPGA I/O pins required to support the four Ethernet interfaces.
Xilinx provides Ethernet MAC IP that will support 10/100/1000 Mb/s via the ISE Design Suite Coregen tool and the Vivado design suite. Please refer to Xilinx Product Guide PG051 LogiCORE IP Tri-Mode Ethernet MAC for more information.
| LED | Action | Meaning |
|---|---|---|
| RJ45 Top | Slow blink | Connection Negotiation Complete |
| On | Link activity present
RJ45 Bottom | Off | No link activity | Fast blink | Link activity present Table 3. RJ-45 Ethernet Connector LED Function.
NetFPGA-1G-CML includes a 32-bit PIC microcontroller for managing USB OTG, real-time clock, and secure storage interfacing. The PIC is pre-programmed with manufacturing test code and an ability to load FPGA bitstreams from a USB memory stick. It is possible to re-program the PIC to support end-user applications that make use of various other PIC subsystem features. This may be done via J14 using a PICKit 3 In-Circuit Debugger (Digilent p/n PG164130). If you choose to reprogram the PIC subsystem, it is recommended that you carefully study the board schematic to avoid issues that may arise with conflicting signal levels.
To run the pre-programmed manufacturing test, first set up the NetFPGA-1G-CML and host PC as described in Appendix A: Manufacturing Test. When the board is powered on, the factory-loaded PIC firmware will search for the bitstream “mfg_test.bit” on the USB flash drive and use it to configure the FPGA in slave serial mode. After the FPGA has been configured, a test menu will be displayed on the terminal emulator window connected to the PmodUSBUART, and the user can run the tests by following the menu prompts. If the board is set up as described in Appendix A, all tests should pass.
The address map of the PIC I2C peripherals is shown in Table 4. The PIC is also connected to an MX25L12835E SPI Serial Flash using general-purpose I/O ports for increased data storage. The flash's pins are connected to the PIC ports as shown in Table 5.
To program the PIC device, connect a PICkit 3 to the NetFPGA-1G-CML by placing a 1x6 pin header in the zig-zag connector J14 and connect it to the PICkit 3 using a 6-pin cable. If Digilent's 6-pin Pmod cable is used, the white indicator dot on the NetFPGA-1G-CML side should be above pin 6, and the dot on the PICkit 3 side will be face-up and opposite the white arrow on the PICkit 3. The PIC can then be programmed from Microchip's MPLAB X or MPLAB IPE by selecting the PICkit 3 as the programming tool.
| Component Name | PIC I2C Controller | I2C 7-bit Address |
|---|---|---|
| AD5274 Digital Rheostat | I2C2 | 0101110 |
| ADM1177 Hot Swap Controller | I2C2 | 1011011 |
| ATSHA204 CryptoAuthentication | I2C2 | 1100100 |
| M41T62 Real-Time Clock | I2C2 | 1101000 |
| 24LC128 Serial EEPROM | I2C1 | 1010001 |
| Table 4. PIC I2C Peripheral Address Map. |
| Flash Pin | PIC Port |
|---|---|
| CS | RB10 |
| SCLK | RB11 |
| SI | RB12 |
| SO | RB13 |
| WP | RB14 |
| HOLD | RB15 |
| Table 5. PIC Flash Connections. |
Built-in on-board I/O includes four LEDs and six buttons. Four of the buttons are general-purpose and two are set aside for special functions. The red special function buttons are reserved for use as an on-chip reset (BTN4 - RESET) to reset the design logic and a configuration reset (BTN5 – PROG) which initiates a new FPGA configuration sequence like that which occurs at power-on. It is important to note that the buttons and LEDs are not all constrained to the same IOSTANDARD on their associated ports, since they are connected to otherwise un-allocated ports in different FPGA IO banks. Please refer to Appendix B for specific details regarding the button and LED IO port constraints.
The NetFPGA-1G-CML has two 12-pin connectors to support I/O expansion via Digilent Pmods. Digilent manufactures Pmod accessories that support a large variety of external interfaces that increase system flexibility. The Pmod connectors are 2x6 right-angle 100-mil female connectors that work with the standard 2x6 headers available from a variety of distributors. On the NetFPGA-1G-CML, each 12-pin Pmod connector provides two 3.3V VCC supply connections (pins 6 and 12), two Ground connections (pins 5 and 11), and eight logic signals (Fig. 2). The supply pins can provide up to 1A of current to connected Pmod devices. The logic signals are not matched pairs. They are routed without impedance control or delay matching. Note also that the connectors are not keyed, so care should be taken to verify that any connected devices have Pin 1 aligned with Pin 1 on the connector. Pin1, VCC and GND are clearly labeled on the PCB to help simplify proper connection.
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| Figure 2. Pmod Connectors, End View. |
The NetFPGA-1G-CML includes a VITA-57 compatible FMC (FPGA Mezzanine Card) carrier connector. A High Pin Count (HPC) connector is used to provide the maximum possible compatibility with a variety of commercially available mezzanine cards. Select I/O ports on the XC7K325T are connected to all of the standard Low Pin Count (LPC) signals on the connector, but only 22 of the HPC signals are supported due to the limitations of the FF676 package. Up to four differential send/receive pairs for GTX transceivers are also supported.
The FMC interface signals are driven by two Select I/O banks within the FPGA. Signal drive voltages within these banks are configured together to match the various requirements of different mezzanine cards. These banks are disabled on the board when shipped, but jumper JP5 (VADJ ENABLE) can be installed to prepare these I/O banks for use with the FMC connector. Three control outputs are then included in the FPGA design configuration to set the FMC signaling voltage and enable it. Those signals are VADJ_EN, SET_VADJ1, SET VADJ2, and are set according to Table 2. Keep in mind that the IOSTANDARD required by the pin constraints associated with the FMC interface will depend upon the VADJ selected, and that these VADJ programming signals should be set to constants within the design.
Please refer to the American National Standards Institute ANSI/VITA 57.1 FPGA Mezzanine Card (FMC) Standard for additional detail regarding standard FMC module and carrier requirements. Refer to Appendix B for specific I/O constraints relating FPGA pins to their associated FMC control and connector pins.
Figure 3 shows the signals that are connected on the FMC connector using the FMC standard signal names. No signals in the shaded areas are connected except for the GNDs.
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| Figure 3. FMC Signal Population |