RLDRAM Test Manual
This manual describes how to set up the NetFPGA-10G board and run the included RLDRAM Test. This test verifies that the on-board reduced-latency DRAM ICs and FPGA interface are working correctly. You should run the RLDRAM Test and the Production Test before attempting any development with NetFPGA-10G. If either test indicates a problem with your board, please return it immediately to HiTech Global (HTG).
The RLDRAM Test is performed by the NetFPGA-10G’s Virtex5 FPGA. The FPGA design stresses the RLDRAM interface, writing and reading a test sequence at 100% utilization with a clock frequency of 200MHz. The status of the tests can be read back serially using the UART. A bitstream containing the RLDRAM Test FPGA design is provided in the NetFPGA-10G github repository in the projects/production_test/ subdirectory.
Although the description below describes standalone operation, this test can also be run in server mode.
In order to download bitstreams to the FPGA and CPLD devices on the NetFPGA-10G board, you will need to install the Xilinx ISE software and the associated JTAG programming cable drivers. ISE can be downloaded from Xilinx's Download site at www.xilinx.com/support/downloads. Installation instructions for supported Windows and Linux platforms can be found at Xilinx's Product Support & Documentation site, www.xilinx.com/support.
The following items are required to conduct the test:
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NetFPGA-10G board – revision 4 or higher
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RLDRAM Test bitstream – stored in the projects/production_test/ subdirectory of the NetFPGA-10G git repository
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ATX PC power supply (or equivalent)
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Xilinx JTAG programming cable
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An RS232 serial (null-modem) cable
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Serial Terminal Emulation software to communicate with the NetFPGA-10G board over the RS232 interface:
For Windows, there are a number of freely-available Terminal Emulators, including PuTTY. On Linux, use minicom. Fedora's built-in package manager should allow you to install minicom from the GUI using Add/Remove Software. If not, RPMs for minicom (and lrzsz, on which it depends) can be found at pkgs.org.
Before running the RLDRAM Test, follow these steps to set up your board:
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Place the board on a flat surface and disconnect all attached connections.
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Ensure Jumper J16 is not populated. This jumper is located at the top left corner of the board, underneath the RS232 DB-9 connector, as shown below.
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Set switch SW9 to _ATX _to power the board from an external supply. Make sure the switch is set fully in the _ATX _position as shown below.
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Ensure the DIP switches SW1, SW3, _SW6 _and _SW10 _are set correctly, matching the figure below.
SW1: SEL0, SEL1, M2, M1, M0, N2, N1, N0 are set to off, off, off, on, on, on, off, off
SW6: SEL0, SEL1, M2, M1, M0, N2, N1, N0 are set to off, off, off, on, off on, off, on
SW3: M0, M1, M2 is set to on, on, on
SW10: SEL0, SEL1, SEL2 are set to on, off, off
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Connect an ATX power cable to the ATX supply connector on the NetFPGA-10G board.
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Connect an RS232 serial cable to the RS232 port on the NetFPGA-10G board. Connect the other end to your PC's COM (Serial) port, or to a suitable adapter.
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Connect a Xilinx JTAG programming cable to the JTAG connector on the NetFPGA-10G board. Connect the programming cable's USB or parallel port cable to the computer which will be used to program the on-board devices.
Your board is now ready for testing and should be connected as shown in the diagram below.
To run the RLDRAM Test, follow these steps:
- Apply power to the board and use the POWER LEDs to check the board's power rails. All power LEDs should be illuminated steadily and equally as shown below.
2. Start Xilinx iMPACT. If necessary, create a new project. Connect to the JTAG programming cable. You should see the Virtex5 FPGA and the CPLD on the programming cable's JTAG chain, as shown below.
Program the FPGA with the bitstream located at production_test/bitfiles/rldram.bit. iMPACT may ask for attaching a PROM device, select 'no'. Programming the device takes a few seconds. (For instructions on how to install and configure the Xilinx software tools and a driver for the JTAG programming cable, please refer to "Xilinx Software Installation" earlier in this document.)
3. Start a serial terminal session on the PC using PuTTY, _minicom _or equivalent. Connect to the NetFPGA-10G board at 9600bps with 8 data bits, no parity bit, 1 stop bit and no flow control.
4. Check your serial terminal window. After a few seconds, your serial terminal should look something like this:
The screenshot above shows the results of the RLDRAM test. You should see the test result "redraw" periodically. The correct test result is 0xFF5A, as shown.
The RLDRAM Test project page describes in detail how the test exercises the RLDRAM components and provides a list of result codes for the RLDRAMII tests.
Before starting any development on the NetFPGA-10G platform, you should ensure both the Production Test and RLDRAM Test run successfully.