Switch Output Port Lookup

Name

nf10_switch_output_port_lookup

Version

v1.00a (Register based)

v1.10a (CAM based)

Author

Gianni Anitchi (gianni.antichi_at_iet.unipi.it)

Muhammad Shahbaz (muhammad.shahbaz_at_cl.cam.ac.uk)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/std/pcores/nf10_switch_output_port_lookup_v1_10_a/

Interface Types

AXI4-Stream

AXI4-Lite

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width

M_AXIS: Master AXI4-Stream bus, Variable width

S_AXI: Slave AXI4-Lite

Parameters

C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_USER_WIDTH: Data width of the TUSER field.

C_AXI_DATA_WIDTH: Data width of the AXI4-Lite bus.

C_BASEADDR: Base address value of the core.

C_HIGHADDR: High address value of the core.

Register map

0x0: number of hits

0x1: number of misses

Description

For information on Learning CAM Switch visit, http://netfpga.org.