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proper support for Verilog line directive #90
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I understand that the 2 first bullets are working together. But your last bullet seems to be an alternative proposition. Which is not very clear to me: |
I would like to create a list of <line in preprocessed str, original file, original line> from line directives somehow. Then each time the position is required I would use this list to resolve correct original file and original line. |
Maybe we probably do not need the line directives in preprocessed string, but we need some sort of map which keeps the info about orig. file. This info is actually an argument of line directive. |
Well, it is sometime use full to dump prepossessed code. |
@Thomasb81, yes. Let's make it configurable. In pure preprocessor we would like to put Also maybe we would need something more powerful than just list, because of thinks like |
It is possible that I will be able to implement this feature this weekend is anyone working on this? |
It seems that this functionality is connected with intensive code removal and refactoring, I will do it during weekend. |
Now 8c519e4 the preprocessor exports correct file/line map for input string. This map is available in https://github.com/Nic30/hdlConvertor/blob/verilog_pp_line_directive/src/convertor.cpp#L139 verilog_pp::VerilogPreprocOutBuffer but it is not currently used. Next step is to use this map when resolving position of the object or error. |
As mention in #166 with #191, this structure is inaccurate. We probably need data structure that allow to reference a line interval and attach a property. Later we can split the preprocessor result and parse the different piece with different properties. |
Why have we remove the usage of The initial idea in mind was to annotate each token to have the possibility to keep fine grain the origin of each token, from preprocessor up to SV parser. By only keeping track of line I think you can't identify that original source code is behind a macro... |
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Currently
line
directive is used only by preprocessor. Preprocessor builds a large string from all the input files and this string is an input of the parser.Problem is that the original code positions are usually lost because preprocessor does not set
line
directive and Verilog parser ignores it.Solution:
line
directive https://github.com/Nic30/hdlConvertor/blob/master/src/verilogPreproc/verilogPreprocContainer.cpp#L90.line
directives to SystemVerilog grammar https://github.com/Nic30/hdlConvertor/blob/master/grammars/sv2017Lexer.g4 https://github.com/Nic30/hdlConvertor/blob/master/grammars/sv2017Parser.g4SVParserContext
which will contain commentParser and actual file and offset which will be used for all positions of objects and all exceptions.The text was updated successfully, but these errors were encountered: