From 8063d1d019cf5dbbe1e2cce818c86105b092cc09 Mon Sep 17 00:00:00 2001 From: optical Date: Wed, 27 Jan 2021 16:15:16 +0100 Subject: [PATCH] Crc: Fixed test to use latest value from simulation --- hwtLib/logic/crcComb.py | 2 +- hwtLib/logic/crcComb_test.py | 19 ++++++++++--------- 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/hwtLib/logic/crcComb.py b/hwtLib/logic/crcComb.py index 2aafc56c..25d4abe9 100644 --- a/hwtLib/logic/crcComb.py +++ b/hwtLib/logic/crcComb.py @@ -48,7 +48,7 @@ class CrcComb(Unit): def _config(self): self.DATA_WIDTH = Param(7 + 4) self.IN_IS_BIGENDIAN = Param(False) - self.PIPELINE_AGG = Param(32) + self.PIPELINE_AGG = Param(2) self.setConfig(CRC_5_USB) def setConfig(self, crcConfigCls): diff --git a/hwtLib/logic/crcComb_test.py b/hwtLib/logic/crcComb_test.py index b3cbc5ce..6167b183 100644 --- a/hwtLib/logic/crcComb_test.py +++ b/hwtLib/logic/crcComb_test.py @@ -95,7 +95,7 @@ def test_crc1(self): inp = b"a" u.dataIn._ag.data.append(stoi(inp)) - self.runSim(20 * Time.ns) + self.runSim(40 * Time.ns) crc = 1 out = int(u.dataOut._ag.data[-1]) @@ -107,10 +107,11 @@ def test_crc8(self): inp = b"a" u.dataIn._ag.data.append(stoi(inp)) - self.runSim(20 * Time.ns) + self.runSim(40 * Time.ns) crc = 0x20 - self.assertValSequenceEqual(u.dataOut._ag.data, [crc]) + out = int(u.dataOut._ag.data[-1]) + self.assertEqual(out, crc, "0x{:x} 0x{:x}".format(crc, out)) def test_crc32_py(self): self.assertEqual(crc32(b"aa"), crc32(b"a", crc32(b"a"))) @@ -188,7 +189,7 @@ def test_crc32(self): u.dataIn._ag.data.append( stoi(inp), ) - self.runSim(20 * Time.ns, name=os.path.join(self.DEFAULT_LOG_DIR, + self.runSim(100 * Time.ns, name=os.path.join(self.DEFAULT_LOG_DIR, f"test_crc32_{i:d}.vcd")) out = int(u.dataOut._ag.data[-1]) ref = crc32(inp) & mask(32) @@ -198,7 +199,7 @@ def test_crc32_64b(self): inp = b"abcdefgh" u = self.setUpCrc(CRC_32, dataWidth=64) u.dataIn._ag.data.append(stoi(inp)) - self.runSim(20 * Time.ns) + self.runSim(100 * Time.ns) out = int(u.dataOut._ag.data[-1]) ref = crc32(inp) & 0xffffffff self.assertEqual(out, ref, f"0x{out:08X} 0x{ref:08X}") @@ -209,12 +210,12 @@ def test_crc16(self): u = self.u u.dataIn._ag.data.append(stoi(inp)) - self.runSim(20 * Time.ns, name=os.path.join(self.DEFAULT_LOG_DIR, + self.runSim(100 * Time.ns, name=os.path.join(self.DEFAULT_LOG_DIR, f"test_crc16_{i:d}.vcd")) # crc = 0x449C ref = crc_hqx(inp, CRC_16_CCITT.INIT) - d = u.dataOut._ag.data[0] + d = u.dataOut._ag.data[-1] self.assertValEqual(d, ref, (inp, "0x{:x} 0x{:x}".format(int(d), ref))) def test_crc5_usb(self): @@ -241,9 +242,9 @@ def lsb_first_to_msb_first(val): u.dataIn._ag.data.append(inp) trace_file = os.path.join(self.DEFAULT_LOG_DIR, f"test_crc5_usb_{i:d}.vcd") - self.runSim(20 * Time.ns, name=trace_file) + self.runSim(100 * Time.ns, name=trace_file) - d = u.dataOut._ag.data[0] + d = u.dataOut._ag.data[-1] _d = int(d) self.assertValEqual(d, ref, (i, f"{_d:05b} {ref:05b}"))