stats.txt

---------- Begin Simulation Statistics ----------
final_tick                                64954738500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
host_inst_rate                                 242338                       # Simulator instruction rate (inst/s)
host_mem_usage                                 691608                       # Number of bytes of host memory used
host_op_rate                                   265195                       # Simulator op (including micro ops) rate (op/s)
host_seconds                                   412.65                       # Real time elapsed on the host
host_tick_rate                              157409724                       # Simulator tick rate (ticks/s)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
sim_insts                                   100000001                       # Number of instructions simulated
sim_ops                                     109431937                       # Number of ops (including micro ops) simulated
sim_seconds                                  0.064955                       # Number of seconds simulated
sim_ticks                                 64954738500                       # Number of ticks simulated
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             88.088148                       # BTB Hit Percentage
system.cpu.branchPred.BTBHits                 8691529                       # Number of BTB hits
system.cpu.branchPred.BTBLookups              9866854                       # Number of BTB lookups
system.cpu.branchPred.RASInCorrect                345                       # Number of incorrect RAS predictions.
system.cpu.branchPred.condIncorrect            142503                       # Number of conditional branches incorrect
system.cpu.branchPred.condPredicted          16342529                       # Number of conditional branches predicted
system.cpu.branchPred.indirectHits             300025                       # Number of indirect target hits.
system.cpu.branchPred.indirectLookups          434104                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectMisses           134079                       # Number of indirect misses.
system.cpu.branchPred.lookups                20405395                       # Number of BP lookups
system.cpu.branchPred.usedRAS                 1050672                       # Number of times the RAS was used to get a target.
system.cpu.branchPredindirectMispredicted         1038                       # Number of mispredicted indirect branches.
system.cpu.committedInsts                   100000001                       # Number of instructions committed
system.cpu.committedOps                     109431937                       # Number of ops (including micro ops) committed
system.cpu.cpi                               1.299095                       # CPI: cycles per instruction
system.cpu.discardedOps                        690949                       # Number of ops (including micro ops) which were discarded before commit
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.stage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.stage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dtb.stage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.fetch2.amo_instructions                  0                       # Number of memory atomic instructions successfully decoded
system.cpu.fetch2.fp_instructions                   0                       # Number of floating point instructions successfully decoded
system.cpu.fetch2.int_instructions           49596732                       # Number of integer instructions successfully decoded
system.cpu.fetch2.load_instructions          17142165                       # Number of memory load instructions successfully decoded
system.cpu.fetch2.store_instructions          9894427                       # Number of memory store instructions successfully decoded
system.cpu.fetch2.vec_instructions                  0                       # Number of SIMD instructions successfully decoded
system.cpu.idleCycles                        13496912                       # Total number of cycles that the object has spent stopped
system.cpu.ipc                               0.769767                       # IPC: instructions per cycle
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.stage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.stage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.stage2_mmu.stage2_tlb.hits            0                       # DTB hits
system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.itb.stage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.itb.stage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.itb.stage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.itb.stage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.itb.stage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.numCycles                        129909477                       # number of cpu cycles simulated
system.cpu.numFetchSuspends                         0                       # Number of times Execute suspended instruction fetching
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.op_class_0::No_OpClass                   0      0.00%      0.00% # Class of committed instruction
system.cpu.op_class_0::IntAlu                72955303     66.67%     66.67% # Class of committed instruction
system.cpu.op_class_0::IntMult                 568365      0.52%     67.19% # Class of committed instruction
system.cpu.op_class_0::IntDiv                       0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatAdd                     0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatCmp                     0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatCvt                     0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatMult                    0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatMultAcc                 0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatDiv                     0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatMisc                    0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::FloatSqrt                    0      0.00%     67.19% # Class of committed instruction
system.cpu.op_class_0::SimdAdd                 241252      0.22%     67.41% # Class of committed instruction
system.cpu.op_class_0::SimdAddAcc                   0      0.00%     67.41% # Class of committed instruction
system.cpu.op_class_0::SimdAlu                 154720      0.14%     67.55% # Class of committed instruction
system.cpu.op_class_0::SimdCmp                 120626      0.11%     67.66% # Class of committed instruction
system.cpu.op_class_0::SimdCvt                      0      0.00%     67.66% # Class of committed instruction
system.cpu.op_class_0::SimdMisc                 44544      0.04%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdMult                     0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdMultAcc                  0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdShift                    0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdShiftAcc                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdDiv                      0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdSqrt                     0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAdd                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatAlu                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCmp                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatCvt                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatDiv                 0      0.00%     67.70% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMisc           166465      0.15%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMult                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdFloatMultAcc             0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdFloatSqrt                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdReduceAdd                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdReduceAlu                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdReduceCmp                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdFloatReduceAdd            0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdFloatReduceCmp            0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdAes                      0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdAesMix                   0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdSha1Hash                 0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdSha1Hash2                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdSha256Hash               0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdSha256Hash2              0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdShaSigma2                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdShaSigma3                0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::SimdPredAlu                  0      0.00%     67.85% # Class of committed instruction
system.cpu.op_class_0::MemRead               20646465     18.87%     86.72% # Class of committed instruction
system.cpu.op_class_0::MemWrite              14534197     13.28%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemRead                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::FloatMemWrite                0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::IprAccess                    0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::InstPrefetch                 0      0.00%    100.00% # Class of committed instruction
system.cpu.op_class_0::total                109431937                       # Class of committed instruction
system.cpu.tickCycles                       116412565                       # Number of cycles that the object actually ticked
system.cpu.workload.numSyscalls                    86                       # Number of system calls
system.membus.snoop_filter.hit_multi_requests            0                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_multi_snoops            0                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.membus.snoop_filter.hit_single_requests         6709                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.hit_single_snoops            0                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.membus.snoop_filter.tot_requests         46577                       # Total number of requests made to the snoop filter.
system.membus.snoop_filter.tot_snoops               0                       # Total number of snoops made to the snoop filter.
system.tol2bus.snoop_filter.hit_multi_requests           29                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.tol2bus.snoop_filter.hit_multi_snoops            2                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.tol2bus.snoop_filter.hit_single_requests       722971                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.tol2bus.snoop_filter.hit_single_snoops          397                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.tol2bus.snoop_filter.tot_requests      1447357                       # Total number of requests made to the snoop filter.
system.tol2bus.snoop_filter.tot_snoops            399                       # Total number of snoops made to the snoop filter.
system.membus.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.membus.trans_dist::ReadResp               1057                       # Transaction distribution
system.membus.trans_dist::WritebackDirty         6536                       # Transaction distribution
system.membus.trans_dist::CleanEvict              172                       # Transaction distribution
system.membus.trans_dist::ReadExReq             38812                       # Transaction distribution
system.membus.trans_dist::ReadExResp            38812                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq          1057                       # Transaction distribution
system.membus.pkt_count_system.l2.mem_side::system.mem_ctrls.port        86446                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  86446                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.l2.mem_side::system.mem_ctrls.port      2969920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                 2969920                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoopTraffic                          0                       # Total snoop traffic (bytes)
system.membus.snoop_fanout::samples             39869                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   39869    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               39869                       # Request fanout histogram
system.membus.respLayer1.occupancy          212517500                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.3                       # Layer utilization (%)
system.membus.reqLayer0.occupancy            81422500                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.1                       # Layer utilization (%)
system.tol2bus.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.tol2bus.trans_dist::ReadResp            685454                       # Transaction distribution
system.tol2bus.trans_dist::WritebackDirty        57060                       # Transaction distribution
system.tol2bus.trans_dist::WritebackClean       668515                       # Transaction distribution
system.tol2bus.trans_dist::CleanEvict            4497                       # Transaction distribution
system.tol2bus.trans_dist::ReadExReq            38935                       # Transaction distribution
system.tol2bus.trans_dist::ReadExResp           38935                       # Transaction distribution
system.tol2bus.trans_dist::ReadCleanReq        668914                       # Transaction distribution
system.tol2bus.trans_dist::ReadSharedReq        16541                       # Transaction distribution
system.tol2bus.pkt_count_system.cpu.icache.mem_side::system.l2.cpu_side      2006342                       # Packet count per connected master and slave (bytes)
system.tol2bus.pkt_count_system.cpu.dcache.mem_side::system.l2.cpu_side       165404                       # Packet count per connected master and slave (bytes)
system.tol2bus.pkt_count::total               2171746                       # Packet count per connected master and slave (bytes)
system.tol2bus.pkt_size_system.cpu.icache.mem_side::system.l2.cpu_side     85595392                       # Cumulative packet size per connected master and slave (bytes)
system.tol2bus.pkt_size_system.cpu.dcache.mem_side::system.l2.cpu_side      6784000                       # Cumulative packet size per connected master and slave (bytes)
system.tol2bus.pkt_size::total               92379392                       # Cumulative packet size per connected master and slave (bytes)
system.tol2bus.snoops                            7105                       # Total snoops (count)
system.tol2bus.snoopTraffic                    418304                       # Total snoop traffic (bytes)
system.tol2bus.snoop_fanout::samples           731495                       # Request fanout histogram
system.tol2bus.snoop_fanout::mean            0.000593                       # Request fanout histogram
system.tol2bus.snoop_fanout::stdev           0.024463                       # Request fanout histogram
system.tol2bus.snoop_fanout::underflows             0      0.00%      0.00% # Request fanout histogram
system.tol2bus.snoop_fanout::0                 731063     99.94%     99.94% # Request fanout histogram
system.tol2bus.snoop_fanout::1                    430      0.06%    100.00% # Request fanout histogram
system.tol2bus.snoop_fanout::2                      2      0.00%    100.00% # Request fanout histogram
system.tol2bus.snoop_fanout::overflows              0      0.00%    100.00% # Request fanout histogram
system.tol2bus.snoop_fanout::min_value              0                       # Request fanout histogram
system.tol2bus.snoop_fanout::max_value              2                       # Request fanout histogram
system.tol2bus.snoop_fanout::total             731495                       # Request fanout histogram
system.tol2bus.reqLayer0.occupancy         1442717500                       # Layer occupancy (ticks)
system.tol2bus.reqLayer0.utilization              2.2                       # Layer utilization (%)
system.tol2bus.respLayer1.occupancy          83216495                       # Layer occupancy (ticks)
system.tol2bus.respLayer1.utilization             0.1                       # Layer utilization (%)
system.tol2bus.respLayer0.occupancy        1003369999                       # Layer occupancy (ticks)
system.tol2bus.respLayer0.utilization             1.5                       # Layer utilization (%)
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.l2.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.l2.demand_hits::.cpu.inst               668401                       # number of demand (read+write) hits
system.l2.demand_hits::.cpu.data                16114                       # number of demand (read+write) hits
system.l2.demand_hits::total                   684515                       # number of demand (read+write) hits
system.l2.overall_hits::.cpu.inst              668401                       # number of overall hits
system.l2.overall_hits::.cpu.data               16114                       # number of overall hits
system.l2.overall_hits::total                  684515                       # number of overall hits
system.l2.demand_misses::.cpu.inst                513                       # number of demand (read+write) misses
system.l2.demand_misses::.cpu.data              39362                       # number of demand (read+write) misses
system.l2.demand_misses::total                  39875                       # number of demand (read+write) misses
system.l2.overall_misses::.cpu.inst               513                       # number of overall misses
system.l2.overall_misses::.cpu.data             39362                       # number of overall misses
system.l2.overall_misses::total                 39875                       # number of overall misses
system.l2.demand_miss_latency::.cpu.inst     39178000                       # number of demand (read+write) miss cycles
system.l2.demand_miss_latency::.cpu.data   3216079500                       # number of demand (read+write) miss cycles
system.l2.demand_miss_latency::total       3255257500                       # number of demand (read+write) miss cycles
system.l2.overall_miss_latency::.cpu.inst     39178000                       # number of overall miss cycles
system.l2.overall_miss_latency::.cpu.data   3216079500                       # number of overall miss cycles
system.l2.overall_miss_latency::total      3255257500                       # number of overall miss cycles
system.l2.demand_accesses::.cpu.inst           668914                       # number of demand (read+write) accesses
system.l2.demand_accesses::.cpu.data            55476                       # number of demand (read+write) accesses
system.l2.demand_accesses::total               724390                       # number of demand (read+write) accesses
system.l2.overall_accesses::.cpu.inst          668914                       # number of overall (read+write) accesses
system.l2.overall_accesses::.cpu.data           55476                       # number of overall (read+write) accesses
system.l2.overall_accesses::total              724390                       # number of overall (read+write) accesses
system.l2.demand_miss_rate::.cpu.inst        0.000767                       # miss rate for demand accesses
system.l2.demand_miss_rate::.cpu.data        0.709532                       # miss rate for demand accesses
system.l2.demand_miss_rate::total            0.055046                       # miss rate for demand accesses
system.l2.overall_miss_rate::.cpu.inst       0.000767                       # miss rate for overall accesses
system.l2.overall_miss_rate::.cpu.data       0.709532                       # miss rate for overall accesses
system.l2.overall_miss_rate::total           0.055046                       # miss rate for overall accesses
system.l2.demand_avg_miss_latency::.cpu.inst 76370.370370                       # average overall miss latency
system.l2.demand_avg_miss_latency::.cpu.data 81705.185204                       # average overall miss latency
system.l2.demand_avg_miss_latency::total 81636.551724                       # average overall miss latency
system.l2.overall_avg_miss_latency::.cpu.inst 76370.370370                       # average overall miss latency
system.l2.overall_avg_miss_latency::.cpu.data 81705.185204                       # average overall miss latency
system.l2.overall_avg_miss_latency::total 81636.551724                       # average overall miss latency
system.l2.blocked_cycles::no_mshrs                  0                       # number of cycles access was blocked
system.l2.blocked_cycles::no_targets                0                       # number of cycles access was blocked
system.l2.blocked::no_mshrs                         0                       # number of cycles access was blocked
system.l2.blocked::no_targets                       0                       # number of cycles access was blocked
system.l2.avg_blocked_cycles::no_mshrs            nan                       # average number of cycles each access was blocked
system.l2.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.l2.writebacks::.writebacks                6536                       # number of writebacks
system.l2.writebacks::total                      6536                       # number of writebacks
system.l2.demand_mshr_hits::.cpu.inst               1                       # number of demand (read+write) MSHR hits
system.l2.demand_mshr_hits::.cpu.data               5                       # number of demand (read+write) MSHR hits
system.l2.demand_mshr_hits::total                   6                       # number of demand (read+write) MSHR hits
system.l2.overall_mshr_hits::.cpu.inst              1                       # number of overall MSHR hits
system.l2.overall_mshr_hits::.cpu.data              5                       # number of overall MSHR hits
system.l2.overall_mshr_hits::total                  6                       # number of overall MSHR hits
system.l2.demand_mshr_misses::.cpu.inst           512                       # number of demand (read+write) MSHR misses
system.l2.demand_mshr_misses::.cpu.data         39357                       # number of demand (read+write) MSHR misses
system.l2.demand_mshr_misses::total             39869                       # number of demand (read+write) MSHR misses
system.l2.overall_mshr_misses::.cpu.inst          512                       # number of overall MSHR misses
system.l2.overall_mshr_misses::.cpu.data        39357                       # number of overall MSHR misses
system.l2.overall_mshr_misses::total            39869                       # number of overall MSHR misses
system.l2.demand_mshr_miss_latency::.cpu.inst     33993500                       # number of demand (read+write) MSHR miss cycles
system.l2.demand_mshr_miss_latency::.cpu.data   2822182500                       # number of demand (read+write) MSHR miss cycles
system.l2.demand_mshr_miss_latency::total   2856176000                       # number of demand (read+write) MSHR miss cycles
system.l2.overall_mshr_miss_latency::.cpu.inst     33993500                       # number of overall MSHR miss cycles
system.l2.overall_mshr_miss_latency::.cpu.data   2822182500                       # number of overall MSHR miss cycles
system.l2.overall_mshr_miss_latency::total   2856176000                       # number of overall MSHR miss cycles
system.l2.demand_mshr_miss_rate::.cpu.inst     0.000765                       # mshr miss rate for demand accesses
system.l2.demand_mshr_miss_rate::.cpu.data     0.709442                       # mshr miss rate for demand accesses
system.l2.demand_mshr_miss_rate::total       0.055038                       # mshr miss rate for demand accesses
system.l2.overall_mshr_miss_rate::.cpu.inst     0.000765                       # mshr miss rate for overall accesses
system.l2.overall_mshr_miss_rate::.cpu.data     0.709442                       # mshr miss rate for overall accesses
system.l2.overall_mshr_miss_rate::total      0.055038                       # mshr miss rate for overall accesses
system.l2.demand_avg_mshr_miss_latency::.cpu.inst 66393.554688                       # average overall mshr miss latency
system.l2.demand_avg_mshr_miss_latency::.cpu.data 71707.256651                       # average overall mshr miss latency
system.l2.demand_avg_mshr_miss_latency::total 71639.017783                       # average overall mshr miss latency
system.l2.overall_avg_mshr_miss_latency::.cpu.inst 66393.554688                       # average overall mshr miss latency
system.l2.overall_avg_mshr_miss_latency::.cpu.data 71707.256651                       # average overall mshr miss latency
system.l2.overall_avg_mshr_miss_latency::total 71639.017783                       # average overall mshr miss latency
system.l2.replacements                           7105                       # number of replacements
system.l2.WritebackDirty_hits::.writebacks        50524                       # number of WritebackDirty hits
system.l2.WritebackDirty_hits::total            50524                       # number of WritebackDirty hits
system.l2.WritebackDirty_accesses::.writebacks        50524                       # number of WritebackDirty accesses(hits+misses)
system.l2.WritebackDirty_accesses::total        50524                       # number of WritebackDirty accesses(hits+misses)
system.l2.WritebackClean_hits::.writebacks       668504                       # number of WritebackClean hits
system.l2.WritebackClean_hits::total           668504                       # number of WritebackClean hits
system.l2.WritebackClean_accesses::.writebacks       668504                       # number of WritebackClean accesses(hits+misses)
system.l2.WritebackClean_accesses::total       668504                       # number of WritebackClean accesses(hits+misses)
system.l2.CleanEvict_mshr_misses::.writebacks            2                       # number of CleanEvict MSHR misses
system.l2.CleanEvict_mshr_misses::total             2                       # number of CleanEvict MSHR misses
system.l2.CleanEvict_mshr_miss_rate::.writebacks          inf                       # mshr miss rate for CleanEvict accesses
system.l2.CleanEvict_mshr_miss_rate::total          inf                       # mshr miss rate for CleanEvict accesses
system.l2.ReadExReq_hits::.cpu.data               123                       # number of ReadExReq hits
system.l2.ReadExReq_hits::total                   123                       # number of ReadExReq hits
system.l2.ReadExReq_misses::.cpu.data           38812                       # number of ReadExReq misses
system.l2.ReadExReq_misses::total               38812                       # number of ReadExReq misses
system.l2.ReadExReq_miss_latency::.cpu.data   3168227500                       # number of ReadExReq miss cycles
system.l2.ReadExReq_miss_latency::total    3168227500                       # number of ReadExReq miss cycles
system.l2.ReadExReq_accesses::.cpu.data         38935                       # number of ReadExReq accesses(hits+misses)
system.l2.ReadExReq_accesses::total             38935                       # number of ReadExReq accesses(hits+misses)
system.l2.ReadExReq_miss_rate::.cpu.data     0.996841                       # miss rate for ReadExReq accesses
system.l2.ReadExReq_miss_rate::total         0.996841                       # miss rate for ReadExReq accesses
system.l2.ReadExReq_avg_miss_latency::.cpu.data 81630.101515                       # average ReadExReq miss latency
system.l2.ReadExReq_avg_miss_latency::total 81630.101515                       # average ReadExReq miss latency
system.l2.ReadExReq_mshr_misses::.cpu.data        38812                       # number of ReadExReq MSHR misses
system.l2.ReadExReq_mshr_misses::total          38812                       # number of ReadExReq MSHR misses
system.l2.ReadExReq_mshr_miss_latency::.cpu.data   2780107500                       # number of ReadExReq MSHR miss cycles
system.l2.ReadExReq_mshr_miss_latency::total   2780107500                       # number of ReadExReq MSHR miss cycles
system.l2.ReadExReq_mshr_miss_rate::.cpu.data     0.996841                       # mshr miss rate for ReadExReq accesses
system.l2.ReadExReq_mshr_miss_rate::total     0.996841                       # mshr miss rate for ReadExReq accesses
system.l2.ReadExReq_avg_mshr_miss_latency::.cpu.data 71630.101515                       # average ReadExReq mshr miss latency
system.l2.ReadExReq_avg_mshr_miss_latency::total 71630.101515                       # average ReadExReq mshr miss latency
system.l2.ReadCleanReq_hits::.cpu.inst         668401                       # number of ReadCleanReq hits
system.l2.ReadCleanReq_hits::total             668401                       # number of ReadCleanReq hits
system.l2.ReadCleanReq_misses::.cpu.inst          513                       # number of ReadCleanReq misses
system.l2.ReadCleanReq_misses::total              513                       # number of ReadCleanReq misses
system.l2.ReadCleanReq_miss_latency::.cpu.inst     39178000                       # number of ReadCleanReq miss cycles
system.l2.ReadCleanReq_miss_latency::total     39178000                       # number of ReadCleanReq miss cycles
system.l2.ReadCleanReq_accesses::.cpu.inst       668914                       # number of ReadCleanReq accesses(hits+misses)
system.l2.ReadCleanReq_accesses::total         668914                       # number of ReadCleanReq accesses(hits+misses)
system.l2.ReadCleanReq_miss_rate::.cpu.inst     0.000767                       # miss rate for ReadCleanReq accesses
system.l2.ReadCleanReq_miss_rate::total      0.000767                       # miss rate for ReadCleanReq accesses
system.l2.ReadCleanReq_avg_miss_latency::.cpu.inst 76370.370370                       # average ReadCleanReq miss latency
system.l2.ReadCleanReq_avg_miss_latency::total 76370.370370                       # average ReadCleanReq miss latency
system.l2.ReadCleanReq_mshr_hits::.cpu.inst            1                       # number of ReadCleanReq MSHR hits
system.l2.ReadCleanReq_mshr_hits::total             1                       # number of ReadCleanReq MSHR hits
system.l2.ReadCleanReq_mshr_misses::.cpu.inst          512                       # number of ReadCleanReq MSHR misses
system.l2.ReadCleanReq_mshr_misses::total          512                       # number of ReadCleanReq MSHR misses
system.l2.ReadCleanReq_mshr_miss_latency::.cpu.inst     33993500                       # number of ReadCleanReq MSHR miss cycles
system.l2.ReadCleanReq_mshr_miss_latency::total     33993500                       # number of ReadCleanReq MSHR miss cycles
system.l2.ReadCleanReq_mshr_miss_rate::.cpu.inst     0.000765                       # mshr miss rate for ReadCleanReq accesses
system.l2.ReadCleanReq_mshr_miss_rate::total     0.000765                       # mshr miss rate for ReadCleanReq accesses
system.l2.ReadCleanReq_avg_mshr_miss_latency::.cpu.inst 66393.554688                       # average ReadCleanReq mshr miss latency
system.l2.ReadCleanReq_avg_mshr_miss_latency::total 66393.554688                       # average ReadCleanReq mshr miss latency
system.l2.ReadSharedReq_hits::.cpu.data         15991                       # number of ReadSharedReq hits
system.l2.ReadSharedReq_hits::total             15991                       # number of ReadSharedReq hits
system.l2.ReadSharedReq_misses::.cpu.data          550                       # number of ReadSharedReq misses
system.l2.ReadSharedReq_misses::total             550                       # number of ReadSharedReq misses
system.l2.ReadSharedReq_miss_latency::.cpu.data     47852000                       # number of ReadSharedReq miss cycles
system.l2.ReadSharedReq_miss_latency::total     47852000                       # number of ReadSharedReq miss cycles
system.l2.ReadSharedReq_accesses::.cpu.data        16541                       # number of ReadSharedReq accesses(hits+misses)
system.l2.ReadSharedReq_accesses::total         16541                       # number of ReadSharedReq accesses(hits+misses)
system.l2.ReadSharedReq_miss_rate::.cpu.data     0.033251                       # miss rate for ReadSharedReq accesses
system.l2.ReadSharedReq_miss_rate::total     0.033251                       # miss rate for ReadSharedReq accesses
system.l2.ReadSharedReq_avg_miss_latency::.cpu.data 87003.636364                       # average ReadSharedReq miss latency
system.l2.ReadSharedReq_avg_miss_latency::total 87003.636364                       # average ReadSharedReq miss latency
system.l2.ReadSharedReq_mshr_hits::.cpu.data            5                       # number of ReadSharedReq MSHR hits
system.l2.ReadSharedReq_mshr_hits::total            5                       # number of ReadSharedReq MSHR hits
system.l2.ReadSharedReq_mshr_misses::.cpu.data          545                       # number of ReadSharedReq MSHR misses
system.l2.ReadSharedReq_mshr_misses::total          545                       # number of ReadSharedReq MSHR misses
system.l2.ReadSharedReq_mshr_miss_latency::.cpu.data     42075000                       # number of ReadSharedReq MSHR miss cycles
system.l2.ReadSharedReq_mshr_miss_latency::total     42075000                       # number of ReadSharedReq MSHR miss cycles
system.l2.ReadSharedReq_mshr_miss_rate::.cpu.data     0.032948                       # mshr miss rate for ReadSharedReq accesses
system.l2.ReadSharedReq_mshr_miss_rate::total     0.032948                       # mshr miss rate for ReadSharedReq accesses
system.l2.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 77201.834862                       # average ReadSharedReq mshr miss latency
system.l2.ReadSharedReq_avg_mshr_miss_latency::total 77201.834862                       # average ReadSharedReq mshr miss latency
system.l2.tags.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.l2.tags.tagsinuse                 26016.296189                       # Cycle average of tags in use
system.l2.tags.total_refs                     1447320                       # Total number of references to valid blocks.
system.l2.tags.sampled_refs                     39873                       # Sample count of references to valid blocks.
system.l2.tags.avg_refs                     36.298247                       # Average number of references to valid blocks.
system.l2.tags.warmup_cycle                     77000                       # Cycle when the warmup percentage was hit.
system.l2.tags.occ_blocks::.writebacks       1.268382                       # Average occupied blocks per requestor
system.l2.tags.occ_blocks::.cpu.inst       312.122180                       # Average occupied blocks per requestor
system.l2.tags.occ_blocks::.cpu.data     25702.905627                       # Average occupied blocks per requestor
system.l2.tags.occ_percent::.writebacks      0.000039                       # Average percentage of cache occupancy
system.l2.tags.occ_percent::.cpu.inst        0.009525                       # Average percentage of cache occupancy
system.l2.tags.occ_percent::.cpu.data        0.784390                       # Average percentage of cache occupancy
system.l2.tags.occ_percent::total            0.793954                       # Average percentage of cache occupancy
system.l2.tags.occ_task_id_blocks::1024         32768                       # Occupied blocks per task id
system.l2.tags.age_task_id_blocks_1024::0            3                       # Occupied blocks per task id
system.l2.tags.age_task_id_blocks_1024::1           31                       # Occupied blocks per task id
system.l2.tags.age_task_id_blocks_1024::2          362                       # Occupied blocks per task id
system.l2.tags.age_task_id_blocks_1024::3         3296                       # Occupied blocks per task id
system.l2.tags.age_task_id_blocks_1024::4        29076                       # Occupied blocks per task id
system.l2.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.l2.tags.tag_accesses                  11618497                       # Number of tag accesses
system.l2.tags.data_accesses                 11618497                       # Number of data accesses
system.cpu_voltage_domain.voltage                   1                       # Voltage in Volts
system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.mem_ctrls.bytes_read::.cpu.inst          32768                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::.cpu.data        2518848                       # Number of bytes read from this memory
system.mem_ctrls.bytes_read::total            2551616                       # Number of bytes read from this memory
system.mem_ctrls.bytes_inst_read::.cpu.inst        32768                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_inst_read::total         32768                       # Number of instructions bytes read from this memory
system.mem_ctrls.bytes_written::.writebacks       418304                       # Number of bytes written to this memory
system.mem_ctrls.bytes_written::total          418304                       # Number of bytes written to this memory
system.mem_ctrls.num_reads::.cpu.inst             512                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::.cpu.data           39357                       # Number of read requests responded to by this memory
system.mem_ctrls.num_reads::total               39869                       # Number of read requests responded to by this memory
system.mem_ctrls.num_writes::.writebacks         6536                       # Number of write requests responded to by this memory
system.mem_ctrls.num_writes::total               6536                       # Number of write requests responded to by this memory
system.mem_ctrls.bw_read::.cpu.inst            504474                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::.cpu.data          38778510                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_read::total              39282985                       # Total read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::.cpu.inst       504474                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_inst_read::total           504474                       # Instruction read bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::.writebacks        6439930                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_write::total              6439930                       # Write bandwidth from this memory (bytes/s)
system.mem_ctrls.bw_total::.writebacks        6439930                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::.cpu.inst           504474                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::.cpu.data         38778510                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.bw_total::total             45722915                       # Total bandwidth to/from this memory (bytes/s)
system.mem_ctrls.avgPriority_.writebacks::samples      6536.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.inst::samples       512.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.avgPriority_.cpu.data::samples     39355.00                       # Average QoS priority value for accepted requests
system.mem_ctrls.priorityMinLatency      0.000000018750                       # per QoS priority minimum request to response latency (s)
system.mem_ctrls.priorityMaxLatency      0.018681178500                       # per QoS priority maximum request to response latency (s)
system.mem_ctrls.numReadWriteTurnArounds          361                       # Number of turnarounds from READ to WRITE
system.mem_ctrls.numWriteReadTurnArounds          361                       # Number of turnarounds from WRITE to READ
system.mem_ctrls.numStayReadState              102920                       # Number of times bus staying in READ state
system.mem_ctrls.numStayWriteState               6160                       # Number of times bus staying in WRITE state
system.mem_ctrls.readReqs                       39869                       # Number of read requests accepted
system.mem_ctrls.writeReqs                       6536                       # Number of write requests accepted
system.mem_ctrls.readBursts                     39869                       # Number of DRAM read bursts, including those serviced by the write queue
system.mem_ctrls.writeBursts                     6536                       # Number of DRAM write bursts, including those merged in the write queue
system.mem_ctrls.servicedByWrQ                      2                       # Number of DRAM read bursts serviced by the write queue
system.mem_ctrls.mergedWrBursts                     0                       # Number of DRAM write bursts merged with an existing one
system.mem_ctrls.neitherReadNorWriteReqs            0                       # Number of requests that are neither read nor write
system.mem_ctrls.perBankRdBursts::0              2477                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::1              2365                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::2              2347                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::3              2613                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::4              2682                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::5              2456                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::6              2446                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::7              2473                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::8              2473                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::9              2505                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::10             2490                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::11             2512                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::12             2509                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::13             2471                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::14             2553                       # Per bank write bursts
system.mem_ctrls.perBankRdBursts::15             2495                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::0               353                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::1               287                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::2               285                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::3               488                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::4               613                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::5               407                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::6               398                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::7               402                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::8               402                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::9               408                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::10              409                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::11              401                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::12              412                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::13              402                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::14              430                       # Per bank write bursts
system.mem_ctrls.perBankWrBursts::15              413                       # Per bank write bursts
system.mem_ctrls.avgRdQLen                       1.00                       # Average read queue length when enqueuing
system.mem_ctrls.avgWrQLen                      12.70                       # Average write queue length when enqueuing
system.mem_ctrls.totQLat                    472099000                       # Total ticks spent queuing
system.mem_ctrls.totBusLat                  199335000                       # Total ticks spent in databus transfers
system.mem_ctrls.totMemAccLat              1219605250                       # Total ticks spent from burst creation until serviced by the DRAM
system.mem_ctrls.avgQLat                     11841.85                       # Average queueing delay per DRAM burst
system.mem_ctrls.avgBusLat                    5000.00                       # Average bus latency per DRAM burst
system.mem_ctrls.avgMemAccLat                30591.85                       # Average memory access latency per DRAM burst
system.mem_ctrls.numRdRetry                         0                       # Number of times read queue was full causing retry
system.mem_ctrls.numWrRetry                         0                       # Number of times write queue was full causing retry
system.mem_ctrls.readRowHits                    27390                       # Number of row buffer hits during reads
system.mem_ctrls.writeRowHits                    5505                       # Number of row buffer hits during writes
system.mem_ctrls.readRowHitRate                 68.70                       # Row buffer hit rate for reads
system.mem_ctrls.writeRowHitRate                84.23                       # Row buffer hit rate for writes
system.mem_ctrls.readPktSize::0                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::1                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::2                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::3                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::4                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::5                     0                       # Read request sizes (log2)
system.mem_ctrls.readPktSize::6                 39869                       # Read request sizes (log2)
system.mem_ctrls.writePktSize::0                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::1                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::2                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::3                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::4                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::5                    0                       # Write request sizes (log2)
system.mem_ctrls.writePktSize::6                 6536                       # Write request sizes (log2)
system.mem_ctrls.rdQLenPdf::0                   39669                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::1                     192                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::2                       6                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::3                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::4                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::5                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::6                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::7                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::8                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::9                       0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::10                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::11                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::12                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::13                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::14                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::15                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::16                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::17                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::18                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::19                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::20                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::21                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::22                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::23                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::24                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::25                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::26                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::27                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::28                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::29                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::30                      0                       # What read queue length does an incoming req see
system.mem_ctrls.rdQLenPdf::31                      0                       # What read queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::0                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::1                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::2                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::3                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::4                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::5                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::6                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::7                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::8                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::9                       1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::10                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::11                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::12                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::13                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::14                      1                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::15                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::16                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::17                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::18                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::19                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::20                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::21                    363                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::22                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::23                    362                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::24                    363                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::25                    363                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::26                    365                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::27                    361                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::28                    364                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::29                    363                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::30                    361                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::31                    361                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::32                    361                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::33                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::34                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::35                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::36                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::37                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::38                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::39                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::40                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::41                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::42                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::43                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::44                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::45                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::46                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::47                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::48                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::49                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::50                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::51                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::52                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::53                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::54                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::55                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::56                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::57                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::58                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::59                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::60                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::61                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::62                      0                       # What write queue length does an incoming req see
system.mem_ctrls.wrQLenPdf::63                      0                       # What write queue length does an incoming req see
system.mem_ctrls.bytesPerActivate::samples        13481                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::mean    220.166456                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::gmean   178.935711                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::stdev   167.650795                       # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::0-127         2019     14.98%     14.98% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::128-255         7895     58.56%     73.54% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::256-383         2018     14.97%     88.51% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::384-511          471      3.49%     92.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::512-639          736      5.46%     97.46% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::640-767           34      0.25%     97.72% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::768-895           46      0.34%     98.06% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::896-1023           47      0.35%     98.41% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::1024-1151          215      1.59%    100.00% # Bytes accessed per row activation
system.mem_ctrls.bytesPerActivate::total        13481                       # Bytes accessed per row activation
system.mem_ctrls.rdPerTurnAround::samples          361                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::mean     110.404432                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::gmean     19.506845                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::stdev   1522.743778                       # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::0-1023          358     99.17%     99.17% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::1024-2047            2      0.55%     99.72% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::28672-29695            1      0.28%    100.00% # Reads before turning the bus around for writes
system.mem_ctrls.rdPerTurnAround::total           361                       # Reads before turning the bus around for writes
system.mem_ctrls.wrPerTurnAround::samples          361                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::mean      18.033241                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::gmean     18.032380                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::stdev      0.179514                       # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::18              349     96.68%     96.68% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::19               12      3.32%    100.00% # Writes before turning the bus around for reads
system.mem_ctrls.wrPerTurnAround::total           361                       # Writes before turning the bus around for reads
system.mem_ctrls.bytesReadDRAM                2551488                       # Total number of bytes read from DRAM
system.mem_ctrls.bytesReadWrQ                     128                       # Total number of bytes read from write queue
system.mem_ctrls.bytesWritten                  416640                       # Total number of bytes written to DRAM
system.mem_ctrls.bytesReadSys                 2551616                       # Total read bytes from the system interface side
system.mem_ctrls.bytesWrittenSys               418304                       # Total written bytes from the system interface side
system.mem_ctrls.avgRdBW                        39.28                       # Average DRAM read bandwidth in MiByte/s
system.mem_ctrls.avgWrBW                         6.41                       # Average achieved write bandwidth in MiByte/s
system.mem_ctrls.avgRdBWSys                     39.28                       # Average system read bandwidth in MiByte/s
system.mem_ctrls.avgWrBWSys                      6.44                       # Average system write bandwidth in MiByte/s
system.mem_ctrls.peakBW                      12800.00                       # Theoretical peak bandwidth in MiByte/s
system.mem_ctrls.busUtil                         0.36                       # Data bus utilization in percentage
system.mem_ctrls.busUtilRead                     0.31                       # Data bus utilization in percentage for reads
system.mem_ctrls.busUtilWrite                    0.05                       # Data bus utilization in percentage for writes
system.mem_ctrls.totGap                   64954072000                       # Total gap between requests
system.mem_ctrls.avgGap                    1399721.41                       # Average gap between requests
system.mem_ctrls.masterReadBytes::.cpu.inst        32768                       # Per-master bytes read from memory
system.mem_ctrls.masterReadBytes::.cpu.data      2518720                       # Per-master bytes read from memory
system.mem_ctrls.masterWriteBytes::.writebacks       416640                       # Per-master bytes write to memory
system.mem_ctrls.masterReadRate::.cpu.inst 504474.357940799033                       # Per-master bytes read from memory rate (Bytes/sec)
system.mem_ctrls.masterReadRate::.cpu.data 38776539.759297162294                       # Per-master bytes read from memory rate (Bytes/sec)
system.mem_ctrls.masterWriteRate::.writebacks 6414312.637098832056                       # Per-master bytes write to memory rate (Bytes/sec)
system.mem_ctrls.masterReadAccesses::.cpu.inst          512                       # Per-master read serviced memory accesses
system.mem_ctrls.masterReadAccesses::.cpu.data        39357                       # Per-master read serviced memory accesses
system.mem_ctrls.masterWriteAccesses::.writebacks         6536                       # Per-master write serviced memory accesses
system.mem_ctrls.masterReadTotalLat::.cpu.inst     13029000                       # Per-master read total memory access latency
system.mem_ctrls.masterReadTotalLat::.cpu.data   1206576250                       # Per-master read total memory access latency
system.mem_ctrls.masterWriteTotalLat::.writebacks 796441060500                       # Per-master write total memory access latency
system.mem_ctrls.masterReadAvgLat::.cpu.inst     25447.27                       # Per-master read average memory access latency
system.mem_ctrls.masterReadAvgLat::.cpu.data     30657.22                       # Per-master read average memory access latency
system.mem_ctrls.masterWriteAvgLat::.writebacks 121854507.42                       # Per-master write average memory access latency
system.mem_ctrls.pageHitRate                    70.89                       # Row buffer hit rate, read and write combined
system.mem_ctrls.rank1.actEnergy             48309240                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.rank1.preEnergy             25676970                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.rank1.readEnergy           142857120                       # Energy for read commands per rank (pJ)
system.mem_ctrls.rank1.writeEnergy           17105940                       # Energy for write commands per rank (pJ)
system.mem_ctrls.rank1.refreshEnergy     5127326880.000001                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.rank1.actBackEnergy      15399889500                       # Energy for active background per rank (pJ)
system.mem_ctrls.rank1.preBackEnergy      11974291680                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.rank1.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.rank1.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.rank1.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.rank1.totalEnergy        32735457330                       # Total energy per rank (pJ)
system.mem_ctrls.rank1.averagePower        503.973353                       # Core power per rank (mW)
system.mem_ctrls.rank1.totalIdleTime                0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.rank1.memoryStateTime::IDLE  30989223250                       # Time in different power states
system.mem_ctrls.rank1.memoryStateTime::REF   2168920000                       # Time in different power states
system.mem_ctrls.rank1.memoryStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.rank1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.rank1.memoryStateTime::ACT  31796595250                       # Time in different power states
system.mem_ctrls.rank1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.mem_ctrls.rank0.actEnergy             47952240                       # Energy for activate commands per rank (pJ)
system.mem_ctrls.rank0.preEnergy             25483425                       # Energy for precharge commands per rank (pJ)
system.mem_ctrls.rank0.readEnergy           141793260                       # Energy for read commands per rank (pJ)
system.mem_ctrls.rank0.writeEnergy           16876260                       # Energy for write commands per rank (pJ)
system.mem_ctrls.rank0.refreshEnergy     5127326880.000001                       # Energy for refresh commands per rank (pJ)
system.mem_ctrls.rank0.actBackEnergy      14985160350                       # Energy for active background per rank (pJ)
system.mem_ctrls.rank0.preBackEnergy      12323537280                       # Energy for precharge background per rank (pJ)
system.mem_ctrls.rank0.actPowerDownEnergy            0                       # Energy for active power-down per rank (pJ)
system.mem_ctrls.rank0.prePowerDownEnergy            0                       # Energy for precharge power-down per rank (pJ)
system.mem_ctrls.rank0.selfRefreshEnergy            0                       # Energy for self refresh per rank (pJ)
system.mem_ctrls.rank0.totalEnergy        32668129695                       # Total energy per rank (pJ)
system.mem_ctrls.rank0.averagePower        502.936821                       # Core power per rank (mW)
system.mem_ctrls.rank0.totalIdleTime                0                       # Total Idle time Per DRAM Rank
system.mem_ctrls.rank0.memoryStateTime::IDLE  31902252500                       # Time in different power states
system.mem_ctrls.rank0.memoryStateTime::REF   2168920000                       # Time in different power states
system.mem_ctrls.rank0.memoryStateTime::SREF            0                       # Time in different power states
system.mem_ctrls.rank0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.mem_ctrls.rank0.memoryStateTime::ACT  30883566000                       # Time in different power states
system.mem_ctrls.rank0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.pwrStateResidencyTicks::ON     64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.demand_hits::.cpu.inst     27660948                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         27660948                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::.cpu.inst     27660948                       # number of overall hits
system.cpu.icache.overall_hits::total        27660948                       # number of overall hits
system.cpu.icache.demand_misses::.cpu.inst       668914                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total         668914                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::.cpu.inst       668914                       # number of overall misses
system.cpu.icache.overall_misses::total        668914                       # number of overall misses
system.cpu.icache.demand_miss_latency::.cpu.inst   8729688500                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   8729688500                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::.cpu.inst   8729688500                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   8729688500                       # number of overall miss cycles
system.cpu.icache.demand_accesses::.cpu.inst     28329862                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     28329862                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::.cpu.inst     28329862                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     28329862                       # number of overall (read+write) accesses
system.cpu.icache.demand_miss_rate::.cpu.inst     0.023612                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.023612                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::.cpu.inst     0.023612                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.023612                       # miss rate for overall accesses
system.cpu.icache.demand_avg_miss_latency::.cpu.inst 13050.539382                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13050.539382                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::.cpu.inst 13050.539382                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13050.539382                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.icache.writebacks::.writebacks       668515                       # number of writebacks
system.cpu.icache.writebacks::total            668515                       # number of writebacks
system.cpu.icache.demand_mshr_misses::.cpu.inst       668914                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total       668914                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::.cpu.inst       668914                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total       668914                       # number of overall MSHR misses
system.cpu.icache.demand_mshr_miss_latency::.cpu.inst   8060775500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   8060775500                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::.cpu.inst   8060775500                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   8060775500                       # number of overall MSHR miss cycles
system.cpu.icache.demand_mshr_miss_rate::.cpu.inst     0.023612                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.023612                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::.cpu.inst     0.023612                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.023612                       # mshr miss rate for overall accesses
system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 12050.540877                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 12050.540877                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 12050.540877                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 12050.540877                       # average overall mshr miss latency
system.cpu.icache.replacements                 668515                       # number of replacements
system.cpu.icache.ReadReq_hits::.cpu.inst     27660948                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        27660948                       # number of ReadReq hits
system.cpu.icache.ReadReq_misses::.cpu.inst       668914                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total        668914                       # number of ReadReq misses
system.cpu.icache.ReadReq_miss_latency::.cpu.inst   8729688500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   8729688500                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_accesses::.cpu.inst     28329862                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     28329862                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_miss_rate::.cpu.inst     0.023612                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.023612                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 13050.539382                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13050.539382                       # average ReadReq miss latency
system.cpu.icache.ReadReq_mshr_misses::.cpu.inst       668914                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total       668914                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst   8060775500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   8060775500                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst     0.023612                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.023612                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 12050.540877                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12050.540877                       # average ReadReq mshr miss latency
system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.icache.tags.tagsinuse           397.678010                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            28329861                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs            668913                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs             42.352086                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle             87500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::.cpu.inst   397.678010                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::.cpu.inst     0.776715                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.776715                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          398                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           10                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2            4                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4          383                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024     0.777344                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses          57328637                       # Number of tag accesses
system.cpu.icache.tags.data_accesses         57328637                       # Number of data accesses
system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.demand_hits::.cpu.data     35656670                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         35656670                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::.cpu.data     35659996                       # number of overall hits
system.cpu.dcache.overall_hits::total        35659996                       # number of overall hits
system.cpu.dcache.demand_misses::.cpu.data        75305                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total          75305                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::.cpu.data        75340                       # number of overall misses
system.cpu.dcache.overall_misses::total         75340                       # number of overall misses
system.cpu.dcache.demand_miss_latency::.cpu.data   4651880500                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   4651880500                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::.cpu.data   4651880500                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   4651880500                       # number of overall miss cycles
system.cpu.dcache.demand_accesses::.cpu.data     35731975                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     35731975                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::.cpu.data     35735336                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     35735336                       # number of overall (read+write) accesses
system.cpu.dcache.demand_miss_rate::.cpu.data     0.002107                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002107                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::.cpu.data     0.002108                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002108                       # miss rate for overall accesses
system.cpu.dcache.demand_avg_miss_latency::.cpu.data 61773.859637                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 61773.859637                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::.cpu.data 61745.161933                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 61745.161933                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets               0                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.dcache.writebacks::.writebacks        50524                       # number of writebacks
system.cpu.dcache.writebacks::total             50524                       # number of writebacks
system.cpu.dcache.demand_mshr_hits::.cpu.data        19858                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        19858                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::.cpu.data        19858                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        19858                       # number of overall MSHR hits
system.cpu.dcache.demand_mshr_misses::.cpu.data        55447                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total        55447                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::.cpu.data        55476                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total        55476                       # number of overall MSHR misses
system.cpu.dcache.demand_mshr_miss_latency::.cpu.data   3467303000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total   3467303000                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::.cpu.data   3468507500                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total   3468507500                       # number of overall MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_rate::.cpu.data     0.001552                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001552                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::.cpu.data     0.001552                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001552                       # mshr miss rate for overall accesses
system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 62533.644742                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 62533.644742                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 62522.667460                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 62522.667460                       # average overall mshr miss latency
system.cpu.dcache.replacements                  54452                       # number of replacements
system.cpu.dcache.ReadReq_hits::.cpu.data     21457486                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        21457486                       # number of ReadReq hits
system.cpu.dcache.ReadReq_misses::.cpu.data        19738                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         19738                       # number of ReadReq misses
system.cpu.dcache.ReadReq_miss_latency::.cpu.data    309363000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total    309363000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_accesses::.cpu.data     21477224                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     21477224                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_miss_rate::.cpu.data     0.000919                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.000919                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 15673.472490                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 15673.472490                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_mshr_hits::.cpu.data         3226                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total         3226                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::.cpu.data        16512                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        16512                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data    239381500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    239381500                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data     0.000769                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.000769                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 14497.426114                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14497.426114                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_hits::.cpu.data     14199184                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       14199184                       # number of WriteReq hits
system.cpu.dcache.WriteReq_misses::.cpu.data        55567                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        55567                       # number of WriteReq misses
system.cpu.dcache.WriteReq_miss_latency::.cpu.data   4342517500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total   4342517500                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_accesses::.cpu.data     14254751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     14254751                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_miss_rate::.cpu.data     0.003898                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.003898                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 78149.216261                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 78149.216261                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_mshr_hits::.cpu.data        16632                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        16632                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_misses::.cpu.data        38935                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total        38935                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data   3227921500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total   3227921500                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data     0.002731                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.002731                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 82905.393605                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82905.393605                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_hits::.cpu.data         3326                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total          3326                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_misses::.cpu.data           35                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total           35                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_accesses::.cpu.data         3361                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total         3361                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data     0.010414                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.010414                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data           29                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total           29                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data      1204500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total      1204500                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data     0.008628                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.008628                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 41534.482759                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 41534.482759                       # average SoftPFReq mshr miss latency
system.cpu.dcache.LoadLockedReq_hits::.cpu.data        89082                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        89082                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_accesses::.cpu.data        89082                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        89082                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_hits::.cpu.data        89082                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        89082                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_accesses::.cpu.data        89082                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        89082                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.dcache.tags.tagsinuse          1020.450956                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            35893636                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs             55476                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            647.011969                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle            195500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::.cpu.data  1020.450956                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::.cpu.data     0.996534                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.996534                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024         1024                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0            4                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1           51                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          454                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3          477                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           38                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          71882476                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         71882476                       # Number of data accesses
system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states
system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED  64954738500                       # Cumulative time (in ticks) in various power states

---------- End Simulation Statistics   ----------