From 0f04712c19a021cc7eb5994e43a1a7de2de108d5 Mon Sep 17 00:00:00 2001 From: Huaqi Fang <578567190@qq.com> Date: Fri, 16 Aug 2024 19:27:02 +0800 Subject: [PATCH] conf/evalsoc: enable riscv hpm support for nuclei peformance monitor see the pmu section in dts And default user mode access cycle and instret not allowed when PMU enabled. echo 2 > /proc/sys/kernel/perf_user_access Signed-off-by: Huaqi Fang <578567190@qq.com> --- conf/evalsoc/linux_rv64imac_defconfig | 2 + conf/evalsoc/linux_rv64imafdc_defconfig | 2 + conf/evalsoc/nuclei_rv64imac.dts | 94 +++++++++++++++++++++++++ conf/evalsoc/nuclei_rv64imafdc.dts | 94 +++++++++++++++++++++++++ 4 files changed, 192 insertions(+) diff --git a/conf/evalsoc/linux_rv64imac_defconfig b/conf/evalsoc/linux_rv64imac_defconfig index 3208c55..b020ab2 100644 --- a/conf/evalsoc/linux_rv64imac_defconfig +++ b/conf/evalsoc/linux_rv64imac_defconfig @@ -12,6 +12,8 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_LZO is not set CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set +CONFIG_PERF_EVENTS=y +CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_HZ_100=y diff --git a/conf/evalsoc/linux_rv64imafdc_defconfig b/conf/evalsoc/linux_rv64imafdc_defconfig index 3208c55..b020ab2 100644 --- a/conf/evalsoc/linux_rv64imafdc_defconfig +++ b/conf/evalsoc/linux_rv64imafdc_defconfig @@ -12,6 +12,8 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_LZO is not set CONFIG_EXPERT=y # CONFIG_KALLSYMS is not set +CONFIG_PERF_EVENTS=y +CONFIG_NONPORTABLE=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_HZ_100=y diff --git a/conf/evalsoc/nuclei_rv64imac.dts b/conf/evalsoc/nuclei_rv64imac.dts index 35e3366..d819015 100644 --- a/conf/evalsoc/nuclei_rv64imac.dts +++ b/conf/evalsoc/nuclei_rv64imac.dts @@ -171,6 +171,100 @@ clock-output-names = "hfclk"; }; + pmu { + compatible = "riscv,pmu"; + /* https://perf.wiki.kernel.org/index.php/Tutorial#Events */ + /* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */ + /* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */ + riscv,event-to-mhpmevent = + /* Type #0 SBI_PMU_HW_CPU_CYCLES -> Nuclei event sel=0 idx=1 Cycle count */ + <0x00001 0x00000000 0x00000010>, + /* Type #0 SBI_PMU_HW_INSTRUCTIONS -> Nuclei event sel=0 idx=2 Retired instruction count */ + <0x00002 0x00000000 0x00000020>, + /* Type #0 SBI_PMU_HW_CACHE_MISSES -> Nuclei event sel=1 idx=2 Dcache miss */ + <0x00004 0x00000000 0x00000021>, + /* Type #0 SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Nuclei event sel=0 idx=8 Conditional branch */ + <0x00005 0x00000000 0x00000080>, + /* Type #0 SBI_PMU_HW_BRANCH_MISSES -> Nuclei event sel=0 idx=24 Conditional branch prediction fail */ + <0x00006 0x00000000 0x00000180>, + /* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) MISS(1) -> Nuclei event sel=1 idx=1 Icache miss */ + <0x10009 0x00000000 0x00000011>, + /* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) MISS(1) -> Nuclei event sel=1 idx=2 Dcache miss */ + <0x10001 0x00000000 0x00000021>, + /* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) MISS(1) -> Nuclei event sel=1 idx=3 Itlb miss */ + <0x10021 0x00000000 0x00000031>, + /* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) MISS(1) -> Nuclei event sel=1 idx=4 Dtlb miss */ + <0x10019 0x00000000 0x00000041>; + /* make hpm3-6 counter available for all hardware events */ + riscv,event-to-mhpmcounters = + <0x00001 0x00000007 0x00000078>, + <0x10009 0x00010021 0x00000078>; + /* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */ + riscv,raw-event-to-mhpmcounters = + /* instruction commit events - 0x1 Cycle count */ + <0x00000000 0x00000010 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x2 Retired instruction count */ + <0x00000000 0x00000020 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x3 Integer load instruction(includes LR) */ + <0x00000000 0x00000030 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x4 Integer store instruction(includes SC) */ + <0x00000000 0x00000040 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x5 Atomic memory operation(do not include LR and SC) */ + <0x00000000 0x00000050 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x6 System instruction */ + <0x00000000 0x00000060 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x7 Integer computational instruction(excluding multiplication/division/remainder) */ + <0x00000000 0x00000070 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x8 Conditional branch */ + <0x00000000 0x00000080 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x9 Taken conditional branch */ + <0x00000000 0x00000090 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xa JAL instruction */ + <0x00000000 0x000000a0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xb JALR instruction */ + <0x00000000 0x000000b0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xc Return instruction */ + <0x00000000 0x000000c0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xd Control transfer instruction(CBR+JAL+JALR) */ + <0x00000000 0x000000d0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xe Reserved */ + <0x00000000 0x000000e0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xf Integer multiplication instruction */ + <0x00000000 0x000000f0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x10 Integer division/remainder instruction */ + <0x00000000 0x00000100 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x11 Floating-point load instruction */ + <0x00000000 0x00000110 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x12 Floating-point store instruction */ + <0x00000000 0x00000120 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x13 Floating-point addition/subtraction */ + <0x00000000 0x00000130 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x14 Floating-point multiplication */ + <0x00000000 0x00000140 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x15 Floating-point fused multiply-add(FMADD/FMSUB/FNMSUB/FNMADD) */ + <0x00000000 0x00000150 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x16 Floating-point division or square-root */ + <0x00000000 0x00000160 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x17 Other floating-point instruction */ + <0x00000000 0x00000170 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x18 Conditional branch prediction fail */ + <0x00000000 0x00000180 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x19 JAL prediction fail */ + <0x00000000 0x00000190 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x1a JALR prediction fail */ + <0x00000000 0x000001a0 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x1 Icache miss */ + <0x00000000 0x00000011 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x2 Dcache miss */ + <0x00000000 0x00000021 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x3 ITLB miss */ + <0x00000000 0x00000031 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x4 DTLB miss */ + <0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x5 Main TLB miss */ + <0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>; + }; + plic0: interrupt-controller@1c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; diff --git a/conf/evalsoc/nuclei_rv64imafdc.dts b/conf/evalsoc/nuclei_rv64imafdc.dts index f9e671f..195adca 100644 --- a/conf/evalsoc/nuclei_rv64imafdc.dts +++ b/conf/evalsoc/nuclei_rv64imafdc.dts @@ -171,6 +171,100 @@ clock-output-names = "hfclk"; }; + pmu { + compatible = "riscv,pmu"; + /* https://perf.wiki.kernel.org/index.php/Tutorial#Events */ + /* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */ + /* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */ + riscv,event-to-mhpmevent = + /* Type #0 SBI_PMU_HW_CPU_CYCLES -> Nuclei event sel=0 idx=1 Cycle count */ + <0x00001 0x00000000 0x00000010>, + /* Type #0 SBI_PMU_HW_INSTRUCTIONS -> Nuclei event sel=0 idx=2 Retired instruction count */ + <0x00002 0x00000000 0x00000020>, + /* Type #0 SBI_PMU_HW_CACHE_MISSES -> Nuclei event sel=1 idx=2 Dcache miss */ + <0x00004 0x00000000 0x00000021>, + /* Type #0 SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Nuclei event sel=0 idx=8 Conditional branch */ + <0x00005 0x00000000 0x00000080>, + /* Type #0 SBI_PMU_HW_BRANCH_MISSES -> Nuclei event sel=0 idx=24 Conditional branch prediction fail */ + <0x00006 0x00000000 0x00000180>, + /* Type #1 SBI_PMU_HW_CACHE_L1I(1) READ(0) MISS(1) -> Nuclei event sel=1 idx=1 Icache miss */ + <0x10009 0x00000000 0x00000011>, + /* Type #1 SBI_PMU_HW_CACHE_L1D(0) READ(0) MISS(1) -> Nuclei event sel=1 idx=2 Dcache miss */ + <0x10001 0x00000000 0x00000021>, + /* Type #1 SBI_PMU_HW_CACHE_ITLB(4) READ(0) MISS(1) -> Nuclei event sel=1 idx=3 Itlb miss */ + <0x10021 0x00000000 0x00000031>, + /* Type #1 SBI_PMU_HW_CACHE_DTLB(3) READ(0) MISS(1) -> Nuclei event sel=1 idx=4 Dtlb miss */ + <0x10019 0x00000000 0x00000041>; + /* make hpm3-6 counter available for all hardware events */ + riscv,event-to-mhpmcounters = + <0x00001 0x00000007 0x00000078>, + <0x10009 0x00010021 0x00000078>; + /* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */ + riscv,raw-event-to-mhpmcounters = + /* instruction commit events - 0x1 Cycle count */ + <0x00000000 0x00000010 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x2 Retired instruction count */ + <0x00000000 0x00000020 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x3 Integer load instruction(includes LR) */ + <0x00000000 0x00000030 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x4 Integer store instruction(includes SC) */ + <0x00000000 0x00000040 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x5 Atomic memory operation(do not include LR and SC) */ + <0x00000000 0x00000050 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x6 System instruction */ + <0x00000000 0x00000060 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x7 Integer computational instruction(excluding multiplication/division/remainder) */ + <0x00000000 0x00000070 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x8 Conditional branch */ + <0x00000000 0x00000080 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x9 Taken conditional branch */ + <0x00000000 0x00000090 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xa JAL instruction */ + <0x00000000 0x000000a0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xb JALR instruction */ + <0x00000000 0x000000b0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xc Return instruction */ + <0x00000000 0x000000c0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xd Control transfer instruction(CBR+JAL+JALR) */ + <0x00000000 0x000000d0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xe Reserved */ + <0x00000000 0x000000e0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0xf Integer multiplication instruction */ + <0x00000000 0x000000f0 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x10 Integer division/remainder instruction */ + <0x00000000 0x00000100 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x11 Floating-point load instruction */ + <0x00000000 0x00000110 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x12 Floating-point store instruction */ + <0x00000000 0x00000120 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x13 Floating-point addition/subtraction */ + <0x00000000 0x00000130 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x14 Floating-point multiplication */ + <0x00000000 0x00000140 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x15 Floating-point fused multiply-add(FMADD/FMSUB/FNMSUB/FNMADD) */ + <0x00000000 0x00000150 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x16 Floating-point division or square-root */ + <0x00000000 0x00000160 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x17 Other floating-point instruction */ + <0x00000000 0x00000170 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x18 Conditional branch prediction fail */ + <0x00000000 0x00000180 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x19 JAL prediction fail */ + <0x00000000 0x00000190 0xffffffff 0xffffffff 0x00000078>, + /* instruction commit events - 0x1a JALR prediction fail */ + <0x00000000 0x000001a0 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x1 Icache miss */ + <0x00000000 0x00000011 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x2 Dcache miss */ + <0x00000000 0x00000021 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x3 ITLB miss */ + <0x00000000 0x00000031 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x4 DTLB miss */ + <0x00000000 0x00000041 0xffffffff 0xffffffff 0x00000078>, + /* memory access events - 0x5 Main TLB miss */ + <0x00000000 0x00000051 0xffffffff 0xffffffff 0x00000078>; + }; + plic0: interrupt-controller@1c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0";