From 92a146dda2a9773e498c48d0b517145ae32b89b6 Mon Sep 17 00:00:00 2001
From: Huaqi Fang <578567190@qq.com>
Date: Thu, 29 Aug 2024 18:52:51 +0800
Subject: [PATCH] conf/evalsoc: Fix wrong riscv,event-to-mhpmcounters mapping

Signed-off-by: Huaqi Fang <578567190@qq.com>
---
 conf/evalsoc/nuclei_rv64imac.dts   | 3 ++-
 conf/evalsoc/nuclei_rv64imafdc.dts | 3 ++-
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/conf/evalsoc/nuclei_rv64imac.dts b/conf/evalsoc/nuclei_rv64imac.dts
index 96382a2..bea2eb4 100644
--- a/conf/evalsoc/nuclei_rv64imac.dts
+++ b/conf/evalsoc/nuclei_rv64imac.dts
@@ -185,6 +185,7 @@
   pmu {
     compatible = "riscv,pmu";
     /* https://perf.wiki.kernel.org/index.php/Tutorial#Events */
+    /* eg. perf stat -B coremark */
     /* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */
     /* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */
     riscv,event-to-mhpmevent =
@@ -209,7 +210,7 @@
     /* make hpm3-6 counter available for all hardware events */
     riscv,event-to-mhpmcounters =
       <0x00001 0x00000007 0x00000078>,
-      <0x10009 0x00010021 0x00000078>;
+      <0x10001 0x00010022 0x00000078>;
     /* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */
     riscv,raw-event-to-mhpmcounters =
       /* instruction commit events - 0x1 Cycle count */
diff --git a/conf/evalsoc/nuclei_rv64imafdc.dts b/conf/evalsoc/nuclei_rv64imafdc.dts
index 067738b..ab14b9c 100644
--- a/conf/evalsoc/nuclei_rv64imafdc.dts
+++ b/conf/evalsoc/nuclei_rv64imafdc.dts
@@ -185,6 +185,7 @@
   pmu {
     compatible = "riscv,pmu";
     /* https://perf.wiki.kernel.org/index.php/Tutorial#Events */
+    /* eg. perf stat -B coremark */
     /* eg. perf stat -e cycles -e instructions -e cache-misses -e branches -e branch-misses coremark */
     /* eg. perf stat -e cycles -e instructions -e L1-icache-load-misses -e L1-dcache-load-misses -e iTLB-load-misses -e dTLB-load-misses coremark */
     riscv,event-to-mhpmevent =
@@ -209,7 +210,7 @@
     /* make hpm3-6 counter available for all hardware events */
     riscv,event-to-mhpmcounters =
       <0x00001 0x00000007 0x00000078>,
-      <0x10009 0x00010021 0x00000078>;
+      <0x10001 0x00010022 0x00000078>;
     /* Raw event: eg. perf stat -e cycles -e instructions -e r00000190 -e r00000010 coremark */
     riscv,raw-event-to-mhpmcounters =
       /* instruction commit events - 0x1 Cycle count */