shartid CSR #20
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Hello, |
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Replies: 3 comments 2 replies
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We just add this csr to avoid ecall to m-mode to get hartid, @matthewgui could you provide more details |
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hello, @aousherovitch-tt
Because we use plic as interrupt controller,its claim register is percpu context(https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#2-memory-map), so core hartid is needed.
yes, optee core code is relying on core id, which is determined by the optee framework, in our current hardware environment, using hartid is convenient for us. |
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Thank you, @fanghuaqi and @matthewgui |
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hello, @aousherovitch-tt
Because we use plic as interrupt controller,its claim register is percpu context(https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#2-memory-map), so core hartid is needed.