From 24358e655df2bebe8e3b44f9df08ee6b13bfd009 Mon Sep 17 00:00:00 2001 From: dongyongtao Date: Tue, 29 Oct 2024 14:18:13 +0800 Subject: [PATCH] SoC: now n100 external interrupt number has changed from 30 to 16 Signed-off-by: dongyongtao --- .../nuclei_fpga_eval/Source/GCC/evalsoc.memory | 8 +++++--- SoC/evalsoc/Common/Include/cpufeature.h | 2 +- SoC/evalsoc/Common/Include/evalsoc.h | 14 -------------- SoC/evalsoc/Common/Source/GCC/startup_evalsoc.S | 2 +- 4 files changed, 7 insertions(+), 19 deletions(-) diff --git a/SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/evalsoc.memory b/SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/evalsoc.memory index 1d87183e..d2e5cabe 100644 --- a/SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/evalsoc.memory +++ b/SoC/evalsoc/Board/nuclei_fpga_eval/Source/GCC/evalsoc.memory @@ -16,10 +16,12 @@ SRAM_MEMORY_ROM_SIZE = 0x10000; /* MTVT and MTVEC Information */ /* - * MTVT_BASE and MTVEC_BASE must be set with an value + * MTVT_BASE and MTVEC_BASE must be set with an value(uncomment it) if it is present * If it is not present, you need to remove section in the linker script * MTVT_BASE: isr_vector section * MTVEC_BASE: exception section + * + * MTVT_BASE = 0xA0000000; + * MTVEC_BASE = 0xA000004c; */ -MTVT_BASE = 0xA0000000; -MTVEC_BASE = 0xA0000084; + diff --git a/SoC/evalsoc/Common/Include/cpufeature.h b/SoC/evalsoc/Common/Include/cpufeature.h index 2ef99109..865135eb 100644 --- a/SoC/evalsoc/Common/Include/cpufeature.h +++ b/SoC/evalsoc/Common/Include/cpufeature.h @@ -21,7 +21,7 @@ extern "C" { #define CFG_TMR_PRIVATE #define CFG_HAS_IRQC // External Interrupt Number -#define CFG_IRQ_NUM 30 +#define CFG_IRQ_NUM 16 // EXCP is the exception module, if not defined, it means not present // If not present, you need to remove .exception section in linker script diff --git a/SoC/evalsoc/Common/Include/evalsoc.h b/SoC/evalsoc/Common/Include/evalsoc.h index 366bea9a..29198f7d 100644 --- a/SoC/evalsoc/Common/Include/evalsoc.h +++ b/SoC/evalsoc/Common/Include/evalsoc.h @@ -94,20 +94,6 @@ typedef enum IRQn { SOC_INT15_IRQn = 15, /*!< Device Interrupt */ SOC_INT16_IRQn = 16, /*!< Device Interrupt */ SOC_INT17_IRQn = 17, /*!< Device Interrupt */ - SOC_INT18_IRQn = 18, /*!< Device Interrupt */ - SOC_INT19_IRQn = 19, /*!< Device Interrupt */ - SOC_INT20_IRQn = 20, /*!< Device Interrupt */ - SOC_INT21_IRQn = 21, /*!< Device Interrupt */ - SOC_INT22_IRQn = 22, /*!< Device Interrupt */ - SOC_INT23_IRQn = 23, /*!< Device Interrupt */ - SOC_INT24_IRQn = 24, /*!< Device Interrupt */ - SOC_INT25_IRQn = 25, /*!< Device Interrupt */ - SOC_INT26_IRQn = 26, /*!< Device Interrupt */ - SOC_INT27_IRQn = 27, /*!< Device Interrupt */ - SOC_INT28_IRQn = 28, /*!< Device Interrupt */ - SOC_INT29_IRQn = 29, /*!< Device Interrupt */ - SOC_INT30_IRQn = 30, /*!< Device Interrupt */ - SOC_INT31_IRQn = 31, /*!< Device Interrupt */ #ifdef CFG_IRQ_NUM SOC_INT_MAX = 2 + CFG_IRQ_NUM, /*!< Two fixed cpu interrupt and max 30 external interrupt */ #else diff --git a/SoC/evalsoc/Common/Source/GCC/startup_evalsoc.S b/SoC/evalsoc/Common/Source/GCC/startup_evalsoc.S index 2c2baecd..5e61e7cf 100644 --- a/SoC/evalsoc/Common/Source/GCC/startup_evalsoc.S +++ b/SoC/evalsoc/Common/Source/GCC/startup_evalsoc.S @@ -66,7 +66,7 @@ _start: /* Set correct sp for current cpu */ la sp, _sp - /* mtvec and mtvt are readonly CSRs for N100, no need to initialize it */ + /* mtvec and mtvt are initialized in _premain_init if they are writable */ /* ===== Startup Stage 2 ===== */