From 761c4712cb7f9b3aee5a18de3ddcc84ed7d95836 Mon Sep 17 00:00:00 2001 From: dongyongtao Date: Tue, 29 Oct 2024 15:03:45 +0800 Subject: [PATCH] SoC: Now n100 has writable mtvt and mtvec csr to configure by software Signed-off-by: dongyongtao --- SoC/evalsoc/Common/Include/cpufeature.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/SoC/evalsoc/Common/Include/cpufeature.h b/SoC/evalsoc/Common/Include/cpufeature.h index 865135eb..a80ac6ac 100644 --- a/SoC/evalsoc/Common/Include/cpufeature.h +++ b/SoC/evalsoc/Common/Include/cpufeature.h @@ -28,7 +28,7 @@ extern "C" { #define CFG_HAS_EXCP // Define it when you have TRAP related CSR such as MTVT and MTVEC -//#define CFG_HAS_TRAP_CSR +#define CFG_HAS_TRAP_CSR // PMONITOR is the mcycle and minsret counter, if not defined, it means not present #define CFG_HAS_PMONITOR