From 71673eb50b5d716da7844b9d7bd1c6aa19c6c4d1 Mon Sep 17 00:00:00 2001 From: anandaravuri Date: Thu, 12 Oct 2023 11:56:28 -0700 Subject: [PATCH] fix: set stride to 3 for fpga rd/wr cache hit/miss Signed-off-by: anandaravuri --- samples/cxl_host_exerciser/cxl_he_cache_cmd.h | 29 +++++++++++++++++-- 1 file changed, 27 insertions(+), 2 deletions(-) diff --git a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h index 1005d0b7926b..2945ba23810e 100644 --- a/samples/cxl_host_exerciser/cxl_he_cache_cmd.h +++ b/samples/cxl_host_exerciser/cxl_he_cache_cmd.h @@ -105,6 +105,7 @@ class he_cache_cmd : public he_cmd { ->transform(CLI::CheckedTransformer(he_cxl_device)) ->default_val("/dev/dfl-cxl-cache.0"); + // Set sride app->add_option("--stride", he_stide_, "Set stride value") ->transform(CLI::Range(0, 3))->default_val("0"); @@ -137,6 +138,9 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); + // Set Stride to 3 for FPGA read/write cache hit/miss + he_stide_ = 3; + cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -151,7 +155,10 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - rd_table_ctl_.enable_address_stride = 1; + if (he_stide_ > 0) { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stide_; + } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); // Allocate DSM buffer @@ -241,6 +248,9 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); + // Set Stride to 3 for FPGA read/write cache hit/miss + he_stide_ = 3; + cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -256,7 +266,10 @@ class he_cache_cmd : public he_cmd { // set RD_ADDR_TABLE_CTRL rd_table_ctl_.value = 0; - rd_table_ctl_.enable_address_stride = 1; + if (he_stide_ > 0) { + rd_table_ctl_.enable_address_stride = 1; + rd_table_ctl_.stride = he_stide_; + } host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); // Allocate DSM buffer @@ -296,6 +309,12 @@ class he_cache_cmd : public he_cmd { he_wr_cfg_.opcode = WR_LINE_M; host_exe_->write64(HE_WR_CONFIG, he_wr_cfg_.value); + // set RD_ADDR_TABLE_CTRL + he_rd_cfg_.value = 0; + host_exe_->write64(HE_RD_CONFIG, he_rd_cfg_.value); + rd_table_ctl_.value = 0; + host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value); + // Set WR_ADDR_TABLE_CTRL wr_table_ctl_.value = 0; if (he_stide_ > 0) { @@ -345,6 +364,9 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES); + // Set Stride to 3 for FPGA read/write cache hit/miss + he_stide_ = 3; + cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl; @@ -415,6 +437,9 @@ class he_cache_cmd : public he_cmd { he_info_.value = host_exe_->read64(HE_INFO); host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES); + // Set Stride to 3 for FPGA read/write cache hit/miss + he_stide_ = 0x3; + cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl; cout << "Line Repeat Count:" << he_linerep_count_ << endl; cout << "Read address table size:" << he_info_.read_addr_table_size << endl;