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@nakulkorde nakulkorde released this 17 Apr 00:59
· 3208 commits to master since this release
0.13.1
eb43f90

The Open Programmable Acceleration Engine is a software framework for managing and accessing programmable accelerators (FPGAs). Its main parts are:

  • The OPAE Software Development Kit (OPAE SDK),

  • the OPAE Linux driver for Intel(R) Xeon(R) CPU with FPGAs, and

  • the Basic Building Block (BBB) library for accelerating AFU
    development (not part of this release, but pre-release code is
    available [on GitHub)[https://github.com/OPAE/intel-fpga-bbb\]

OPAE is under active development to extend to more hardware platforms, as well as to build up the software stack with additional abstractions to enable more software developers.

The OPAE SDK is a collection of libraries and tools to facilitate the development of software applications and accelerators using OPAE. It provides a library implementing the OPAE C API for presenting a streamlined and easy-to-use interface for software applications to discover, access, and manage FPGA devices and accelerators using the OPAE software stack. The OPAE SDK also includes the AFU Simulation Environment (ASE) for end-to-end simulation of accelerator RTL together with software applications using the OPAE C API.

OPAE's goal is to accelerate FPGA adoption. It is a community effort to simplify the development and deployment of FPGA applications, so we explicitly welcome discussions and contributions! The OPAE SDK source, unless otherwise noted, is released under a BSD 3-clause license.

More information about OPAE can be found
at [http://01.org/OPAE]{.underline}.

Open Programmable Acceleration Engine (OPAE) 0.13.1 Release Notes

This document provides the Release Notes for the Open Programmable
Acceleration Engine (OPAE) 0.13.1 release.

System Compatibility

  • Hardware: tightly coupled FPGA products and programmable FPGA
    acceleration cards for Intel(R) Xeon(R) processors (to be released);
    Intel(R) PAC with Arria(R) 10 card

  • Operating System: tested on Red Hat Enterprise Linux 7.4, and CentOS
    7.4, with Linux kernels 3.10 through 4.7

  • Intel Programmable Acceleration Card (PAC) with Intel Arria® 10 GX FPGA (PCI ID: 0x09c4)
    FIM Version : 1.0.3 (1.0 Production)

Major Changes from 0.13.0 to 0.13.1

  • Refactor fpga internals

    • Change object_ID to object_id to be more consistent with other property names

    • Rename `sysfs_resource` to `sysfs_node` class

    • Default log to /tmp + error handling. This changes fpgainfo to log to /tmp directory but also adds exception handling in case the log file can't be opened. If that happens, it will log to stderr

  •  fpgabist:

    • Support identifying target card via "-b", "-d", and/or "-f" flags when multiple cards are present. If there is only one card on the system the tool will default to running on the only available fpga
    • Improve input parsing and output formatting

  • Define usage of flags to work with vhdla on ModelSim(use "-F") and
    VCS(use "-f").

  • Reduce amount of logging when interrupts are supported by hardware

  • hssi: fix help message for `send` command

Notes / Known Issues

  • A different OPN is used in the design examples

    The Intel Quartus Prime Pro Edition license uses a design example

    OPN of 10AX115N3F40E2SG, instead of the Intel PAC with Intel Arria
    10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact
    your design.

  • PCIe directed speed changes are not supported

    Only automatic down-training at boot time is supported

  • Virtual Function (VF) may fail to attach or detach when using the
    Linux Red Hat* 3.10 kernel

    This is a known issue with qemu/kvm and libvirt. Refer to the Red
    Hat* website for more information about this issue.

  • The Intel FPGA Dynamic Profiler Tool for OpenCL* GUI reports
    frequency and bandwidth incorrectly

    This issue will be resolved in a future version of the Intel
    Acceleration Stack.

  • fpgainfo may raise a UnicodeEncodeError when the Python*
    interpreter cannot determine what encoding to use

    This issue typically occurs when redirecting or piping output. The
    fpgabist tool calls fpgainfo and is also impacted.

    There are two workarounds for this issue:

  • Set the PYTHONENCODING environment variable to UTF-8.

  • Modify the fpgainfo script to force the use of UTF-8:

    -- Add an import codecs statement at the top of the file with the
    other import statements.

    -- Before the line that calls args.func(args), insert this comment and code line:

    # wrap stdout with the StreamWriter that does unicode
    sys.stdout = codecs.getwriter('UTF- 8')(sys.stdout)

  • When simulating the hello_intr_afu sample code, the
    af2cp_sTxPort.c1.hdr.rsvd2[5:4] has a value of X

    This issue will be resolved in the Intel Acceleration Stack 1.1
    version.

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