feat: organization

Signed-off-by: Michael Pollind <[email protected]>

Forge/Math/Internal/ScalarTypes.h

@@ -1,3 +1,6 @@
+#pragma once
+#ifndef TF_MATH_INTERNAL_SCALAR_TYPES_H
+#define TF_MATH_INTERNAL_SCALAR_TYPES_H
 
 
 struct float4
@@ -54,3 +57,6 @@ struct half3
 struct half4
 {
 };
+
+#endif
+

Forge/Math/Internal/SimdTypes.h

@@ -70,7 +70,7 @@ struct TSimdQuatFloat {
   TSimdFloat32x4 mValue; 
 };
 
-struct TSimdFloat1x4 {
+struct TSimdFloat4x1 {
     union
     {
         struct
@@ -81,7 +81,7 @@ struct TSimdFloat1x4 {
     };
 };
 
-struct TSimdFloat2x4
+struct TSimdFloat4x2
 {
     union
     {
@@ -94,7 +94,7 @@ struct TSimdFloat2x4
     };
 };
 
-struct TSimdFloat3x4 {
+struct TSimdFloat4x3 {
   union {
     struct {
       TSimdFloat32x4 mCol0; 
@@ -125,12 +125,16 @@ struct TSimdFloat3
   TSimdFloat32x3 mRow; 
 };
 
-struct TSimdFloat1x3
-{
-  TSimdFloat32x3 mCol0; 
+struct TSimdFloat3x1 {
+    union {
+        struct {
+            TSimdFloat32x3 mCol0;
+        };
+        TSimdFloat32x3 mCol[1];
+    };
 };
 
-struct TSimdFloat2x3
+struct TSimdFloat3x2
 {
     union
     {
@@ -161,15 +165,25 @@ struct TSimdFloat2 {
   TSimdFloat32x2 mRow; 
 };
 
-struct TSimdFloat1x2
+struct TSimdFloat2x1
 {
-  TSimdFloat32x2 mCol0; 
+    union {
+        struct {
+          TSimdFloat32x2 mCol0; 
+        };
+        TSimdFloat32x2 mCol[1];
+    };
 };
 
 struct TSimdFloat2x2
 {
-  TSimdFloat32x2 mCol0; 
-  TSimdFloat32x2 mCol1; 
+    union {
+        struct {
+            TSimdFloat32x2 mCol0;
+            TSimdFloat32x2 mCol1;
+        };
+        TSimdFloat32x2 mCol[2];
+    };
 };
 
 

Forge/Math/Internal/TF_Simd2x32_neon.inl → Forge/Math/Internal/TF_Simd32x2_neon.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_NEON
 #include "Forge/TF_Config.h"
-#include "../TF_Simd2x32.h"
+#include "../TF_Simd32x2.h"
 #endif
 
 inline TSimdInt32x2   tfSimd2iSelect(TSimdInt32x2 arg0, TSimdInt32x2 arg1, TSimdInt32x2 mask) { return vbsl_s32(mask, arg1, arg1); }

Forge/Math/Internal/TF_Simd2x32_scalar.inl → Forge/Math/Internal/TF_Simd32x2_scalar.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_SCALAR  
 #include "Forge/TF_Config.h"
-#include "../TF_Simd2x32.h"
+#include "../TF_Simd32x2.h"
 #endif
 
 inline TSimdInt32x2 tfSimd2iSelect(TSimdInt32x2 arg0, TSimdInt32x2 arg1, TSimdInt32x2 mask) {
@@ -152,3 +152,12 @@ inline bool tfSimd2iCmpAllEq(TSimdInt32x2 arg1, TSimdInt32x2 arg2) {
     }
     return true;
 }
+
+static inline bool tfSimdFloat32x2CmpAllLt(TSimdFloat32x2 arg1, TSimdFloat32x2 arg2) {
+    for (int i = 0; i < 2; i++) {
+        if (arg1.v[i] >= arg2.v[i]) {
+            return false;
+        }
+    }
+    return true;
+}

Forge/Math/Internal/TF_Simd2x32_sse.inl → Forge/Math/Internal/TF_Simd32x2_sse.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_SSE  
 #include "Forge/TF_Config.h"
-#include "../TF_Simd2x32.h"
+#include "../TF_Simd32x2.h"
 #endif
 
 inline TSimdInt32x2   tfSimd2iSelect(TSimdInt32x2 arg0, TSimdInt32x2 arg1, TSimdInt32x2 mask) { return _mm_blendv_epi8(arg0, arg1, mask); }
@@ -100,3 +100,9 @@ inline bool tfSimd2iCmpAllEq(TSimdInt32x2 arg1, TSimdInt32x2 arg2) {
     const TSimdInt32x2 compare = tfSimd2iCmpEq(arg1, arg2);
     return (_mm_movemask_epi8(compare) & 0b0011) == 0b0011;
 }
+
+static inline bool tfSimdFloat32x2CmpAllLt(TSimdFloat32x2 a, TSimdFloat32x2 b) {
+    TSimdFloat32x3 compare = tfSimd2fCmpLt(a, b);
+    return (_mm_movemask_ps(compare) & 0b0011) == 0b0011;
+}
+

Forge/Math/Internal/TF_Simd3x32_neon.inl → Forge/Math/Internal/TF_Simd32x3_neon.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_NEON
 #include "Forge/TF_Config.h"
-#include "../TF_Simd3x32.h"
+#include "../TF_Simd32x3.h"
 #endif
 
 inline TSimdInt32x3   tfSimd3iSelect(TSimdInt32x3 arg0, TSimdInt32x3 arg1, TSimdInt32x3 mask) { return vbslq_s32(mask, arg0, arg1); }

Forge/Math/Internal/TF_Simd3x32_scalar.inl → Forge/Math/Internal/TF_Simd32x3_scalar.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_SCALAR  
 #include "Forge/TF_Config.h"
-#include "../TF_Simd3x32.h"
+#include "../TF_Simd32x3.h"
 #endif
 
 inline TSimdInt32x3 tfSimd3iSelect(TSimdInt32x3 arg0, TSimdInt32x3 arg1, TSimdInt32x3 mask) {
@@ -120,8 +120,8 @@ inline TSimdFloat32x3 tfSimd3fAbs(TSimdFloat32x3 value) {
     };
 }
 
-inline TSimdFloat32x3 tfSimdFloat3Load(float x, float y, float z) { return { x, y, z }; }
-inline TSimdInt32x3 tfSimdInt3Load(int32_t x, int32_t y, int32_t z) { return { x, y, z }; }
+inline TSimdFloat32x3 tfSimdFloat3x32Load(float x, float y, float z) { return { x, y, z }; }
+inline TSimdInt32x3 tfSimdInt3x32Load(int32_t x, int32_t y, int32_t z) { return { x, y, z }; }
 
 inline TSimdFloat32x2 tfSimd3fToSimd2f(TSimdFloat32x3 value) { return { value.v[0], value.v[1] }; }
 
@@ -177,3 +177,25 @@ inline bool tfSimd3iCmpAllEq(TSimdInt32x3 arg1, TSimdInt32x3 arg2) {
     }
     return true;
 }
+
+static inline bool tfSimdFloat32x3CmpAllLt(TSimdFloat32x3 a, TSimdFloat32x3 b) {
+    for (int i = 0; i < 3; i++) {
+        if (a.v[i] >= b.v[i]) {
+            return false;
+        }
+    }
+    return true;
+}
+
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex0ByValue(TSimdFloat32x3 input, float value) {
+    return {value, input.v[1], input.v[2]};
+}
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex1ByValue(TSimdFloat32x3 input, float value){
+    return {input.v[0], value, input.v[2]};
+};
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex2ByValue(TSimdFloat32x3 input, float value){
+    return {input.v[0], input.v[1], value};
+};
+
+
+

Forge/Math/Internal/TF_Simd3x32_sse.inl → Forge/Math/Internal/TF_Simd32x3_sse.inl

@@ -1,7 +1,7 @@
 #if defined(__CLANGD__)
 #define TF_FEATURE_CPU_SSE  
 #include "Forge/TF_Config.h"
-#include "../TF_Simd3x32.h"
+#include "../TF_Simd32x3.h"
 #endif
 
 inline TSimdInt32x3   tfSimd3iSelect(TSimdInt32x3 arg0, TSimdInt32x3 arg1, TSimdInt32x3 mask) { return _mm_blendv_epi8(arg0, arg1, mask); }
@@ -38,15 +38,22 @@ inline TSimdFloat32x3 tfSimd3fClamp(TSimdFloat32x3 value, TSimdFloat32x3 min, TS
 }
 
 inline TSimdInt32x3 tfSimd3fToSimd3i(TSimdFloat32x3 value) { return _mm_castps_si128(value); }
-
 inline TSimdFloat32x3 tfSimd3iToSimd3f(TSimdInt32x3 value) { return _mm_castsi128_ps(value); }
 
 inline float tfSimd3fSelectIndex0(TSimdFloat32x3 value) { return _mm_cvtss_f32(value); }
-
 inline float tfSimd3fSelectIndex1(TSimdFloat32x3 value) { return tfSimd3fSelectIndex0(tfSimd3fSplatIndex1(value)); }
-
 inline float tfSimd3fSelectIndex2(TSimdFloat32x3 value) { return tfSimd3fSelectIndex0(tfSimd3fSplatIndex2(value)); }
 
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex0ByValue(TSimdFloat32x3 input, float value) {
+    return _mm_blend_ps(input, tfSimd3fSplat(value), 0b0001);
+}
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex1ByValue(TSimdFloat32x3 input, float value) {
+    return _mm_blend_ps(input, tfSimd3fSplat(value), 0b0010);
+}
+static inline TSimdFloat32x3 tfSimdFloat3x32ReplaceIndex2ByValue(TSimdFloat32x3 input, float value) {
+    return _mm_blend_ps(input, tfSimd3fSplat(value), 0b0100);
+}
+
 inline TSimdFloat32x3 tfSimd3fAdd(TSimdFloat32x3 arg1, TSimdFloat32x3 arg2) { return _mm_add_ps(arg1, arg2); }
 inline TSimdFloat32x3 tfSimd3fSub(TSimdFloat32x3 arg1, TSimdFloat32x3 arg2) { return _mm_sub_ps(arg1, arg2); }
 inline TSimdFloat32x3 tfSimd3fMul(TSimdFloat32x3 arg1, TSimdFloat32x3 arg2) { return _mm_mul_ps(arg1, arg2); }
@@ -64,9 +71,8 @@ inline TSimdFloat32x3 tfSimd3fAbs(TSimdFloat32x3 value) {
     return _mm_and_ps(value, signMask);
 }
 
-inline TSimdFloat32x3 tfSimdFloat3Load(float x, float y, float z) { return _mm_set_ps(0.0f, z, y, x); }
-
-inline TSimdInt32x3 tfSimdInt3Load(int32_t x, int32_t y, int32_t z) { return _mm_set_epi32(0.0f, x, y, z); }
+inline TSimdFloat32x3 tfSimdFloat3x32Load(float x, float y, float z) { return _mm_set_ps(0.0f, z, y, x); }
+inline TSimdInt32x3 tfSimdInt3x32Load(int32_t x, int32_t y, int32_t z) { return _mm_set_epi32(0.0f, x, y, z); }
 
 inline TSimdFloat32x2 tfSimd3fToSimd2f(TSimdFloat32x3 value) { return value; }
 
@@ -78,7 +84,7 @@ inline TSimdFloat32x3 tfSimd3fSplatIndex0(TSimdFloat32x3 value) { return _mm_shu
 inline TSimdFloat32x3 tfSimd3fSplatIndex1(TSimdFloat32x3 value) { return _mm_shuffle_ps(value, value, _MM_SHUFFLE(1, 1, 1, 1)); }
 inline TSimdFloat32x3 tfSimd3fSplatIndex2(TSimdFloat32x3 value) { return _mm_shuffle_ps(value, value, _MM_SHUFFLE(2, 2, 2, 2)); }
 
-inline TSimdInt32x3 tfSimd3iSplat(int32_t value) { return _mm_set1_epi32(value); }
+inline TSimdInt32x3   tfSimd3iSplat(int32_t value) { return _mm_set1_epi32(value); }
 inline TSimdFloat32x3 tfSimd3fSplat(float value) { return _mm_set1_ps(value); }
 
 inline TSimdInt32x3 tfSimd3iCmpEq(TSimdInt32x3 arg1, TSimdInt32x3 arg2) { return _mm_cmpeq_epi32(arg1, arg2); }
@@ -97,8 +103,12 @@ inline bool tfSimd3fCmpAllEq(TSimdFloat32x3 arg1, TSimdFloat32x3 arg2) {
     TSimdFloat32x3 compare = tfSimd3fCmpEq(arg1, arg2);
     return (_mm_movemask_ps(compare) & 0b0111) == 0b0111;
 }
-
 inline bool tfSimd3iCmpAllEq(TSimdInt32x3 arg1, TSimdInt32x3 arg2) {
     const TSimdInt32x3 compare = tfSimd3iCmpEq(arg1, arg2);
     return (_mm_movemask_epi8(compare) & 0b0111) == 0b0111;
 }
+static inline bool tfSimdFloat32x3CmpAllLt(TSimdFloat32x3 a, TSimdFloat32x3 b) {
+    TSimdFloat32x3 compare = tfSimd3fCmpLt(a, b);
+    return (_mm_movemask_ps(compare) & 0b0111) == 0b0111;
+}
+