From 9e9d671e7f39fc9160ea301151a57d67b9a176d9 Mon Sep 17 00:00:00 2001 From: Haojin Tang Date: Tue, 18 Feb 2025 15:51:24 +0800 Subject: [PATCH] build: bump to chisel 6 and fix deprecation warning --- Makefile | 8 ++--- build.sc | 33 ++++++++----------- rocket-chip | 2 +- src/main/scala/huancun/DataStorage.scala | 8 ++--- src/main/scala/huancun/HuanCun.scala | 4 +-- src/main/scala/huancun/Slice.scala | 1 + .../huancun/utils/CustomAnnotations.scala | 19 ++++++----- src/test/scala/huancun/AllocatorTest.scala | 2 +- src/test/scala/huancun/DSTest.scala | 2 +- src/test/scala/huancun/L2Tester.scala | 5 ++- src/test/scala/huancun/TestTop.scala | 15 ++++++--- .../scala/huancun/tlctest/RandomTester.scala | 4 +-- 12 files changed, 52 insertions(+), 51 deletions(-) diff --git a/Makefile b/Makefile index 29fa590d..5ffe1734 100644 --- a/Makefile +++ b/Makefile @@ -10,16 +10,16 @@ test: test-top-l2: - mill -i HuanCun.test.runMain huancun.TestTop_L2 -td build + mill -i HuanCun.test.runMain huancun.TestTop_L2 -td build --target systemverilog --split-verilog test-top-l2standalone: - mill -i HuanCun.test.runMain huancun.TestTop_L2_Standalone -td build + mill -i HuanCun.test.runMain huancun.TestTop_L2_Standalone -td build --target systemverilog --split-verilog test-top-l2l3: - mill -i HuanCun.test.runMain huancun.TestTop_L2L3 -td build + mill -i HuanCun.test.runMain huancun.TestTop_L2L3 -td build --target systemverilog --split-verilog test-top-fullsys: - mill -i HuanCun.test.runMain huancun.TestTop_FullSys -td build + mill -i HuanCun.test.runMain huancun.TestTop_FullSys -td build --target systemverilog --split-verilog basic-test: mill -i HuanCun.test.testOnly -o -s huancun.ConnectionTester diff --git a/build.sc b/build.sc index 8f59c09b..faeaa9bc 100644 --- a/build.sc +++ b/build.sc @@ -6,31 +6,24 @@ import $file.`rocket-chip`.common import $file.`rocket-chip`.cde.common import $file.`rocket-chip`.hardfloat.common -val defaultVersions = Map( - "chisel3" -> "3.6.0", - "chisel3-plugin" -> "3.6.0", - "chiseltest" -> "0.6.2", - "scala" -> "2.13.10", -) +val defaultScalaVersion = "2.13.15" -def getVersion(dep: String, org: String = "edu.berkeley.cs", cross: Boolean = false) = { - val version = sys.env.getOrElse(dep + "Version", defaultVersions(dep)) - if (cross) - ivy"$org:::$dep:$version" - else - ivy"$org::$dep:$version" -} +def defaultVersions = Map( + "chisel" -> ivy"org.chipsalliance::chisel:6.6.0", + "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.6.0", + "chiseltest" -> ivy"edu.berkeley.cs::chiseltest:6.0.0" +) trait HasChisel extends ScalaModule { def chiselModule: Option[ScalaModule] = None def chiselPluginJar: T[Option[PathRef]] = None - def chiselIvy: Option[Dep] = Some(getVersion("chisel3")) + def chiselIvy: Option[Dep] = Some(defaultVersions("chisel")) - def chiselPluginIvy: Option[Dep] = Some(getVersion("chisel3-plugin", cross=true)) + def chiselPluginIvy: Option[Dep] = Some(defaultVersions("chisel-plugin")) - override def scalaVersion = defaultVersions("scala") + override def scalaVersion = defaultScalaVersion override def scalacOptions = super.scalacOptions() ++ Agg("-language:reflectiveCalls", "-Ymacro-annotations", "-Ytasty-reader") @@ -45,9 +38,9 @@ object rocketchip extends `rocket-chip`.common.RocketChipModule with HasChisel { val rcPath = os.pwd / "rocket-chip" override def millSourcePath = rcPath - def mainargsIvy = ivy"com.lihaoyi::mainargs:0.5.0" + def mainargsIvy = ivy"com.lihaoyi::mainargs:0.7.0" - def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.5" + def json4sJacksonIvy = ivy"org.json4s::json4s-jackson:4.0.7" object macros extends `rocket-chip`.common.MacrosModule with HasChisel { def scalaReflectIvy = ivy"org.scala-lang:scala-reflect:${scalaVersion}" @@ -87,8 +80,10 @@ object HuanCun extends SbtModule with HasChisel with millbuild.common.HuanCunMod object test extends SbtModuleTests with TestModule.ScalaTest { override def ivyDeps = super.ivyDeps() ++ Agg( - getVersion("chiseltest"), + defaultVersions("chiseltest"), ) } + override def scalacOptions = super.scalacOptions() ++ Agg("-deprecation", "-feature") + } diff --git a/rocket-chip b/rocket-chip index e64b744b..90ae9a93 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit e64b744b1490992bd038aaf9ca628f0e29fa0e59 +Subproject commit 90ae9a9314d444ade097fd5a471916869559b4fd diff --git a/src/main/scala/huancun/DataStorage.scala b/src/main/scala/huancun/DataStorage.scala index 06f9a0be..14d264ed 100644 --- a/src/main/scala/huancun/DataStorage.scala +++ b/src/main/scala/huancun/DataStorage.scala @@ -246,10 +246,10 @@ class DataStorage(implicit p: Parameters) extends HuanCunModule { dataSel.io.en(1) := io.sourceC_raddr.fire } - io.sourceD_rdata.data := Cat(dataSelModules.map(_.io.out(0)).reverse) - io.sourceD_rdata.corrupt := Cat(dataSelModules.map(_.io.err_out(0))).orR - io.sourceC_rdata.data := Cat(dataSelModules.map(_.io.out(1)).reverse) - io.sourceC_rdata.corrupt := Cat(dataSelModules.map(_.io.err_out(1))).orR + io.sourceD_rdata.data := Cat(dataSelModules.map(_.io.out(0)).reverse.toIndexedSeq) + io.sourceD_rdata.corrupt := Cat(dataSelModules.map(_.io.err_out(0)).toIndexedSeq).orR + io.sourceC_rdata.data := Cat(dataSelModules.map(_.io.out(1)).reverse.toIndexedSeq) + io.sourceC_rdata.corrupt := Cat(dataSelModules.map(_.io.err_out(1)).toIndexedSeq).orR val d_addr_reg = RegNextN(io.sourceD_raddr.bits, sramLatency) val c_addr_reg = RegNextN(io.sourceC_raddr.bits, sramLatency) diff --git a/src/main/scala/huancun/HuanCun.scala b/src/main/scala/huancun/HuanCun.scala index cde21093..123c369f 100644 --- a/src/main/scala/huancun/HuanCun.scala +++ b/src/main/scala/huancun/HuanCun.scala @@ -265,8 +265,8 @@ class HuanCun(implicit p: Parameters) extends LazyModule with HasHuanCunParamete val sizeBytes = cacheParams.toCacheParams.capacity.toDouble def sizeBytesToStr(sizeBytes: Double): String = sizeBytes match { - case _ if sizeBytes >= 1024 * 1024 => (sizeBytes / 1024 / 1024) + "MB" - case _ if sizeBytes >= 1024 => (sizeBytes / 1024) + "KB" + case _ if sizeBytes >= 1024 * 1024 => s"${sizeBytes / 1024 / 1024}MB" + case _ if sizeBytes >= 1024 => s"${sizeBytes / 1024}KB" case _ => "B" } val sizeStr = sizeBytesToStr(sizeBytes) diff --git a/src/main/scala/huancun/Slice.scala b/src/main/scala/huancun/Slice.scala index 5c0df2df..8f9de398 100644 --- a/src/main/scala/huancun/Slice.scala +++ b/src/main/scala/huancun/Slice.scala @@ -19,6 +19,7 @@ package huancun +import scala.language.existentials import org.chipsalliance.cde.config.Parameters import chisel3._ import chisel3.util._ diff --git a/src/main/scala/huancun/utils/CustomAnnotations.scala b/src/main/scala/huancun/utils/CustomAnnotations.scala index 42582045..73bad1e9 100644 --- a/src/main/scala/huancun/utils/CustomAnnotations.scala +++ b/src/main/scala/huancun/utils/CustomAnnotations.scala @@ -1,30 +1,31 @@ package huancun.utils -import firrtl.annotations.{Annotation, ModuleName, Named, SingleTargetAnnotation} import chisel3._ import chisel3.experimental.ChiselAnnotation -case class SRAMClkDivBy2Annotation(mod: ModuleName) extends SingleTargetAnnotation[ModuleName] { - override val target: ModuleName = mod +case class SRAMClkDivBy2Annotation(mod: firrtl.annotations.ModuleName) + extends firrtl.annotations.SingleTargetAnnotation[firrtl.annotations.ModuleName] { + override val target: firrtl.annotations.ModuleName = mod - override def duplicate(n: ModuleName): Annotation = this.copy(n) + override def duplicate(n: firrtl.annotations.ModuleName): firrtl.annotations.Annotation = this.copy(n) } -case class SRAMSpecialDepthAnnotation(mod: ModuleName) extends SingleTargetAnnotation[ModuleName] { - override val target: ModuleName = mod +case class SRAMSpecialDepthAnnotation(mod: firrtl.annotations.ModuleName) + extends firrtl.annotations.SingleTargetAnnotation[firrtl.annotations.ModuleName] { + override val target: firrtl.annotations.ModuleName = mod - override def duplicate(n: ModuleName): Annotation = this.copy(n) + override def duplicate(n: firrtl.annotations.ModuleName): firrtl.annotations.Annotation = this.copy(n) } object CustomAnnotations { def annotateClkDivBy2(mod: Module) = { chisel3.experimental.annotate(new ChiselAnnotation { - override def toFirrtl: Annotation = SRAMClkDivBy2Annotation(mod.toNamed) + override def toFirrtl: firrtl.annotations.Annotation = SRAMClkDivBy2Annotation(mod.toNamed) }) } def annotateSpecialDepth(mod: Module) = { chisel3.experimental.annotate(new ChiselAnnotation { - override def toFirrtl: Annotation = SRAMSpecialDepthAnnotation(mod.toNamed) + override def toFirrtl: firrtl.annotations.Annotation = SRAMSpecialDepthAnnotation(mod.toNamed) }) } } diff --git a/src/test/scala/huancun/AllocatorTest.scala b/src/test/scala/huancun/AllocatorTest.scala index 6a616b6d..7e76463b 100644 --- a/src/test/scala/huancun/AllocatorTest.scala +++ b/src/test/scala/huancun/AllocatorTest.scala @@ -8,7 +8,7 @@ import freechips.rocketchip.tilelink.{BankBinder, TLCacheCork, TLFuzzer, TLRAM, class AllocatorTest extends L2Tester { val system = LazyModule(new ExampleSystem()) - chisel3.stage.ChiselStage.elaborate(system.module) + circt.stage.ChiselStage.convert(system.module) val mshrAlloc = chisel3.aop.Select.collectDeep[MSHRAlloc](system.module){ case alloc: MSHRAlloc => diff --git a/src/test/scala/huancun/DSTest.scala b/src/test/scala/huancun/DSTest.scala index 62a4d56a..dcb53cfb 100644 --- a/src/test/scala/huancun/DSTest.scala +++ b/src/test/scala/huancun/DSTest.scala @@ -6,7 +6,7 @@ import freechips.rocketchip.diplomacy.LazyModule class DSTest extends L2Tester { val system = LazyModule(new ExampleSystem()) - chisel3.stage.ChiselStage.elaborate(system.module) + circt.stage.ChiselStage.convert(system.module) val datastorage = chisel3.aop.Select.collectDeep[DataStorage](system.module){ case ds: DataStorage => diff --git a/src/test/scala/huancun/L2Tester.scala b/src/test/scala/huancun/L2Tester.scala index 9a6263ae..23fce887 100644 --- a/src/test/scala/huancun/L2Tester.scala +++ b/src/test/scala/huancun/L2Tester.scala @@ -5,15 +5,14 @@ import org.chipsalliance.cde.config.Config import chiseltest._ import chiseltest.{VerilatorBackendAnnotation, WriteVcdAnnotation} import chiseltest.simulator.{VerilatorCFlags, VerilatorFlags} -import firrtl.AnnotationSeq -import firrtl.stage.RunFirrtlTransformAnnotation +import firrtl2.AnnotationSeq import org.scalatest.flatspec._ import org.scalatest.matchers.should._ import huancun.prefetch._ abstract class L2Tester extends AnyFlatSpec with ChiselScalatestTester with Matchers with HasTestAnnos { behavior of "L2" - implicit val defaultConfig = new Config((_, _, _) => { + implicit val defaultConfig: Config = new Config((_, _, _) => { case HCCacheParamsKey => HCCacheParameters( prefetch = Some(BOPParameters()),// None, inclusive = false, diff --git a/src/test/scala/huancun/TestTop.scala b/src/test/scala/huancun/TestTop.scala index f0517bd9..5b0fee66 100644 --- a/src/test/scala/huancun/TestTop.scala +++ b/src/test/scala/huancun/TestTop.scala @@ -1,11 +1,12 @@ package huancun import chisel3._ +import circt.stage.{ChiselStage, FirtoolOption} import chisel3.util._ import utility._ import huancun.debug._ import org.chipsalliance.cde.config._ -import chisel3.stage.{ChiselGeneratorAnnotation, ChiselStage} +import chisel3.stage.ChiselGeneratorAnnotation import freechips.rocketchip.util._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ @@ -526,7 +527,8 @@ object TestTop_L2 extends App { val top = DisableMonitors(p => LazyModule(new TestTop_L2()(p)) )(config) (new ChiselStage).execute(args, Seq( - ChiselGeneratorAnnotation(() => top.module) + ChiselGeneratorAnnotation(() => top.module), + FirtoolOption("--disable-annotation-unknown") )) ChiselDB.addToFileRegisters FileRegisters.write(fileDir = "./build") @@ -544,7 +546,8 @@ object TestTop_L2_Standalone extends App { val top = DisableMonitors(p => LazyModule(new TestTop_L2_Standalone()(p)) )(config) (new ChiselStage).execute(args, Seq( - ChiselGeneratorAnnotation(() => top.module) + ChiselGeneratorAnnotation(() => top.module), + FirtoolOption("--disable-annotation-unknown") )) ChiselDB.addToFileRegisters FileRegisters.write(fileDir = "./build") @@ -562,7 +565,8 @@ object TestTop_L2L3 extends App { (new ChiselStage).execute(args, Seq( - ChiselGeneratorAnnotation(() => top.module) + ChiselGeneratorAnnotation(() => top.module), + FirtoolOption("--disable-annotation-unknown") )) ChiselDB.addToFileRegisters FileRegisters.write(fileDir = "./build") @@ -579,7 +583,8 @@ object TestTop_FullSys extends App { val top = DisableMonitors( p => LazyModule(new TestTop_FullSys()(p)) )(config) (new ChiselStage).execute(args, Seq( - ChiselGeneratorAnnotation(() => top.module) + ChiselGeneratorAnnotation(() => top.module), + FirtoolOption("--disable-annotation-unknown") )) ChiselDB.addToFileRegisters FileRegisters.write(fileDir = "./build") diff --git a/src/test/scala/huancun/tlctest/RandomTester.scala b/src/test/scala/huancun/tlctest/RandomTester.scala index 3e91137e..81d2e1fe 100644 --- a/src/test/scala/huancun/tlctest/RandomTester.scala +++ b/src/test/scala/huancun/tlctest/RandomTester.scala @@ -15,11 +15,11 @@ trait RandomSampleUtil { } final def sample[A](dist: Map[A, Double], r: scala.util.Random): A = { - val p = r.nextDouble + val p = r.nextDouble() val it = dist.iterator var accum = 0.0 while (it.hasNext) { - val (item, itemProb) = it.next + val (item, itemProb) = it.next() accum += itemProb if (accum >= p) return item // return so that we don't have to search through the whole distribution