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PyHDI / veriloggen Public

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Add OpenLane Support #53

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mu2519 wants to merge 16 commits into PyHDI:develop

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Add OpenLane Support #53

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first ASIC support

mu2519 Feb 15, 2023

Improved API for configuration generation

mu2519 Feb 15, 2023

Added simulator and fixed bugs

mu2519 Feb 15, 2023

Changed code for backward compatibility

mu2519 Feb 16, 2023

Added one example for ASIC

mu2519 Feb 16, 2023

Added rectpack to dependencies

mu2519 Feb 16, 2023

mu2519 Feb 16, 2023

Modified the root conftest.py

mu2519 Feb 20, 2023

Added .coveragerc

mu2519 Feb 20, 2023

Added a test case for veriloggen.asic.sram

mu2519 Feb 20, 2023

Modified pytest.ini, setup.py, and conftest.py to improve testing

mu2519 Feb 20, 2023

Added a test case for a configuration file checker

mu2519 Feb 21, 2023

Added a test case for matrix multiplication with ASIC

mu2519 Mar 5, 2023

Fixed a problem

mu2519 Mar 5, 2023

Merge branch 'PyHDI:develop' into feature-asic

mu2519 Mar 25, 2023

Removed a meaningless file

mu2519 Mar 25, 2023

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mu2519 committed Mar 25, 2023

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