From 8dd1c57096a95130cd423e28211cad83fa28b5b2 Mon Sep 17 00:00:00 2001 From: coolbreeze413 Date: Tue, 12 Nov 2024 01:50:58 +0530 Subject: [PATCH] bitstream generation is not skipped now, even if flat_routing is enabled --- src/Compiler/CompilerOpenFPGA_ql.cpp | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/Compiler/CompilerOpenFPGA_ql.cpp b/src/Compiler/CompilerOpenFPGA_ql.cpp index 9982a1075..a09a66792 100644 --- a/src/Compiler/CompilerOpenFPGA_ql.cpp +++ b/src/Compiler/CompilerOpenFPGA_ql.cpp @@ -4468,15 +4468,16 @@ bool CompilerOpenFPGA_ql::GenerateBitstream() { return true; } - // if flat_routing is enabled in VPR, skip bitstream generation - // OpenFPGA does not support bitstream generation with flat_routing (yet) - // ref: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2256#issuecomment-1498007179 - if( QLSettingsManager::getStringValue("vpr", "route", "flat_routing") == "checked" ) { - Message("##################################################"); - Message("Skipping Bitstream Generation since flat_routing is enabled in VPR!"); - Message("##################################################"); - return true; - } + // flat_routing enabled should be able to generate bitstream with updated OpenFPGA/vpr 11NOV2024. + // // if flat_routing is enabled in VPR, skip bitstream generation + // // OpenFPGA does not support bitstream generation with flat_routing (yet) + // // ref: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2256#issuecomment-1498007179 + // if( QLSettingsManager::getStringValue("vpr", "route", "flat_routing") == "checked" ) { + // Message("##################################################"); + // Message("Skipping Bitstream Generation since flat_routing is enabled in VPR!"); + // Message("##################################################"); + // return true; + // } #if UPSTREAM_UNUSED if (BitsOpt() == BitstreamOpt::EnableSimulation) {