From d58e6c603632c91f5349215cae8352090bc994f8 Mon Sep 17 00:00:00 2001 From: coolbreeze413 Date: Thu, 5 Dec 2024 20:51:57 +0530 Subject: [PATCH] skip bitstream generation if flat routing is enabled --- src/Compiler/CompilerOpenFPGA_ql.cpp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/Compiler/CompilerOpenFPGA_ql.cpp b/src/Compiler/CompilerOpenFPGA_ql.cpp index f9f6a9d27..e53c9c381 100644 --- a/src/Compiler/CompilerOpenFPGA_ql.cpp +++ b/src/Compiler/CompilerOpenFPGA_ql.cpp @@ -4555,6 +4555,17 @@ bool CompilerOpenFPGA_ql::GenerateBitstream() { return true; } + + // if flat_routing is enabled in VPR, skip bitstream generation + // OpenFPGA does not support bitstream generation with flat_routing (fully, yet) + // ref: https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2256#issuecomment-1498007179 + if( QLSettingsManager::getStringValue("vpr", "route", "flat_routing") == "checked" ) { + Message("##################################################"); + Message("Skipping Bitstream Generation since flat_routing is enabled in VPR!"); + Message("##################################################"); + return true; + } + #if UPSTREAM_UNUSED if (BitsOpt() == BitstreamOpt::EnableSimulation) { std::filesystem::path bit_path =