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sdf errors during load #377

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kkumar23 opened this issue Jun 21, 2021 · 0 comments
Open

sdf errors during load #377

kkumar23 opened this issue Jun 21, 2021 · 0 comments
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@mkurc-ant
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@kkumar23
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kkumar23 commented Jun 21, 2021 •
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sdf shows errors while loading in questasim. Where as iverilog its fine.

Take any designs and run post -layout simulation with sdf file. It shows below error in questa/modelsim.

Error (suppressible): (vsim-SDF-12090) D:/Open_core/Releases/testing/counter/build/counter_post_synthesis.sdf(319): Failed to find matching specify timing constraint for SETUP.
Error (suppressible): (vsim-SDF-12090) D:/Open_core/Releases/testing/counter/build/counter_post_synthesis.sdf(320): Failed to find matching specify timing constraint for SETUP.
Error (suppressible): (vsim-SDF-12090) D:/Open_core/Releases/testing/counter/build/counter_post_synthesis.sdf(321): Failed to find matching specify timing constraint for SETUP.
@kkumar23 kkumar23 added the bug Something isn't working label Jul 8, 2021
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