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x86 Live View.html
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<html>
<head>
<title>x86-Disassembler (Intel/AMD/Other).</title>
<meta property="og:image" content="https://repository-images.githubusercontent.com/25504860/fa13ff80-65fc-11ea-82a9-44a6ba3079b7" />
</head>
<body onload="setup()">
<script type="text/javascript" src="x86/dis-x86.js"></script>
<script type="text/javascript">
function setup()
{
coreType = document.getElementById("coreType");
//Update disassembler controls to the current default settings.
if( core.bitMode == 0 ) { document.getElementById("B16").checked = true; }
if( core.bitMode == 1 ) { document.getElementById("B32").checked = true; }
if( core.bitMode == 2 ) { document.getElementById("B64").checked = true; }
//Hex, and position display modes.
document.getElementById("DHex").checked = core.showInstructionHex;
document.getElementById("DPos").checked = core.showInstructionPos;
//Update base position, and disassemble the 64 bit sample code.
updateBase(); decode(document.getElementById('T').value);
}
function decode(e)
{
//Read the X86 hex code entered by user.
var Hex = e.replace(/\n|\r\n|\r/g, ""); //Remove enters.
Hex = Hex.replace(/ /g, ""); //Remove spaces.
//Load the Hex string into the Disassembler.
if (core.loadBinCode(Hex)) //Check if loaded correctly.
{
//Clear error output.
document.getElementById("ERR").innerHTML = "";
//Use the Linear Disassemble algorithm, for the Section of binary.
out = core.disassemble();
//Update the disassemble output.
document.getElementById("DisAsm").value = out;
}
//else the hex input is bad.
else
{
document.getElementById("ERR").innerHTML = "<hr />Only numbers 0 though 9, and alphabetical letters A to F are allowed. Any other characters will result in invalid instructions.";
}
//Reset the base position.
updateBase();
}
//Updates the disassembly output when a setting changes.
function update()
{
//8086 binary mode 16 bit, and up to X86-64.
if( document.getElementById("B16").checked ) { core.bitMode = 0; updateBase(); }
if( document.getElementById("B32").checked ) { core.bitMode = 1; updateBase(); }
if( document.getElementById("B64").checked ) { core.bitMode = 2; updateBase(); }
//Hex, and position display modes.
core.showInstructionHex = document.getElementById("DHex").checked;
core.showInstructionPos = document.getElementById("DPos").checked;
//Decode the binary with the new settings.
decode(document.getElementById('T').value);
}
//Update Base Position.
function updateBase()
{
//Get the Base address for the binary based on the base address entered by user.
var CodeSegment = document.getElementById("CS").value;
var Offset = document.getElementById("RIP").value;
//Set the position the binary is read from.
core.setBasePosition(CodeSegment + ":" + Offset);
//Depending on format 8086 (X86-16), 386 (X86-32), and X86-64 Instruction Pointer Size changes.
var P = core.getBasePosition().split(":"); //Split code segment, and instruction offset separator.
var Offset = P[P.length - 1]; //Read the last element for the Instruction pointer.
var Seg = (document.getElementById("CS").value).slice(-4);
//If segment is read set it as Seg.
if (P.length == 2)
{
Seg = P[0];
}
//The Instruction offset size is the Instruction pointer size.
if (Offset.length == 16)
{
document.getElementById("XIP").innerHTML = "RIP:";
}
else if (Offset.length == 8)
{
document.getElementById("XIP").innerHTML = "EIP:";
}
else
{
document.getElementById("XIP").innerHTML = "IP:";
}
document.getElementById("RIP").value = Offset; //Update the instruction pointer size based on CPU format type.
document.getElementById("CS").value = Seg; //Update the CodeSegment.
}
function help( h )
{
if( h === 0 )
{
alert("x86 is a family of backwards compatible instruction set architectures. Which means there should be no conflicts, but they are only minor.\r\n\
If the CPU is not listed in compatibility modes. Then the code is compatible with the Full X86 architecture mode. For more information on what each compatibility mode effects click the technical info buttons.\r\n\
*There are very few conflicting instructions through all X86 cores. You should only set compatibility mode if you know the code is designed for one of the conflicting architectures otherwise everything else matches the X86 architecture code standard.");
}
if( h === 1 )
{
var win = window.open("", "X86", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "Enables decoding of all binary instructions. This is the proper setting if the CPU is not listed in compatibility mode. Meaning the architecture is fully backwards comparable from the modern architecture.<br /><br />\
x86 is a family of backwards compatible instruction set architectures with almost full backwards compatibility.<br /><br />\
However not all processors match the modern X86 architecture encoding perfectly. Which is the reason for compatibility modes settings.";
}
if( h === 2 )
{
var win = window.open("", "K1OM", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "Knights Corner compatibility mode corrects VEX encoded Mask instructions that are different in Knights landing, and Xeon Phi.<br /><br />\
VEX mask instruction 41 can be encoded 4 ways in knights landing, and later.<br /><br />\
C4E17941C0 is KANDB K0,K0,K0<br />\
C4E17841C0 is KANDW K0,K0,K0<br />\
C4E1F941C0 is KANDD K0,K0,K0<br />\
C4E1F841C0 is KANDQ K0,K0,K0<br /><br />\
In knights corner variable size controlled mask did not exist KAND[B|W|D|Q], and also the Vector encoded mask register does not exist.<br />\
In knights corner the same instructions are decoded as follows.<br /><br />\
C4E17941C0 is KAND K0,K0<br />\
C4E17841C0 is KAND K0,K0<br />\
C4E1F941C0 is KAND K0,K0<br />\
C4E1F841C0 is KAND K0,K0<br /><br />\
The mask instructions are adjusted to there proper decoding.<br /><br />\
KAND[B|W|D|Q] is adjusted to KAND.<br />\
KANDN[B|W|D|Q] is adjusted to KANDN.<br />\
KNOT[B|W|D|Q] is adjusted to KNOT.<br />\
KOR[B|W|D|Q] is adjusted to KOR.<br />\
KXNOR[B|W|D|Q] is adjusted to KXNOR.<br />\
KXOR[B|W|D|Q] is adjusted to KXOR.<br />\
KMOV[B|W|D|Q] is adjusted to KMOV.<br />\
KORTEST[B|W|D|Q] is adjusted to KORTEST.<br /><br />\
The Jump with mask register instructions.<br /><br />\
C5 F8 84 00 00 00 00 = VJKZD K0,0000000000000007<br />\
C5 F8 85 00 00 00 00 = VJKNZD K0,0000000000000007<br /><br />\
Semi Conflicts with the jump instructions.<br /><br />\
66 0F 84 00 00 = JE 0000000000000005<br />\
66 0F 85 00 00 = JNE 0000000000000005<br /><br />\
These tow jump instructions are still enclosable with K1OM set active.<br /><br />\
0F 84 00 00 00 00 = JE 0000000000000006<br />\
0F 85 00 00 00 00 = JNE 0000000000000006<br /><br />\
Just they can not be adjust to 16 bit in size with K1OM active.<br /><br />\
Lastly the instruction encoding's used by knights corner using the MVEX encoding is distinguishable from the EVEX encoding used by the Knights landing processor and later without error. \
The only instructions that cause an problem for knights corner support are above.<br /><br />\
The full Knights corner instruction set is supported under the \"Full X86 Architecture\" compatibility mode. Just that enabling the \"Knights corner\" compatibility mode will correct the mask instruction problem.";
}
if( h === 3 )
{
var win = window.open("", "L1OM", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "The Intel Larrabee co-processor is fully supported by this dissembler without having to set Larrabee compatibility mode.<br />\
Except there are an few special Larrabee instructions that use the Knights corner, and Knights landing vector format.<br />\
Enabling Larrabee compatibility mode will enable Larrabee mask, and memory instructions listed bellow.<br /><br />\
62E0C0 = BSFI RAX,RAX<br />\
62E1C0 = BSRI RAX,RAX<br />\
62E2C0 = BSFF RAX,RAX<br />\
62E3C0 = BSRF RAX,RAX<br />\
62E4C0 = BITINTERLEAVE11 RAX,RAX<br />\
62E5C0 = BITINTERLEAVE21 RAX,RAX<br />\
62E6C011116677 = INSERTFIELD RAX,RAX,1111,66,77<br />\
62E7C011116677 = ROTATEFIELD RAX,RAX,1111,66,77<br />\
62E8C0 = COUNTBITS RAX,RAX<br />\
62E9C0 = QUADMASK16 RAX,RAX<br />\
62CB00 = VPREFETCH1 [RAX]<br />\
62CB08 = VPREFETCH2 [RAX]<br />\
62EB00 = CLEVICT1 [RAX]<br />\
62EB08 = CLEVICT2 [RAX]<br />\
62EB10 = LDVXCSR DWORD PTR [RAX]<br />\
62EB18 = STVXCSR DWORD PTR [RAX]<br />\
62FBC0 = VKMOVLHB K0,K0<br />\
62DCC0 = VKMOV EAX,K0<br />\
62ECC0 = VKMOV K0,EAX<br />\
62FCC0 = VKMOV K0,K0<br />\
62CDC0 = VKAND K0,K0<br />\
62DDC0 = VKANDN K0,K0<br />\
62EDC0 = VKANDNR K0,K0<br />\
62FDC0 = VKNOT K0,K0<br />\
62CEC0 = VKOR K0,K0<br />\
62DEC0 = VKORTEST K0,K0<br />\
62EEC0 = VKXOR K0,K0<br />\
62FEC0 = VKXNOR K0,K0<br />\
62DFC0 = DELAY R8D<br />\
62DFC8 = SPFLT R9D<br />\
62EFC0 = VKSWAPB K0,K0<br /><br />\
Once the above instructions are enabled the dissembler will not decode AVX512 code anymore, for Knights corner, or Knights landing and later.<br />\
However Larrabee vector instructions decode without Larrabee compatibility mode. Bellow is an few sample Larrabee vector instructions.<br /><br />\
D600016200 = VMADD213PS V0{K1},V0,[RAX]<br />\
66D610076200 = VMADD213PD V0{K7},V0,QWORD PTR [RAX]{1To8}<br />\
D690979100 = VCVTPS2PI V0{K7},DWORD PTR [RAX]{1To16,5B}{NT}, {RU}<br />\
D600F09100 = VCVTPS2PI V0,[RAX]{31B}, {RZ}<br />\
D600181000 = VLOADD V0,[RAX]{SRGB8}<br />\
D610181000 = VLOADD V0,DWORD PTR [RAX]{1To16,SRGB8}<br /><br />\
So actually Larrabee compatibility mode should not have to be set except in very rare cases.";
}
if( h === 4 )
{
var win = window.open("", "Cyrix", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "Cyrix, and Geode instruction SMINT is the three byte opcode map instruction 0F38.<br />\
Cyrix instruction BB0_RESET Conflicts with the three byte opcode map 0F3A.<br />\
Cyrix instruction BB1_RESET Conflicts with the three byte opcode map 0F3B, however 0F3B is reserved for future instructions if necessary.<br />\
Cyrix instruction CPU_WRITE Conflicts with the three byte opcode map 0F3C, however 0F3C is reserved for future instructions if necessary.<br />\
Cyrix instruction CPU_READ Conflicts with the three byte opcode map 0F3D, however 0F3D is reserved for future instructions if necessary.<br /><br />\
Lastly the Cyrix instructions.<br /><br />\
Code 0F50 is Cyrix instruction PAVEB.<br />\
Code 0F51 is Cyrix instruction PADDSIW.<br />\
Code 0F52 is Cyrix instruction PMAGW.<br />\
Code 0F54 is Cyrix instruction PDISTIB.<br />\
Code 0F55 is Cyrix instruction PSUBSIW.<br />\
Code 0F58 is Cyrix instruction PMVZB.<br />\
Code 0F59 is Cyrix instruction PMULHRW.<br />\
Code 0F5A is Cyrix instruction PMVNZB.<br />\
Code 0F5B is Cyrix instruction PMVLZB.<br />\
Code 0F5C is Cyrix instruction PMVGEZB.<br />\
Code 0F5D is Cyrix instruction PMULHRIW.<br />\
Code 0F5E is Cyrix instruction PMACHRIW.<br />\
Code 0F78 is Cyrix instruction SVDC.<br />\
Code 0F79 is Cyrix instruction RSDC.<br />\
Code 0F7A is Cyrix instruction SVLDT.<br />\
Code 0F7B is Cyrix instruction RSLDT.<br />\
Code 0F7C is Cyrix instruction SVTS.<br />\
Code 0F7D is Cyrix instruction RSTS.<br />\
Code 0F7E is Cyrix instruction SMINT.<br /><br />\
Are the following instructions in modern X86 Arcutecure.<br /><br />\
Code 0F50 is vector instruction MOVMSK[PS|PD].<br />\
Code 0F51 is vector instruction SQRT[PS|PD|SS|SD].<br />\
Code 0F52 is vector instruction RSQRT[PS|PD].<br />\
Code 0F54 is vector instruction AND[PS|PD].<br />\
Code 0F58 is vector instruction ADD[PS|PD|SS|SD].<br />\
Code 0F59 is vector instruction MUL[PS|PD|SS|SD].<br />\
Code 0F5A is vector instruction CVT[PS|PD|SS|SD]2[PD|PS|SD|SS].<br />\
Code 0F5B is vector instruction CVT[DQ|PS]2[PS|DQ].<br />\
Code 0F5C is vector instruction SUB[PS|PD|SS|SD].<br />\
Code 0F5D is vector instruction MIN[PS|PD|SS|SD].<br />\
Code 0F5E is vector instruction DIV[PS|PD|SS|SD].<br />\
Code 0F78 is virtual machine instruction VMREAD.<br />\
Code 0F79 is virtual machine instruction VMWRITE.<br />\
Code 0F7A is vector instruction CVT[TPS|TPD|UDQ|UQQ]2[QQ|PD|PS].<br />\
Code 0F7B is vector instruction CTV[PS|PD|USI]2[QQ|SS|SD].<br />\
Code 0F7C is vector instruction HADD[PD|PS].<br />\
Code 0F7D is vector instruction HSUB[PD|PS].<br />\
Code 0F7E is instruction MOV[D|Q].<br /><br />\
The rest of the instruction encoding's remain unchanged to the \"Full X86 Architecture\" compatibility mode allowing the Cyrix CPU to execute regular X86 compatible instructions.<br /><br />\
Enabling Cyrix compatibility mode will allow the Cyrix instructions to disassemble, but at an cost of all vector instructions under the three byte opcodes to not disassemble since they are now instructions under 0F38, and 0F3A.<br />\
Also the conflicting Vector, and virtual machine instructions will be changed into Cyrix instructions as how they are supposed to be on the Cyrix CPU.<br /><br />\
Only enable this mode if you Are certain the code is optimized, and meant specifically for the Cyrix CPU otherwise some vector, and virtual machine codes will decode as Cyrix instructions.";
}
if( h === 5 )
{
var win = window.open("", "Geode", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "AMD created the Geode CPU which derived from the Cyrix CPU. The key differences are listed bellow.<br /><br />\
Cyrix, and Geode instruction SMINT is the three byte opcode map instruction 0F38.<br />\
Geode instruction DMINT is the three byte opcode map instruction 0F39, however 0F39 is reserved for future instructions if necessary.<br />\
Geode instruction RDM Conflicts with the three byte opcode map 0F3A.<br /><br />\
The rest of the instruction encoding's remain unchanged to the \"Full X86 Architecture\" compatibility mode allowing the Geode CPU to execute regular X86 compatible instructions.<br /><br />\
Setting Geode compatibility mode will allow the instructions SMINT, DMINT, and RDM to disassemble, but at an cost of disabling an lot of vector instructions that are under the three byte opcodes.";
}
if( h === 6 )
{
var win = window.open("", "Centaur", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "The Centaur CPU instruction ALTINST Conflicts with the three byte opcode map 0F3F, however 0F3F is reserved for future instructions if necessary.<br /><br />\
Instruction 0FA6 is the instruction XBIT, but is grouped instructions MONTMUL (0FA6C0), XSA1 (0FA6C8), XSA256 (0FA6D0) in the Centaur CPU.<br />\
Instruction 0FA7 is the Instruction IBITS, but is grouped instructions XSTORE (0FA7C0), XCRYPT-ECB (F30FA7C8), XCRYPT-CBC (F30FA7D0), XCRYPT-CTR (F30FA7D8), XCRYPT-CFB (F30FA7E0), XCRYPT-OFB (F30FA7E8) in the Centaur CPU.<br /><br />\
The rest of the instruction encoding's remain unchanged to the \"Full X86 Architecture\" compatibility mode allowing the Centaur CPU to execute regular X86 compatible instructions.<br /><br />\
Setting Centaur compatibility mode will allow the Centaur CPU instructions to disassemble instead, of the XBIT, and IBITS instructions.";
}
if( h === 7 )
{
var win = window.open("", "486", "toolbar=no, location=no, directories=no, status=no, menubar=no, scrollbars=yes, resizable=yes");
win.document.body.innerHTML = "In 486 and older CPU's the instruction UMOV conflicts with the new vector MOV instructions: MOVU[PS|PD], MOV[SS|SD], MOVL[PS|PD], MOV[SLD|SS]UP, MOVHLPS, MOVL[PS|PD].<br /><br />\
Instruction 0F10 is vector instruction MOVU[PS|PD], MOV[SS|SD], but is instruction UMOV in 486<br />\
Instruction 0F11 is vector instruction MOVU[PS|PD], MOV[SS|SD], but is instruction UMOV in 486<br />\
Instruction 0F12 is vector instruction MOVL[PS|PD], MOV[SLD|SS]UP, MOVHLPS, but is instruction UMOV in 486<br />\
Instruction 0F13 is vector instruction MOVL[PS|PD], but is instruction UMOV in 486<br /><br />\
Instruction 0FA6 is XBIT, but is instruction CMPXCHG in 486.<br />\
Instruction 0FA7 is IBITS, but is instruction CMPXCHG in 486.<br /><br />\
The rest of the instruction encoding's remain unchanged to the \"Full X86 Architecture\" compatibility mode allowing the 486 CPU to execute regular X86 compatible instructions.<br /><br />\
Setting 486 compatibility mode will allow UMOV, and CMPXCHG to disassemble instead, of the Vectored MOV instructions, and XBIT, IBITS instructions.";
}
}
</script>
<center>
<h1>
Full X86 Disassembler by Damian Recoskie.
</h1>
<h4>Version 2.5.</h4>
</center>
<form>
<table border="1px" width="100%">
<tr>
<td>Format:</td>
<td><input type="radio" name="Format" id="B16" onclick="update();" value="16bit">16 bit binaries (X86-16).</td>
<td><input type="radio" name="Format" id="B32" onclick="update();" value="32bit">32 bit binaries (X86-32).</td>
<td><input type="radio" name="Format" id="B64" onclick="update();" value="64bit" checked>64 bit binaries (X86-64).</td>
</tr>
</table>
<table border="1px" width="100%">
<tr>
<td>
<input type="button" onclick="Help(0)" value="Compatibility Mode Help." />Compatibility Mode:
</td>
<td>
<input type="radio" name="CMode" id="Defualt" onclick="core.compatibilityMode(0);update();" checked>Full X86 Architecture.<div style="float:right;display:inline-block"><input type="button" onclick="help(1)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="K1OM" onclick="core.compatibilityMode(1);update();">Knights Corner.<div style="float:right;display:inline-block"><input type="button" onclick="help(2)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="L1OM" onclick="core.compatibilityMode(2);update();">Larrabee.<div style="float:right;display:inline-block"><input type="button" onclick="help(3)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="Cyrix" onclick="core.compatibilityMode(3);update();">Cyrix.<div style="float:right;display:inline-block"><input type="button" onclick="help(4)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="Geode" onclick="core.compatibilityMode(4);update();">Geode.<div style="float:right;display:inline-block"><input type="button" onclick="help(5)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="Centaur" onclick="core.compatibilityMode(5);update();">Centaur.<div style="float:right;display:inline-block"><input type="button" onclick="help(6)" value="Technical info." /></div>
</td>
<td>
<input type="radio" name="CMode" id="X86/486" onclick="core.compatibilityMode(6);update();">X86/486.<div style="float:right;display:inline-block"><input type="button" onclick="help(7)" value="Technical info." /></div>
</td>
</tr>
</table>
<table border="1px" width="100%">
<tr>
<td>Display Options:</td>
<td><input type="checkbox" name="Display" id="DHex" onclick="update();" value="Hex" checked>Show Disassembled Instruction Hex.</td>
<td><input type="checkbox" name="Display" id="DPos" onclick="update();" value="Pos" checked>Show Instruction Memory Position.</td>
</tr>
</table>
<table border="1px" width="100%">
<tr>
<td>Base Address:</td>
<td>
CS:<input type="text" id="CS" value="0016" onkeyup="update();" onpaste="update();">(Code Segment).
</td>
<td>
<table>
<tr>
<td>
<div id="XIP">RIP:</div>
</td>
<td><input type="text" id="RIP" value="7777777777777777" onkeyup="update();" onpaste="update();">(Instruction Pointer Register).</td>
</tr>
</table>
</td>
</tr>
</table>
<br />
<table border="1px" width="100%">
<tr>
<td>
<center>X86 Code Hex.</center>
</td>
<td>
<center>Disassembly</center>
</td>
</tr>
<tr>
<td>
<center>
You can type in numbers here which will update the Disassembly output.
<div id="ERR"></div>
</center>
</td>
<td>
<center>As you change the X86 code the Result is displayed Here.</center>
</td>
</tr>
<tr>
<td width="30%">
<textarea id="T" style="font-family:monospace;width:100%;" rows="27" onkeyup="var e=this; decode(e.value);" onpaste="var e=this; setTimeout(function(){decode(e.value);}, 100);">CCEB004883C438C3CCCCCCCCCCCCCCCC488BC448895810488970184889782055488DA8E8FDFFFF4881EC10030000488B05930A0A004833C4488985000200004C8B05AAD8090033C0488944244233F6C74424582A002C00488D05B23F05004889442460488D45F04889442448488BF9C744244000000802</textarea>
</td>
<td width="70%">
<textarea id="DisAsm" style="font-family:monospace;width:100%;" rows="27" wrap="off" readonly></textarea>
</td>
</tr>
</table>
</form>
</body>
</html>