Single-cycle-Implementation-of-a-32-bit-RISC-V-processor

Designed the datapath and control unit for a single cycle processor (including instruction memory) which runs 2 unique set of instructions

Instruction Set Architecture:

1. Immediate Type: Ex: li r1, constant -> Loads immediate signed value specified in the instruction to the register.

   opcode: 111111

   Instruction code format

   

2. R-Type: Ex: add r1, r2, r3 -> adds the contents of register r2 and r3 and stores the resultant value in r1.

   opcode: 000000

   Instruction code format

   

Architecture: