The following repository consists of knowledge gained and steps followed while doing the Advanced Physical Design Using OpenLANE/SKY130 workshop. The workshop focuses on the complete ASIC flow approach from RTL2GDS using open soucrce EDA tools such as OpenLANE/SKY130. RISC-V architechture is followed for designing the the core of PICORV32A.
- Sky130 Day 1 - Inception of open-source EDA, OpenLANE and Sky130 PDK
- How to talk to computers
- Introduction to QFN-48 Package, chip, pads, core, die and IPs
- Introduction to RISC-V
- From Software Applications to Hardware
- SoC Design and OpenLane
- Introduction to all components of open-source digital asic design
- Simplified RTL2GDS flow
- Introduction to OpenLane and Strive chipsets
- Introduction to OpenLan and ASIC design flow
- Get Familiar to open-source EDA tools
- OpenLane directory structure in detail
- Design preparatory Step
- Review files after design prep and run synthesis
- OpenLane project Git Link Description
- Steps to characterize synthesis results
- How to talk to computers
First we have a look at the basic building blocks of how computers are made, that is about Packaging, Chips, Pads, Cores, Dies and IPs.
| The image above shows the entire chip. |
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- Package: is the protection layer of the IC chip and the interconnections to other components for transfer of electrical signals
| Diagram of a Package | Image of a package on a microcontroller |
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- Chip: is situated at the centre of the package, with wire bonds connecting it to the ports of the package
| Diagram of a Chip |
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- Pads: are placed all around the chip and are used for sending signals from inside to outside of the chip, vice versa.
- Core: Area containing all the digital logic blocks on the chip.
- Die: Size of the entire chip or can be considered as the overall entity.
| Diagram of a Pad, Die and Core |
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- IP vs Macros: The core of the chip contains IPs and macros.
- IPs are modules that require an extent of intelligence, Eg: SRAM, PLL etc.
- Macros are any regular digital logic block, Eg: RISC V SoC, SPI etc.
- RISC V Architecture:
- is an ISA rooted in reduced set computer (RISC) principles
- its unique, even revolutionary as its open source and free to use, where software can be ported, hardware can be developed & processors can be built to support it
- Picorv32 CPU core:
- A size-optimized RISC-V CPU, a cpu core that implements the RISC-V instruction set.
- Qflow:
- Qflow is a complete tool chain for synthesizing digital circuits starting from verilog source and ending in physical layout for a specific target fabrication process.
What are the steps for a program to run?
- Starting with a C program
- It is compiled into assembly language that is the (RISC V assembly language program)
- Assembly language program is converted into machine code which is a series of 1s and 0s
- The hardware can understand this configuration
The ASIC design procedure requires 3 significant components:
- RTL Designs - Register Transfer Logic - is the design abstraction of modeling digital circuits through HDL
- EDA Tools - Electronic Design Automation - Electronic Design Automation (EDA) refers to a category of software tools used in a workflow to design electronic systems such as semiconductors, integrated circuits, and printed circuit boards. EDA tools enable teams throughout the lifecycle of a chip.
- PDK data - Process Design Kit - a library of basic photonic components generated by the foundry to give open access to their generic process for fabrication.
| The image below shows the simplified RTL2GDS design flow and lists out each steps |
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RTL stands for register transfer logic, is the circuit design made in HDL and GDS2 is the industry standard binary file to represent the IC layout. Below are all the steps described in detail that take us through the RTL to GDS2 design flow.
- Synthesis - the process of turning an abstract design into a correctly implemented chip in terms of logic gates
- Floor/Power Planning :
- Floor Planning involves determining the locations, shape, size of modules in a chip and as such it estimates the chip area, delay and the wiring congestion, thereby providing a ground work for layout.
- Power Planning is to provide power to the every macros, standard cells, and all other cells are present in the design.
- Placement - Placement is the process of determining the locations of circuit devices on a die surface.
- Clock Tree Synthesis - is the automatic insertion of buffers/inverters along the clock paths of the ASIC design in order to balance the clock delay to all clock inputs.
- Route - making physical connections between signal pins using metal layers.
- Sign Off - the collective name given to a series of verification steps that the design must pass before it can be taped out.
OpenLane started as an Open-Source Flow for a True Open Source Tape-Out experiment, and is a part of the striVe family of open everything SoCs: Open PDK, Open EDA and Open RTL.
| The Strive Family has the following models |
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The main objective of the OpenLane ASIC Design flow is to produce a clean GDSII with no human intervention, also with no LVS Violations, no DRC Violations and no Timing violations.
The OpenLane ASIC flow is Tuned for Skywater 130nm Open PDK which also supports XFAB180 and GF130G
- Synthesis Exploration: provides a report that shows how each synthesis strategy performs for delay against area.
- Design Exploration: Generates a report with different design metrics for the final layout of the design. It can also be used for regression testing.
- Design For Test :
- uses the opensource app named Fault.
- Scans Insertion
- Automatic Test Patter Generation
- Test Patter Compaction
- Fault Coverage
- Fault Simulation
- Physical Implementation (Also called automated PnR):
- Uses the opensource app names OpenROAD
- Floor/Power Planning
- End Decoupling Capacitors and Tap cells insertion
- Placement: Global and Detailed
- post placement optimization
- Clock Tree Synthesis (CTS)
- Routing: Global and Detailed
- Logic Equivalence Checking:
- Uses the opnesource app named Yosys
- LEC is used to formally confirm that the function did not change after modifying the netlist
- Dealing With Antenna Rules Violations:
- When a metal wire segment is fabricated it can act as an antenna.
- Reactive ion etching causes charge to accumalate on the wire
- Transistor gates can be damaged during fabrication
- Static Timing Analysis: performed by openSTA
- Physical Verification DRC and LVS: performed using Magic and Netgen
We use PDK data that are kept in 3 directories:
- Skywater-PDK - contains pdk filed provided by the foundry
- open_PDKS - contains scripts to setup pdks for opensource tools
- sky130 - contains sky130 pdk files
OpenLane is built around the sky130 PDK so we will be using that.
- We first run the docker command
docker run -it -v $(pwd):/openLANE_flow -v $PDK_ROOT:$PDK_ROOT -e PDK_ROOT=$PDK_ROOT -u $(id -u
$USER):$ (id -g $USER) openlane:rc6 - Next run flow.tcl with interactive mode on
./flow.tcl