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Welcome to the SiEPIC-Tools wiki!

For Users:

• Installation Instructions
• SiEPIC-Tools menu descriptions
• KLayout and SiEPIC-Tools hotkeys
• Common problems
• Mentor Calibre DRC
• GSiP Technology and Process Design Kit - todo
• Submitting your GDS design to a foundry for manufacturing
• Integration with Lumerical INTERCONNECT for circuit simulations

For component (scripted PCells) developers:

• Creating your own components
  • Layout requirements for Components, including fixed GDS cells and Parameterized cells (PCells)
  • Tutorial on linking a compact model to a layout, for circuit simulations

For scripted layout designers:

• Scripted Layout

For PDK Developers and Maintainers

• PDK Maintenance

For SiEPIC-Tools Developers:

• Contributing
• Implementation details:
  • Netlist extraction
  • Circuit Simulations