Skip to content

Latest commit

 

History

History
10 lines (8 loc) · 300 Bytes

README.md

File metadata and controls

10 lines (8 loc) · 300 Bytes

Lab Sheet 6

LearningObjectives

  • Modeling MIPS Single Cycle Datapath in Verilog
  • Designing modules for each hardware component and some support modules
  • Implementation of the modules in Verilog
  • Integrating these modules
  • Writing test bench
  • Testing the circuit with R-format instruction.