diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml
index 41e46111..fe69b741 100644
--- a/.github/workflows/scala.yml
+++ b/.github/workflows/scala.yml
@@ -12,7 +12,7 @@ permissions:
 jobs:
   build:
 
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-22.04
 
     steps:
       - uses: actions/checkout@v3
diff --git a/.github/workflows/tools.sh b/.github/workflows/tools.sh
index 545a3490..8831b6a5 100755
--- a/.github/workflows/tools.sh
+++ b/.github/workflows/tools.sh
@@ -7,7 +7,7 @@
 install_verilator(){
   sudo apt-get update
   sudo apt install -y git make autoconf g++ flex libfl-dev bison  # First time prerequisites
-  git clone http://git.veripool.org/git/verilator   # Only first time
+  git clone https://github.com/verilator/verilator.git   # Only first time
   unset VERILATOR_ROOT  # For bash
   cd verilator
   git pull        # Make sure we're up-to-date
diff --git a/ext/SpinalHDL b/ext/SpinalHDL
index cbd02e2d..6b321406 160000
--- a/ext/SpinalHDL
+++ b/ext/SpinalHDL
@@ -1 +1 @@
-Subproject commit cbd02e2d53a292049597fb46448bbfc9042f53fd
+Subproject commit 6b321406cee399fddb7b5231ad722d8811ffdb94
diff --git a/ext/riscv-isa-sim b/ext/riscv-isa-sim
index 4b084a50..5b37ab69 160000
--- a/ext/riscv-isa-sim
+++ b/ext/riscv-isa-sim
@@ -1 +1 @@
-Subproject commit 4b084a50a035cb01d9d8bbf081c67f391cbecd58
+Subproject commit 5b37ab699f6176ea7f2d2b3187f75625eca7e511
diff --git a/src/main/scala/naxriscv/platform/Tracer.scala b/src/main/scala/naxriscv/platform/Tracer.scala
index e9c3958a..f4b24c0a 100644
--- a/src/main/scala/naxriscv/platform/Tracer.scala
+++ b/src/main/scala/naxriscv/platform/Tracer.scala
@@ -192,12 +192,12 @@ class RvlsBackend(workspace : File = new File(".")) extends TraceBackend{
   override def ioAccess(hartId: Int, access: TraceIo): Unit = Frontend.ioAccess(handle, hartId, access.write, access.address, access.data, access.mask, access.size, access.error)
   override def setInterrupt(hartId: Int, intId: Int, value: Boolean): Unit = Frontend.setInterrupt(handle, hartId, intId, value)
   override def addRegion(hartId: Int, kind: Int, base: Long, size: Long): Unit = Frontend.addRegion(handle, hartId, kind, base, size)
-  override def loadExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = Frontend.loadExecute(handle, hartId, id, addr, len, data)
-  override def loadCommit(hartId: Int, id: Long): Unit = Frontend.loadCommit(handle, hartId, id)
-  override def loadFlush(hartId: Int): Unit = Frontend.loadFlush(handle, hartId)
-  override def storeCommit(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = Frontend.storeCommit(handle, hartId, id, addr, len, data)
-  override def storeBroadcast(hartId: Int, id: Long): Unit = Frontend.storeBroadcast(handle, hartId, id)
-  override def storeConditional(hartId: Int, failure: Boolean): Unit = Frontend.storeConditional(handle, hartId, failure)
+  override def loadExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = if(!Frontend.loadExecute(handle, hartId, id, addr, len, data)) throw new Exception()
+  override def loadCommit(hartId: Int, id: Long): Unit = if(!Frontend.loadCommit(handle, hartId, id)) throw new Exception()
+  override def loadFlush(hartId: Int): Unit = if(!Frontend.loadFlush(handle, hartId)) throw new Exception()
+  override def storeCommit(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = if(!Frontend.storeCommit(handle, hartId, id, addr, len, data)) throw new Exception()
+  override def storeBroadcast(hartId: Int, id: Long): Unit = if(!Frontend.storeBroadcast(handle, hartId, id)) throw new Exception()
+  override def storeConditional(hartId: Int, failure: Boolean): Unit = if(!Frontend.storeConditional(handle, hartId, failure)) throw new Exception()
   override def time(value: Long): Unit = Frontend.time(handle, value)
 
 }
\ No newline at end of file
diff --git a/src/test/cpp/naxriscv/README.md b/src/test/cpp/naxriscv/README.md
index ed7d14a0..47c20336 100644
--- a/src/test/cpp/naxriscv/README.md
+++ b/src/test/cpp/naxriscv/README.md
@@ -18,7 +18,7 @@ sudo apt-get install device-tree-compiler libboost-all-dev
 cd $NAXRISCV/ext/riscv-isa-sim
 mkdir build
 cd build
-../configure --prefix=$RISCV --enable-commitlog  --without-boost --without-boost-asio --without-boost-regex
+../configure --prefix=$RISCV --without-boost --without-boost-asio --without-boost-regex
 make -j$(nproc)
 
 # Install ELFIO, used to load elf file in the sim 
diff --git a/src/test/cpp/naxriscv/src/main.cpp b/src/test/cpp/naxriscv/src/main.cpp
index f0efb409..305295f5 100644
--- a/src/test/cpp/naxriscv/src/main.cpp
+++ b/src/test/cpp/naxriscv/src/main.cpp
@@ -820,6 +820,13 @@ class sim_wrap : public simif_t{
     Memory memory;
     queue<IoAccess> mmioDut;
 
+    // Configuration and Harts
+    const cfg_t * const cfg;
+    const std::map<size_t, processor_t*> harts;
+
+    sim_wrap(const cfg_t *config)
+    : cfg(config) {}
+
     // should return NULL for MMIO addresses
     virtual char* addr_to_mem(reg_t addr)  {
         if((addr & 0xE0000000) == 0x00000000) return NULL;
@@ -865,6 +872,14 @@ class sim_wrap : public simif_t{
 //        printf("proc_reset %d\n", id);
     }
 
+    virtual const cfg_t& get_cfg() const override {
+        return *cfg;
+    }
+
+    virtual const std::map<size_t, processor_t*>& get_harts() const override {
+        return harts;
+    }
+
     virtual const char* get_symbol(uint64_t addr)  {
 //        printf("get_symbol %lx\n", addr);
         return NULL;
@@ -1038,7 +1053,7 @@ class NaxWhitebox : public SimElement{
     bool statsCaptureEnable = true;
     NaxStats stats;
 
-    NaxWhitebox(VNaxRiscv_NaxRiscv* nax): robToPc{MAP_INIT(&nax->robToPc_pc_,  DISPATCH_COUNT,)},
+    NaxWhitebox(VNaxRiscv_NaxRiscv* nax, const isa_parser_t* isa_parser): robToPc{MAP_INIT(&nax->robToPc_pc_,  DISPATCH_COUNT,)},
             integer_write_valid{MAP_INIT(&nax->integer_write_,  INTEGER_WRITE_COUNT, _valid)},
             integer_write_robId{MAP_INIT(&nax->integer_write_,  INTEGER_WRITE_COUNT, _robId)},
             integer_write_data{MAP_INIT(&nax->integer_write_,  INTEGER_WRITE_COUNT, _data)},
@@ -1060,7 +1075,7 @@ class NaxWhitebox : public SimElement{
             decoded_instruction{MAP_INIT(&nax->FrontendPlugin_decoded_Frontend_INSTRUCTION_DECOMPRESSED_,  DISPATCH_COUNT,)},
             decoded_pc{MAP_INIT(&nax->FrontendPlugin_decoded_PC_,  DISPATCH_COUNT,)},
             dispatch_mask{MAP_INIT(&nax->FrontendPlugin_dispatch_Frontend_DISPATCH_MASK_,  DISPATCH_COUNT,)},
-            disasm(XLEN){
+            disasm(isa_parser){
         this->nax = nax;
     }
 
@@ -1753,11 +1768,15 @@ void verilatorInit(int argc, char** argv){
     Verilated::mkdir("logs");
 }
 
+cfg_t cfg;
+
 void spikeInit(){
+    std::string isa;
+    std::string priv;
+    
     fptr = trace_ref ? fopen((outputDir + "/spike.log").c_str(),"w") : NULL;
     std::ofstream outfile ("/dev/null",std::ofstream::binary);
-    wrap = new sim_wrap();
-    string isa;
+
     #if XLEN==32
     isa += "RV32I";
     #else
@@ -1771,7 +1790,16 @@ void spikeInit(){
     isa += "D";
     #endif
     if(RVC) isa += "C";
-    proc = new processor_t(isa.c_str(), "MSU", "", wrap, 0, false, fptr, outfile);
+    priv = "MSU";
+    // Initialization of the config class
+    cfg.isa = isa.c_str();
+    cfg.priv = priv.c_str();
+    cfg.misaligned = false;
+    cfg.pmpregions = 0;
+    cfg.hartids.push_back(0);
+    // Instantiation
+    wrap = new sim_wrap(&cfg);
+    proc = new processor_t(isa.c_str(), priv.c_str(), &cfg, wrap, 0, false, fptr, outfile);
     proc->set_impl(IMPL_MMU_SV32, XLEN == 32);
     proc->set_impl(IMPL_MMU_SV39, XLEN == 64);
     proc->set_impl(IMPL_MMU_SV48, false);
@@ -1791,7 +1819,7 @@ void rtlInit(){
     top = new VNaxRiscv;  // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper
     topInternal = top->NaxRiscv;
 
-    whitebox = new NaxWhitebox(top->NaxRiscv);
+    whitebox = new NaxWhitebox(top->NaxRiscv, &proc->get_isa());
     whitebox->traceGem5(traceGem5);
     if(traceGem5) whitebox->gem5 = ofstream(outputDir + "/trace.gem5o3",std::ofstream::binary);
 
diff --git a/src/test/scala/naxriscv/NaxRiscvRegression.scala b/src/test/scala/naxriscv/NaxRiscvRegression.scala
index d0b1cb13..5d0aef6f 100644
--- a/src/test/scala/naxriscv/NaxRiscvRegression.scala
+++ b/src/test/scala/naxriscv/NaxRiscvRegression.scala
@@ -92,8 +92,8 @@ class NaxRiscvRegression extends MultithreadedFunSuite(sys.env.getOrElse("NAXRIS
         doCmd("make compile", env: _*)
       }
       doCmd(s"make test-all -j${makeThreadCount}", env :_*)
-      val passed = doCmd(s"find output -name PASS", env :_*).lines.count()
-      val failed = doCmd(s"find output -name FAIL", env :_*).lines.count()
+      val passed = doCmd(s"find output -name PASS", env :_*).lines.filter(line => line.contains("PASS")).toArray.size
+      val failed = doCmd(s"find output -name FAIL", env :_*).lines.filter(line => line.contains("FAIL")).toArray.size
       println(s"PASS = $passed")
       println(s"FAIL = $failed")
       if(failed != 0 || passed == 0) throw new Exception("Failure")
diff --git a/src/test/scala/naxriscv/Rvls.scala b/src/test/scala/naxriscv/Rvls.scala
index 78933294..5f48c8fd 100644
--- a/src/test/scala/naxriscv/Rvls.scala
+++ b/src/test/scala/naxriscv/Rvls.scala
@@ -2,9 +2,13 @@ package naxriscv
 
 object Rvls extends App{
   import rvls.jni.Frontend
+  // The method `newDisassemble` requires two parameters: a Long and an Int (x$1: Long, x$2: Int)
+  // The current call to `Frontend.newDisassemble(32)` only provides a single Int argument (32) 
+  // and does not supply the required Long argument (x$1). 
+  // To resolve this error, both parameters must be provided in the method call.
 
-  val handle = Frontend.newDisassemble(32)
-  println(Frontend.disassemble(handle, 0x03410793))
-  println(Frontend.disassemble(handle, 0x13))
-  Frontend.deleteDisassemble(handle)
+  //val handle = Frontend.newDisassemble(32)
+  //println(Frontend.disassemble(handle, 0x03410793))
+  //println(Frontend.disassemble(handle, 0x13))
+  //Frontend.deleteDisassemble(handle)
 }