From 252cd6344d55fe83cae411a988c02550064b30f2 Mon Sep 17 00:00:00 2001 From: bi262934 Date: Tue, 15 Oct 2024 13:44:06 +0200 Subject: [PATCH 1/8] Update simulator for compatibility with the latest Spike version --- src/test/cpp/naxriscv/README.md | 2 +- src/test/cpp/naxriscv/src/main.cpp | 24 +++++++++++++++++-- .../scala/naxriscv/NaxRiscvRegression.scala | 4 ++-- 3 files changed, 25 insertions(+), 5 deletions(-) diff --git a/src/test/cpp/naxriscv/README.md b/src/test/cpp/naxriscv/README.md index ed7d14a0..47c20336 100644 --- a/src/test/cpp/naxriscv/README.md +++ b/src/test/cpp/naxriscv/README.md @@ -18,7 +18,7 @@ sudo apt-get install device-tree-compiler libboost-all-dev cd $NAXRISCV/ext/riscv-isa-sim mkdir build cd build -../configure --prefix=$RISCV --enable-commitlog --without-boost --without-boost-asio --without-boost-regex +../configure --prefix=$RISCV --without-boost --without-boost-asio --without-boost-regex make -j$(nproc) # Install ELFIO, used to load elf file in the sim diff --git a/src/test/cpp/naxriscv/src/main.cpp b/src/test/cpp/naxriscv/src/main.cpp index f0efb409..e7dad496 100644 --- a/src/test/cpp/naxriscv/src/main.cpp +++ b/src/test/cpp/naxriscv/src/main.cpp @@ -820,6 +820,13 @@ class sim_wrap : public simif_t{ Memory memory; queue mmioDut; + // Configuration and Harts + const cfg_t cfg; + const std::map harts; + + sim_wrap(const cfg_t& configuration) + : cfg(configuration) {} + // should return NULL for MMIO addresses virtual char* addr_to_mem(reg_t addr) { if((addr & 0xE0000000) == 0x00000000) return NULL; @@ -865,6 +872,14 @@ class sim_wrap : public simif_t{ // printf("proc_reset %d\n", id); } + virtual const cfg_t& get_cfg() const override { + return cfg; + } + + virtual const std::map& get_harts() const override { + return harts; + } + virtual const char* get_symbol(uint64_t addr) { // printf("get_symbol %lx\n", addr); return NULL; @@ -1038,7 +1053,7 @@ class NaxWhitebox : public SimElement{ bool statsCaptureEnable = true; NaxStats stats; - NaxWhitebox(VNaxRiscv_NaxRiscv* nax): robToPc{MAP_INIT(&nax->robToPc_pc_, DISPATCH_COUNT,)}, + NaxWhitebox(VNaxRiscv_NaxRiscv* nax, const isa_parser_t* isa_parser): robToPc{MAP_INIT(&nax->robToPc_pc_, DISPATCH_COUNT,)}, integer_write_valid{MAP_INIT(&nax->integer_write_, INTEGER_WRITE_COUNT, _valid)}, integer_write_robId{MAP_INIT(&nax->integer_write_, INTEGER_WRITE_COUNT, _robId)}, integer_write_data{MAP_INIT(&nax->integer_write_, INTEGER_WRITE_COUNT, _data)}, @@ -1060,7 +1075,7 @@ class NaxWhitebox : public SimElement{ decoded_instruction{MAP_INIT(&nax->FrontendPlugin_decoded_Frontend_INSTRUCTION_DECOMPRESSED_, DISPATCH_COUNT,)}, decoded_pc{MAP_INIT(&nax->FrontendPlugin_decoded_PC_, DISPATCH_COUNT,)}, dispatch_mask{MAP_INIT(&nax->FrontendPlugin_dispatch_Frontend_DISPATCH_MASK_, DISPATCH_COUNT,)}, - disasm(XLEN){ + disasm(isa_parser){ this->nax = nax; } @@ -1753,7 +1768,12 @@ void verilatorInit(int argc, char** argv){ Verilated::mkdir("logs"); } +cfg_t cfg; + void spikeInit(){ + std::string isa; + std::string priv; + fptr = trace_ref ? fopen((outputDir + "/spike.log").c_str(),"w") : NULL; std::ofstream outfile ("/dev/null",std::ofstream::binary); wrap = new sim_wrap(); diff --git a/src/test/scala/naxriscv/NaxRiscvRegression.scala b/src/test/scala/naxriscv/NaxRiscvRegression.scala index d0b1cb13..353ec2d5 100644 --- a/src/test/scala/naxriscv/NaxRiscvRegression.scala +++ b/src/test/scala/naxriscv/NaxRiscvRegression.scala @@ -92,8 +92,8 @@ class NaxRiscvRegression extends MultithreadedFunSuite(sys.env.getOrElse("NAXRIS doCmd("make compile", env: _*) } doCmd(s"make test-all -j${makeThreadCount}", env :_*) - val passed = doCmd(s"find output -name PASS", env :_*).lines.count() - val failed = doCmd(s"find output -name FAIL", env :_*).lines.count() + val passed = doCmd(s"find output -name PASS", env :_*).lines.count(line => line.contains("PASS")) + val failed = doCmd(s"find output -name FAIL", env :_*).lines.count(line => line.contains("FAIL")) println(s"PASS = $passed") println(s"FAIL = $failed") if(failed != 0 || passed == 0) throw new Exception("Failure") From 1e0d5b0ca4f5034606250654eae90842ae91147c Mon Sep 17 00:00:00 2001 From: bi262934 Date: Tue, 15 Oct 2024 13:54:31 +0200 Subject: [PATCH 2/8] Using pointers for cfg_t instead of a reference to improve flexibility in memory management and object lifetimes --- src/test/cpp/naxriscv/src/main.cpp | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/src/test/cpp/naxriscv/src/main.cpp b/src/test/cpp/naxriscv/src/main.cpp index e7dad496..305295f5 100644 --- a/src/test/cpp/naxriscv/src/main.cpp +++ b/src/test/cpp/naxriscv/src/main.cpp @@ -821,11 +821,11 @@ class sim_wrap : public simif_t{ queue mmioDut; // Configuration and Harts - const cfg_t cfg; + const cfg_t * const cfg; const std::map harts; - sim_wrap(const cfg_t& configuration) - : cfg(configuration) {} + sim_wrap(const cfg_t *config) + : cfg(config) {} // should return NULL for MMIO addresses virtual char* addr_to_mem(reg_t addr) { @@ -873,13 +873,13 @@ class sim_wrap : public simif_t{ } virtual const cfg_t& get_cfg() const override { - return cfg; + return *cfg; } virtual const std::map& get_harts() const override { return harts; } - + virtual const char* get_symbol(uint64_t addr) { // printf("get_symbol %lx\n", addr); return NULL; @@ -1776,8 +1776,7 @@ void spikeInit(){ fptr = trace_ref ? fopen((outputDir + "/spike.log").c_str(),"w") : NULL; std::ofstream outfile ("/dev/null",std::ofstream::binary); - wrap = new sim_wrap(); - string isa; + #if XLEN==32 isa += "RV32I"; #else @@ -1791,7 +1790,16 @@ void spikeInit(){ isa += "D"; #endif if(RVC) isa += "C"; - proc = new processor_t(isa.c_str(), "MSU", "", wrap, 0, false, fptr, outfile); + priv = "MSU"; + // Initialization of the config class + cfg.isa = isa.c_str(); + cfg.priv = priv.c_str(); + cfg.misaligned = false; + cfg.pmpregions = 0; + cfg.hartids.push_back(0); + // Instantiation + wrap = new sim_wrap(&cfg); + proc = new processor_t(isa.c_str(), priv.c_str(), &cfg, wrap, 0, false, fptr, outfile); proc->set_impl(IMPL_MMU_SV32, XLEN == 32); proc->set_impl(IMPL_MMU_SV39, XLEN == 64); proc->set_impl(IMPL_MMU_SV48, false); @@ -1811,7 +1819,7 @@ void rtlInit(){ top = new VNaxRiscv; // Or use a const unique_ptr, or the VL_UNIQUE_PTR wrapper topInternal = top->NaxRiscv; - whitebox = new NaxWhitebox(top->NaxRiscv); + whitebox = new NaxWhitebox(top->NaxRiscv, &proc->get_isa()); whitebox->traceGem5(traceGem5); if(traceGem5) whitebox->gem5 = ofstream(outputDir + "/trace.gem5o3",std::ofstream::binary); From 46b56a9bd332a85e4f97733090435ba011cf5039 Mon Sep 17 00:00:00 2001 From: bi262934 Date: Tue, 15 Oct 2024 17:30:13 +0200 Subject: [PATCH 3/8] Commented out this unused code that calls Frontend.newDisassemble due to missing parameters --- src/test/scala/naxriscv/Rvls.scala | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/test/scala/naxriscv/Rvls.scala b/src/test/scala/naxriscv/Rvls.scala index 78933294..5f48c8fd 100644 --- a/src/test/scala/naxriscv/Rvls.scala +++ b/src/test/scala/naxriscv/Rvls.scala @@ -2,9 +2,13 @@ package naxriscv object Rvls extends App{ import rvls.jni.Frontend + // The method `newDisassemble` requires two parameters: a Long and an Int (x$1: Long, x$2: Int) + // The current call to `Frontend.newDisassemble(32)` only provides a single Int argument (32) + // and does not supply the required Long argument (x$1). + // To resolve this error, both parameters must be provided in the method call. - val handle = Frontend.newDisassemble(32) - println(Frontend.disassemble(handle, 0x03410793)) - println(Frontend.disassemble(handle, 0x13)) - Frontend.deleteDisassemble(handle) + //val handle = Frontend.newDisassemble(32) + //println(Frontend.disassemble(handle, 0x03410793)) + //println(Frontend.disassemble(handle, 0x13)) + //Frontend.deleteDisassemble(handle) } From 601b459ab2d9354a6d9d7afcc35f8cc681848ea3 Mon Sep 17 00:00:00 2001 From: bi262934 Date: Fri, 18 Oct 2024 00:32:16 +0200 Subject: [PATCH 4/8] Adapted to the RVLS JNI, which now handles exceptions for load/store operations. --- src/main/scala/naxriscv/platform/Tracer.scala | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/main/scala/naxriscv/platform/Tracer.scala b/src/main/scala/naxriscv/platform/Tracer.scala index e9c3958a..f4b24c0a 100644 --- a/src/main/scala/naxriscv/platform/Tracer.scala +++ b/src/main/scala/naxriscv/platform/Tracer.scala @@ -192,12 +192,12 @@ class RvlsBackend(workspace : File = new File(".")) extends TraceBackend{ override def ioAccess(hartId: Int, access: TraceIo): Unit = Frontend.ioAccess(handle, hartId, access.write, access.address, access.data, access.mask, access.size, access.error) override def setInterrupt(hartId: Int, intId: Int, value: Boolean): Unit = Frontend.setInterrupt(handle, hartId, intId, value) override def addRegion(hartId: Int, kind: Int, base: Long, size: Long): Unit = Frontend.addRegion(handle, hartId, kind, base, size) - override def loadExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = Frontend.loadExecute(handle, hartId, id, addr, len, data) - override def loadCommit(hartId: Int, id: Long): Unit = Frontend.loadCommit(handle, hartId, id) - override def loadFlush(hartId: Int): Unit = Frontend.loadFlush(handle, hartId) - override def storeCommit(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = Frontend.storeCommit(handle, hartId, id, addr, len, data) - override def storeBroadcast(hartId: Int, id: Long): Unit = Frontend.storeBroadcast(handle, hartId, id) - override def storeConditional(hartId: Int, failure: Boolean): Unit = Frontend.storeConditional(handle, hartId, failure) + override def loadExecute(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = if(!Frontend.loadExecute(handle, hartId, id, addr, len, data)) throw new Exception() + override def loadCommit(hartId: Int, id: Long): Unit = if(!Frontend.loadCommit(handle, hartId, id)) throw new Exception() + override def loadFlush(hartId: Int): Unit = if(!Frontend.loadFlush(handle, hartId)) throw new Exception() + override def storeCommit(hartId: Int, id: Long, addr: Long, len: Long, data: Long): Unit = if(!Frontend.storeCommit(handle, hartId, id, addr, len, data)) throw new Exception() + override def storeBroadcast(hartId: Int, id: Long): Unit = if(!Frontend.storeBroadcast(handle, hartId, id)) throw new Exception() + override def storeConditional(hartId: Int, failure: Boolean): Unit = if(!Frontend.storeConditional(handle, hartId, failure)) throw new Exception() override def time(value: Long): Unit = Frontend.time(handle, value) } \ No newline at end of file From ff5cb9803836f09b5a23696f3ae33513550d65ea Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 5 Dec 2024 11:53:59 +0100 Subject: [PATCH 5/8] Update tools.sh verilator git --- .github/workflows/tools.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/tools.sh b/.github/workflows/tools.sh index 545a3490..8831b6a5 100755 --- a/.github/workflows/tools.sh +++ b/.github/workflows/tools.sh @@ -7,7 +7,7 @@ install_verilator(){ sudo apt-get update sudo apt install -y git make autoconf g++ flex libfl-dev bison # First time prerequisites - git clone http://git.veripool.org/git/verilator # Only first time + git clone https://github.com/verilator/verilator.git # Only first time unset VERILATOR_ROOT # For bash cd verilator git pull # Make sure we're up-to-date From 54b5a2961a85506e5141683fae58fff52ed79da3 Mon Sep 17 00:00:00 2001 From: bi262934 Date: Mon, 9 Dec 2024 16:01:35 +0100 Subject: [PATCH 6/8] Update ext/SpinalHDL & ext/riscv-isa-sim & ext/rvls --- ext/SpinalHDL | 2 +- ext/riscv-isa-sim | 2 +- ext/rvls | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/ext/SpinalHDL b/ext/SpinalHDL index cbd02e2d..6b321406 160000 --- a/ext/SpinalHDL +++ b/ext/SpinalHDL @@ -1 +1 @@ -Subproject commit cbd02e2d53a292049597fb46448bbfc9042f53fd +Subproject commit 6b321406cee399fddb7b5231ad722d8811ffdb94 diff --git a/ext/riscv-isa-sim b/ext/riscv-isa-sim index 052b6f96..5b37ab69 160000 --- a/ext/riscv-isa-sim +++ b/ext/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 052b6f967b9df22f5a6e174307b62ecc5e2d4ad3 +Subproject commit 5b37ab699f6176ea7f2d2b3187f75625eca7e511 diff --git a/ext/rvls b/ext/rvls index 520b40dc..3081a28e 160000 --- a/ext/rvls +++ b/ext/rvls @@ -1 +1 @@ -Subproject commit 520b40dc9bc4d15348dd2225a7c4fd30ebf900de +Subproject commit 3081a28e562756c12fc7d7aee1c554ea8bae36f5 From 08d0e6fc15873d4d660bea82812a210a7665c4b1 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 9 Dec 2024 18:31:52 +0100 Subject: [PATCH 7/8] Fix verilator compilation --- .github/workflows/scala.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/scala.yml b/.github/workflows/scala.yml index 41e46111..fe69b741 100644 --- a/.github/workflows/scala.yml +++ b/.github/workflows/scala.yml @@ -12,7 +12,7 @@ permissions: jobs: build: - runs-on: ubuntu-latest + runs-on: ubuntu-22.04 steps: - uses: actions/checkout@v3 From 0e787e4b285c082d146aaa8a8ac6068d1bdf8c70 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 9 Dec 2024 18:49:53 +0100 Subject: [PATCH 8/8] Fix scala compilation --- src/test/scala/naxriscv/NaxRiscvRegression.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/test/scala/naxriscv/NaxRiscvRegression.scala b/src/test/scala/naxriscv/NaxRiscvRegression.scala index 353ec2d5..5d0aef6f 100644 --- a/src/test/scala/naxriscv/NaxRiscvRegression.scala +++ b/src/test/scala/naxriscv/NaxRiscvRegression.scala @@ -92,8 +92,8 @@ class NaxRiscvRegression extends MultithreadedFunSuite(sys.env.getOrElse("NAXRIS doCmd("make compile", env: _*) } doCmd(s"make test-all -j${makeThreadCount}", env :_*) - val passed = doCmd(s"find output -name PASS", env :_*).lines.count(line => line.contains("PASS")) - val failed = doCmd(s"find output -name FAIL", env :_*).lines.count(line => line.contains("FAIL")) + val passed = doCmd(s"find output -name PASS", env :_*).lines.filter(line => line.contains("PASS")).toArray.size + val failed = doCmd(s"find output -name FAIL", env :_*).lines.filter(line => line.contains("FAIL")).toArray.size println(s"PASS = $passed") println(s"FAIL = $failed") if(failed != 0 || passed == 0) throw new Exception("Failure")