NaxRiscv update for compatibility with naxriscv branches of rvls/risc-isa-sim

[Bill94l]

• Improvements: Updating Spike and RVLS Submodules #126 (comment)

[Dolu1990]

Hi ^^

I pushed a fix concerning verlator git having migrated to github.
Now the issue seems that NaxRiscv scala binding with RVLS is expecting a more recent version of RVLS.
in particular, it expects that a few of the API return a boolean value to tell if it succeed or not.
Typicaly a feature which was added with this commit :
SpinalHDL/rvls@35c276a

[Bill94l]

Hi @Dolu1990

I just checked locally, and I believe the issue is related to the version of SpinalHDL. On my side, I am working with the version from commit 6b321406cee399fddb7b5231ad722d8811ffdb94, while I see that you are currently using the version from commit cbd02e2d53a292049597fb46448bbfc9042f53fd.

Thanks :D

[Dolu1990]

Ahhh no, the PR you opened need to also update the rvls/riscv-isa-sim.

What you need to do is :

cd NaxRiscv
git add ext/rvls
git add ext/riscv-isa-sim
git commit -m "Update rvls/riscv-isa-sim"
git push

This way, the submodule update will be included in your change :D

(right ? there we are out of sync ?)

[Bill94l]

Hi ^^

• Currently, we are out of sync with the version of the Spinal library. You need to update it on your side.

  

  On my side, I am working with the version from commit 6b321406cee399fddb7b5231ad722d8811ffdb94, while I see that you are currently using the version from commit cbd02e2d53a292049597fb46448bbfc9042f53fd

• This pull request is awaiting your validation Allow LR/SC on MMIO with RVLS riscv-isa-sim#4 (comment)

[Dolu1990]

For this aswell, you need to do a :

cd NaxRiscv
git add ext/SpinalHDL
git commit -m "Update SpinalHDL"
git push

Then this update should show up in this PR.
Basicaly, that git submodule update would become part of the PR. (instead of relying on the main repo having the same version as you already)

[Dolu1990]

SpinalHDL/riscv-isa-sim#4 merged ^^

[Bill94l]

I don't know what's wrong with Verilator ?

[Dolu1990]

Hmm weird, i'm looking at it. Probably a new version of GCC not so happy with it XD

[Dolu1990]

The verilator compilation should be good now ^^

[Dolu1990]

BRAwwwwwww it passes regression <3

[Bill94l]

Great! 😄

We also have an updated version featuring a global Makefile and scripts that automate the local installation of the toolchain without requiring sudo.

• This version allows you to run all regression tests, including booting Linux with RVLS through SocSim.

If you're interested, I'd be happy to prepare a new pull request! 😊

[Dolu1990]

Sure, no sudo is good ^^

[Dolu1990]

All good for merging this PR ?
(the detected conflict, i will solve that)

[Bill94l]

Yes, everything works perfectly for this PR on my side. The regression tests successfully pass for all RV32 and RV64 configurations using RVLS. Regarding the conflict, I'm unsure of its cause, as riscv-isa-sim was merged without any issues.

[Bill94l]

Did you merge into the rvls-update branch? It seems the submodule versions have not been updated as expected.

It seems you merged rvls-update into update-spike, but it should have been the other way around. right?

[Dolu1990]

The
Merge remote-tracking branch 'origin/rvls-update' into updated-spike
did nothing, that was just to get ride of github issues ^^
Nothing was merged yet in SpinalHDL org.

But right now it is merged ^^