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Document Banana Memory Bus #15

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mithro opened this issue Dec 24, 2019 · 1 comment

mithro commented Dec 24, 2019

From your README it says;

The BMB (Banana Memory Bus) which can cover both cached and cacheless SoC without compromises

Do you have any documentation on the BMB and why it can cover both cached and cacheless SoC without compromise.

Member

Dolu1990 commented Dec 24, 2019 •

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I just added that :
https://github.com/SpinalHDL/SaxonSoc#bmb-spec-wip

The BMB bus itself is quite stable now, but the spec writting is WIP
Basicaly it is the combination of the following factors :

Not as complicated than AXI4
Facilities to avoid having slave to implement burst support / unaligned access support
State-less adapter made possible via the context feature
Can do out of order stuff

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