From 3201b410776d78f502ea076090618516b7240c57 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Mon, 25 Nov 2024 13:19:06 +0100
Subject: [PATCH] Add doc about privileges

---
 source/VexiiRiscv/Execute/plugins.rst  |  50 ++-------
 source/VexiiRiscv/Memory/index.rst     |   8 +-
 source/VexiiRiscv/Privileges/index.rst | 118 +++++++++++++++++++++
 source/asset/miaou.drawio              | 141 ++++++++++++++++---------
 source/asset/picture/privileges.png    | Bin 0 -> 27625 bytes
 source/conf.py                         |   3 +
 source/index.rst                       |   1 +
 7 files changed, 223 insertions(+), 98 deletions(-)
 create mode 100644 source/VexiiRiscv/Privileges/index.rst
 create mode 100644 source/asset/picture/privileges.png

diff --git a/source/VexiiRiscv/Execute/plugins.rst b/source/VexiiRiscv/Execute/plugins.rst
index 3052ac7..452a868 100644
--- a/source/VexiiRiscv/Execute/plugins.rst
+++ b/source/VexiiRiscv/Execute/plugins.rst
@@ -125,53 +125,17 @@ Implement load / store through a l1 cache.
 
 More information in the :ref:`lsu` chapter
 
-
-Special
--------
-
-Some implement CSR, privileges and special instructions
-
 CsrAccessPlugin
 ^^^^^^^^^^^^^^^
 
-- Implement the CSR read and write instruction
-- Provide an API for other plugins to specify its hardware mapping
-
-CsrRamPlugin
-^^^^^^^^^^^^
+- Implement the CSR read and write instruction in the execute pipeline
+- Provide an API for other plugins to specify the mapping between the CSR registers and the CSR instruction
 
-- Implement a shared on chip ram
-- Provide an API which allows to statically allocate space on it
-- Provide an API to create read / write ports on it
-- Used by various plugins to store the CSR contents in a FPGA efficient way
-
-PrivilegedPlugin
-^^^^^^^^^^^^^^^^
-
-- Implement the RISC-V privileged spec
-- Use the CsrRamPlugin to implement various CSR as MTVAL, MTVEC, MEPC, MSCRATCH, ...
-
-TrapPlugin
-^^^^^^^^^^^
-
-- Implement the trap buffer / FSM
-- The FSM implement the core logic of many special instructions (MRET, SRET, ECALL, EBREAK, FENCE.I, WFI, ...)
-- Also allows the CPU pipeline to emit hardware traps to re-execute (REDO) the current instruction
-  or to jump to the next one after a full pipeline flush (NEXT).
-- the REDO hardware trap is used by I$ D$ miss, the DecodePlugin when it detect a illegal branch prediction
-- the NEXT hardware trap is used by the CsrAccessPlugin when a state change require a full CPU flush
-
-PerformanceCounterPlugin
-^^^^^^^^^^^^^^^^^^^^^^^^
-
-Implement the privileged performance counters in a FPGA friendly way :
-
-- Use the CsrRamPlugin to store 57 bits for each performance counter
-- Use a dedicated 7 bits hardware register per counter
-- Once that 7 bits register MSB is set, a FSM will flush it into the CsrRamPlugin
+See the :ref:`privileges` chapter for more informations.
 
 EnvPlugin
-^^^^^^^^^
+^^^^^^^^^^^^^^^
+
+See the :ref:`privileges` chapter for more informations.
 
-- Implement a few instructions as MRET, SRET, ECALL, EBREAK, FENCE.I, WFI by producing hardware traps
-- Those hardware trap are then handled in the TrapPlugin FSM
+- Implement a few instructions as MRET, SRET, ECALL, EBREAK, FENCE.I, WFI by producing hardware traps
\ No newline at end of file
diff --git a/source/VexiiRiscv/Memory/index.rst b/source/VexiiRiscv/Memory/index.rst
index 2dc9fc1..06f7052 100644
--- a/source/VexiiRiscv/Memory/index.rst
+++ b/source/VexiiRiscv/Memory/index.rst
@@ -177,11 +177,11 @@ Without it, the CPU software would have to manualy flush/invalidate their L1 cac
 There is mostly 2 kinds of hardware memory coherency architecture :
 
 - By invalidation : When a CPU/DMA write some memory, it notifies the other CPU caches that they should invalidate any
-old copy that they have of the written memory locations. This is generaly used for write-through L1 caches.
-This isn't what VexiiRiscv implements.
+  old copy that they have of the written memory locations. This is generaly used for write-through L1 caches.
+  This isn't what VexiiRiscv implements.
 - By permition : Memory blocks copies (typicaly 64 aligned bytes blocks which resides in L1 cache lines) can have multiple states.
-Some of which provide read only accesses, while others provide read/write accesses. This is generaly used in write-back L1 caches,
-and this is what VexiiRiscv uses.
+  Some of which provide read only accesses, while others provide read/write accesses. This is generaly used in write-back L1 caches,
+  and this is what VexiiRiscv uses.
 
 In VexiiRiscv, the hardware memory coherency (L1) with other memory agents (CPU, DMA, L2, ..) is supported though a MESI implementation which can be bridged to a tilelink memory bus.
 
diff --git a/source/VexiiRiscv/Privileges/index.rst b/source/VexiiRiscv/Privileges/index.rst
new file mode 100644
index 0000000..e149c76
--- /dev/null
+++ b/source/VexiiRiscv/Privileges/index.rst
@@ -0,0 +1,118 @@
+.. _privileges:
+
+Privileges
+###################
+
+RISC-V specifies in "Volume 2, Privileged Specification" most of its special registers (CSR) which allows to handle things as :
+
+- Traps (interrupts + exceptions)
+- Memory protections (MMU, PMP)
+- Privilege modes (Machine, Superivisor, User)
+
+A microcontroller will typicaly only need Machine mode, maybe User mode, while a Linux capable CPU will normaly need them all.
+
+- Machine mode : Baremetal / Bootloader / BIOS / OpenSBI / RTOS
+- Supervisor mode : Kernel / Linux
+- User mode : Applications running on the top of linux
+
+Those are handled in VexiiRiscv via a sets of plugins.
+
+.. image:: /asset/picture/privileges.png
+
+CsrAccessPlugin
+^^^^^^^^^^^^^^^
+
+- Implement the CSR read and write instruction in the execute pipeline
+- Provide an API for other plugins to specify the mapping between the CSR registers and the CSR instruction
+
+For instance, when another plugin want to add a custom CSR, it can do as follow :
+
+.. code-block:: scala
+
+    class CustomPlugin() extends FiberPlugin  {
+      val logic = during setup new Area{
+        val cp = host[CsrService] // CsrAccessPlugin is an implementation of CsrService
+        val buildBefore = retains(cp.csrLock) // This ensure that the CsrService hold one until we are finished with the API usages
+        awaitBuild()
+
+        // Define a few registers
+        val regX = Reg(UInt(8 bits)) init(0)
+        val regY = Reg(UInt(8 bits)) init(0)
+
+        // Map those registers in the RISC-V CSRs at address 0xFF0.
+        // - Bits 17:10 will be regX
+        // - Bits 27:20 will be regY
+        cp.readWrite(0xFF0, 10 -> regX, 20 -> regY)
+
+        // Now that we are with the csr API, we allows it to elaborate
+        buildBefore.release()
+      }
+    }
+
+PrivilegedPlugin
+----------------
+
+- Implement the RISC-V privileged spec, mostly by using the CsrAccessPlugin API
+- Use the CsrRamPlugin to implement various CSR as MTVAL, MTVEC, MEPC, MSCRATCH, ...
+- By default only the machine mode is enabled.
+- You can use `--with-supervisor` and --with-user` to enable the corresponding privileged modes
+
+CsrRamPlugin
+------------
+
+- Provide an API which allows to statically allocate space on it
+- Provide an API to create read / write ports on it
+- Used by various plugins to store the CSR contents in a FPGA efficient way
+
+
+TrapPlugin
+-----------
+
+- Implement the trap buffer / FSM
+- The FSM implement the core logic of many special instructions (MRET, SRET, ECALL, EBREAK, FENCE.I, WFI, ...)
+- Also allows the CPU pipeline to emit hardware traps to re-execute (REDO) the current instruction
+  or to jump to the next one after a full pipeline flush (NEXT).
+- the REDO hardware trap is used by I$ D$ miss, the DecodePlugin when it detect a illegal branch prediction
+- the NEXT hardware trap is used by the CsrAccessPlugin when a state change require a full CPU flush
+
+PerformanceCounterPlugin
+------------------------
+
+Implement the privileged performance counters in a FPGA friendly way :
+
+- Use the CsrRamPlugin to store 57 bits for each performance counter
+- Use a dedicated 7 bits hardware register per counter
+- Once that 7 bits register MSB is set, a FSM will flush it into the CsrRamPlugin
+- By default, this plugins is disabled, to enable it, you can use, for instance, `--performance-counters 9`
+
+EnvPlugin
+---------
+
+- Implement a few instructions as MRET, SRET, ECALL, EBREAK, FENCE.I, WFI by producing hardware traps
+- Those hardware trap are then handled in the TrapPlugin FSM
+
+MmuPlugin
+---------
+
+- Implements supervisor mode memory protections
+- Include a hardware page walker
+- Has a TLB to store the page walker results
+- TLB are stored in multiples directly mapped memories. Typicaly 2 way x 32 TLB for 4KB pages + 1 way x 32 TLB for mega pages
+- Map very well with FPGA which supports asyncronous read memory (LUT based RAM)
+- Can be configured to work with syncronous read memory (block ram), but will likely be your critical path for timings
+
+This plugin is enabled via `--with-mmu` or `--with-supervisor`
+
+PmpPlugin
+----------
+
+- Allows the machine mode to restrict memory accesses of the supervisor/user mode to specific ranges (Physical Memory Protection)
+- Quite expensive in resources and timings.
+- Support NAPOT (aligned power of 2 sized regions)
+- Support TOR (unrestricted region address/size)
+- You can disable the RISC-V TOR support to help with area and timings
+- You can set the granularity of the memory regions (to improve timings and area usage). This throw away some of the address LSB bits.
+  By default, the granularity is 4KB (--pmp-granularity=4096). Minimum allowed is 4.
+- By default, the PmpPlugin is disabled, but you can enable it via, for instance, `--pmp-size=4`,
+  which will enable 4 hardware PMP registres, allowing you to set up to 4 memory regions.
+
diff --git a/source/asset/miaou.drawio b/source/asset/miaou.drawio
index ac8a9c8..f409c1c 100644
--- a/source/asset/miaou.drawio
+++ b/source/asset/miaou.drawio
@@ -1,6 +1,6 @@
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+<mxfile host="Electron" agent="Mozilla/5.0 (X11; Linux x86_64) AppleWebKit/537.36 (KHTML, like Gecko) draw.io/21.6.8 Chrome/114.0.5735.289 Electron/25.5.0 Safari/537.36" modified="2024-11-25T11:53:30.950Z" etag="6I9qyIsqQYwgvryQl4Ec" version="21.6.8" type="device" pages="22">
   <diagram id="21M7YdDJjqVILJei4Rus" name="vexii">
-    <mxGraphModel dx="3654" dy="1235" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="850" pageHeight="1100" math="0" shadow="0">
+    <mxGraphModel dx="7283" dy="3529" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="850" pageHeight="1100" math="0" shadow="0">
       <root>
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@@ -3284,7 +3284,7 @@
     </mxGraphModel>
   </diagram>
   <diagram name="execute" id="cmWOkzOcqqSYMlFNeabi">
-    <mxGraphModel dx="1954" dy="1235" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="850" pageHeight="1100" math="0" shadow="0">
+    <mxGraphModel dx="651" dy="412" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="850" pageHeight="1100" math="0" shadow="0">
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         <mxCell id="UvzUxrtpYBwZnMAskWk_-1" parent="UvzUxrtpYBwZnMAskWk_-0" />
@@ -3609,222 +3609,261 @@
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             <mxPoint x="220" y="1109.92" as="sourcePoint" />
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+        <mxCell id="gw8uTePGPCKkRlXf24tB-1" value="ExecuteLanePlugin" style="rounded=1;whiteSpace=wrap;html=1;fontSize=12;strokeWidth=1;dashed=1;dashPattern=1 1;" parent="UvzUxrtpYBwZnMAskWk_-1" vertex="1">
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diff --git a/source/conf.py b/source/conf.py
index 8cf23d0..eba5c96 100644
--- a/source/conf.py
+++ b/source/conf.py
@@ -236,6 +236,9 @@
 # Whitelist pattern for tags (set to None to ignore all tags)
 smv_tag_whitelist = r'^.*$'
 
+smartquotes = False
+html_use_smartypants = False
+
 # The branch called "latest" is not a real branch/tag, it is aliased by the document
 #  build process to the most recent stable release.
 # Whitelist pattern for branches (set to None to ignore all branches)
diff --git a/source/index.rst b/source/index.rst
index f949a11..35c6592 100644
--- a/source/index.rst
+++ b/source/index.rst
@@ -14,6 +14,7 @@ Welcome to VexiiRiscv's documentation!
    VexiiRiscv/Execute/index
    VexiiRiscv/BranchPrediction/index
    VexiiRiscv/Memory/index
+   VexiiRiscv/Privileges/index
    VexiiRiscv/Debug/index
    VexiiRiscv/HowToUse/index
    VexiiRiscv/Performance/index