From d311ce5870cb5749784e80d3eee4df6350a46ca6 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 3 Dec 2024 17:14:51 +0100 Subject: [PATCH] Efficiency cookbook ++ --- source/VexiiRiscv/Memory/index.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/source/VexiiRiscv/Memory/index.rst b/source/VexiiRiscv/Memory/index.rst index 21bf559..ba94334 100644 --- a/source/VexiiRiscv/Memory/index.rst +++ b/source/VexiiRiscv/Memory/index.rst @@ -292,5 +292,7 @@ Here are a set of design guideline to keep a memory system lean and efficient (d - DMA should avoid doing multiple accesses in a 64 byte block if possible, and instead use a single access. This can preserve the DRAM controller bandwidth (see DDR3/4/5 comments above), but also, L2/L3 cache designs may block any additional memory request targeting a memory block which is already under operation. +- When a DMA start a write burst, it has to complet as fast as possible. The reason is that the interconnect can lock itself on your burst until you finish it. +- When a DMA start a read burst, it should avoid putting backpresure on the read responses. The reason is that the interconnect can lock itself on your burst until you finish it.