Deploying to gh-pages from @ c49000e 🚀

master/.buildinfo

@@ -1,4 +1,4 @@
 # Sphinx build info version 1
 # This file hashes the configuration used when building these files. When it is not found, a full rebuild will be done.
-config: ccc713afacd8a251f9426f0bdfb02850
+config: 26be707923267498bfac71ca7299e5c4
 tags: 645f666f9bcd5a90fca523b33c5a78b7

master/VexiiRiscv/BranchPrediction/index.html

@@ -374,7 +374,7 @@ <h2>LearnPlugin<a class="headerlink" href="#learnplugin" title="Permalink to thi
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Debug/index.html

@@ -352,7 +352,7 @@ <h2>EmbeddedRiscvJtag<a class="headerlink" href="#embeddedriscvjtag" title="Perm
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Decode/index.html

@@ -396,7 +396,7 @@ <h3>Elaboration<a class="headerlink" href="#elaboration" title="Permalink to thi
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Execute/custom.html

@@ -526,7 +526,7 @@ <h3>Conclusion<a class="headerlink" href="#conclusion" title="Permalink to this
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Execute/fpu.html

@@ -366,7 +366,7 @@ <h2>Optimized software<a class="headerlink" href="#optimized-software" title="Pe
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Execute/index.html

@@ -332,7 +332,7 @@ <h1>Execute<a class="headerlink" href="#execute" title="Permalink to this headin
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Execute/introduction.html

@@ -334,7 +334,7 @@ <h1>Introduction<a class="headerlink" href="#introduction" title="Permalink to t
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Execute/plugins.html

@@ -438,7 +438,7 @@ <h3>EnvPlugin<a class="headerlink" href="#envplugin" title="Permalink to this he
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Fetch/index.html

@@ -349,10 +349,10 @@ <h2>FetchL1Plugin<a class="headerlink" href="#fetchl1plugin" title="Permalink to
 <td><p>Enable the L1 D$</p></td>
 </tr>
 <tr class="row-odd"><td><p>--fetch-l1-ways=X</p></td>
-<td><p>Specify the number of ways  for the L1 I$ (how many direct mapped caches in parallel)</p></td>
+<td><p>Specify the number of ways  for the L1 I$ (how many direct mapped caches in parallel), default=1</p></td>
 </tr>
 <tr class="row-even"><td><p>--fetch-l1-sets=X</p></td>
-<td><p>Specify the number of sets for the L1 I$ (how many line of cache per way)</p></td>
+<td><p>Specify the number of sets for the L1 I$ (how many line of cache per way), default=64</p></td>
 </tr>
 <tr class="row-odd"><td><p>--fetch-l1-mem-data-width-min=X</p></td>
 <td><p>Set a lower bound for the L1 I$ data width</p></td>
@@ -361,10 +361,13 @@ <h2>FetchL1Plugin<a class="headerlink" href="#fetchl1plugin" title="Permalink to
 <td><p>Enable the L1 I$ hardware prefetcher (prefetch the next line)</p></td>
 </tr>
 <tr class="row-odd"><td><p>--fetch-l1-refill-count=X</p></td>
-<td><p>Specify how many cache line refill the L1 I$ can handle at the same time</p></td>
+<td><p>Specify how many cache line refill the L1 I$ can handle at the same time, default=1</p></td>
 </tr>
 </tbody>
 </table>
+<p>To improve the performances, consider first increasing the number of cache ways to 4.
+The hardware prefetcher can help, but it is very variable in function of the workload. If you enable it, then consider
+increasing the number of refill slots to at least 2, idealy 3.</p>
 </section>
 <section id="prefetchernextlineplugin">
 <h2>PrefetcherNextLinePlugin<a class="headerlink" href="#prefetchernextlineplugin" title="Permalink to this heading"></a></h2>
@@ -431,7 +434,7 @@ <h2>HistoryPlugin<a class="headerlink" href="#historyplugin" title="Permalink to
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Framework/index.html

@@ -692,7 +692,7 @@ <h2>Pipeline API<a class="headerlink" href="#pipeline-api" title="Permalink to t
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/HowToUse/index.html

@@ -542,7 +542,7 @@ <h2>Using IntelliJ IDEA<a class="headerlink" href="#using-intellij-idea" title="
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Introduction/index.html

@@ -411,7 +411,7 @@ <h2>Check list<a class="headerlink" href="#check-list" title="Permalink to this
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Memory/index.html

@@ -352,10 +352,10 @@ <h2>With L1<a class="headerlink" href="#with-l1" title="Permalink to this headin
 <td><p>Enable the L1 D$</p></td>
 </tr>
 <tr class="row-odd"><td><p>--lsu-l1-ways=X</p></td>
-<td><p>Specify the number of ways  for the L1 D$ (how many direct mapped caches in parallel)</p></td>
+<td><p>Specify the number of ways  for the L1 D$ (how many direct mapped caches in parallel), default=1</p></td>
 </tr>
 <tr class="row-even"><td><p>--lsu-l1-sets=X</p></td>
-<td><p>Specify the number of sets for the L1 D$ (how many line of cache per way)</p></td>
+<td><p>Specify the number of sets for the L1 D$ (how many line of cache per way), default=64</p></td>
 </tr>
 <tr class="row-odd"><td><p>--lsu-l1-mem-data-width-min=X</p></td>
 <td><p>Set a lower bound for the L1 D$ data width</p></td>
@@ -373,13 +373,18 @@ <h2>With L1<a class="headerlink" href="#with-l1" title="Permalink to this headin
 <td><p>Specify how many block of memory can be targeted by the store buffer (disabled/0 by default)</p></td>
 </tr>
 <tr class="row-even"><td><p>--lsu-l1-refill-count=X</p></td>
-<td><p>Specify how many cache line refill the L1 D$ can handle at the same time</p></td>
+<td><p>Specify how many cache line refill the L1 D$ can handle at the same time, default=1</p></td>
 </tr>
 <tr class="row-odd"><td><p>--lsu-l1-writeback-count=X</p></td>
-<td><p>Specify how many cache line writeback the L1 D$ can handle at the same time</p></td>
+<td><p>Specify how many cache line writeback the L1 D$ can handle at the same time, default=1</p></td>
 </tr>
 </tbody>
 </table>
+<p>To improve the performances, consider first increasing the number of cache ways to 4.</p>
+<p>The store buffer will help a lot with the store bandwidth by allowing the CPU to not be blocked by every store miss.
+The hardware prefetcher will help with both store/load bandwidth (but if the store buffer is already enabled, it will not
+realy increase the store bandwidth).</p>
+<p>For the hardware prefetcher to stretch its leg, consider using 4 refill/writeback slots. This will also help the store buffer.</p>
 <section id="prefetching">
 <h3>Prefetching<a class="headerlink" href="#prefetching" title="Permalink to this heading"></a></h3>
 <p>Currently there is two implementation of prefetching</p>
@@ -598,7 +603,7 @@ <h4>Efficiency cookbook<a class="headerlink" href="#efficiency-cookbook" title="
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Performance/index.html

@@ -506,7 +506,7 @@ <h2>Critical paths tool<a class="headerlink" href="#critical-paths-tool" title="
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Privileges/index.html

@@ -426,7 +426,7 @@ <h3>PmpPlugin<a class="headerlink" href="#pmpplugin" title="Permalink to this he
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Soc/index.html

@@ -326,7 +326,7 @@ <h1>SoC<a class="headerlink" href="#soc" title="Permalink to this heading"></
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Soc/litex.html

@@ -359,7 +359,7 @@
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/VexiiRiscv/Soc/microsoc.html

@@ -480,7 +480,7 @@ <h2>Adding a custom instruction<a class="headerlink" href="#adding-a-custom-inst
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/_sources/VexiiRiscv/Fetch/index.rst.txt

@@ -66,8 +66,6 @@ Will :
 - Generate a fetch memory bus for the SoC interconnect
 - Check for the presence of a fetch.PrefetcherPlugin to bind it to the L1
 
-
-
 .. list-table:: Generation parameters
    :widths: 30 70
    :header-rows: 1
@@ -77,16 +75,19 @@ Will :
    * - --fetch-l1
      - Enable the L1 D$
    * - --fetch-l1-ways=X
-     - Specify the number of ways  for the L1 I$ (how many direct mapped caches in parallel)
+     - Specify the number of ways  for the L1 I$ (how many direct mapped caches in parallel), default=1
    * - --fetch-l1-sets=X
-     - Specify the number of sets for the L1 I$ (how many line of cache per way)
+     - Specify the number of sets for the L1 I$ (how many line of cache per way), default=64
    * - --fetch-l1-mem-data-width-min=X
      - Set a lower bound for the L1 I$ data width
    * - --fetch-l1-hardware-prefetc=nl
      - Enable the L1 I$ hardware prefetcher (prefetch the next line)
    * - --fetch-l1-refill-count=X
-     - Specify how many cache line refill the L1 I$ can handle at the same time
+     - Specify how many cache line refill the L1 I$ can handle at the same time, default=1
 
+To improve the performances, consider first increasing the number of cache ways to 4.
+The hardware prefetcher can help, but it is very variable in function of the workload. If you enable it, then consider
+increasing the number of refill slots to at least 2, idealy 3.
 
 
 

master/_sources/VexiiRiscv/Memory/index.rst.txt

@@ -75,9 +75,9 @@ Here is a set of options which can be used :
    * - --lsu-l1
      - Enable the L1 D$
    * - --lsu-l1-ways=X
-     - Specify the number of ways  for the L1 D$ (how many direct mapped caches in parallel)
+     - Specify the number of ways  for the L1 D$ (how many direct mapped caches in parallel), default=1
    * - --lsu-l1-sets=X
-     - Specify the number of sets for the L1 D$ (how many line of cache per way)
+     - Specify the number of sets for the L1 D$ (how many line of cache per way), default=64
    * - --lsu-l1-mem-data-width-min=X
      - Set a lower bound for the L1 D$ data width
    * - --lsu-software-prefetch
@@ -89,9 +89,17 @@ Here is a set of options which can be used :
    * - --lsu-l1-store-buffer-slots=X
      -  Specify how many block of memory can be targeted by the store buffer (disabled/0 by default)
    * - --lsu-l1-refill-count=X
-     - Specify how many cache line refill the L1 D$ can handle at the same time
+     - Specify how many cache line refill the L1 D$ can handle at the same time, default=1
    * - --lsu-l1-writeback-count=X
-     - Specify how many cache line writeback the L1 D$ can handle at the same time
+     - Specify how many cache line writeback the L1 D$ can handle at the same time, default=1
+
+To improve the performances, consider first increasing the number of cache ways to 4.
+
+The store buffer will help a lot with the store bandwidth by allowing the CPU to not be blocked by every store miss.
+The hardware prefetcher will help with both store/load bandwidth (but if the store buffer is already enabled, it will not
+realy increase the store bandwidth).
+
+For the hardware prefetcher to stretch its leg, consider using 4 refill/writeback slots. This will also help the store buffer.
 
 
 Prefetching

master/genindex.html

@@ -284,7 +284,7 @@ <h1 id="index">Index</h1>
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/index.html

@@ -327,7 +327,7 @@ <h1>VexiiRiscv<a class="headerlink" href="#vexiiriscv" title="Permalink to this
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>
 
 

master/search.html

@@ -291,7 +291,7 @@
     <!-- source/_templates/footer.html -->
 
     <div class="doc-footer-current-version"><p>
-    Version: master git~014aa36 2024-11-26
+    Version: master git~c49000e 2024-11-26
     </p></div>