Error when trying to instantiate an entity containing a generic type (VHDL 2008)

[vdahle]

Describe the bug
When trying to instantiate an entity containing a generic type as a component, the generic map will give the error No declaration of 'my_t' (where my_t is the generic type). Furthermore the port map will give the error … does not match type 'my_t'.

To Reproduce
The following two modules should reproduce the problem (tested on 3 different systems), where the module a is initiated inside module b. Module b needs to be added to the work library.

Code
Module a:

entity a is
    generic (type my_t);
    port (
        i : in  my_t;
        o : out my_t    
    );
end entity a;
architecture rtl of a is
begin
    o <= i;
end architecture;

Module b:

entity b is 
end entity b;
architecture rtl of b is
    signal o : integer;
begin
    i : entity work.a
    generic map (
        my_t => integer
    )
    port map (
        i => 1, 
        o => o 
    ); 
end architecture;

Please complete the following information:

• OS: Windows 10 Enterprise
• VSCode version: 1.93
• TerosHDL version: 5.0.12

Screenshots
Screenshot of the errors in module b, visualised using the Error Lens Extension: